JP2001043201A - Multiprocessor fault detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily specify a CPU, in which a fault occurs, inside a multiprocessor by dumping a memory while simplifying a device configuration and reducing the device cost without providing the counters of hardware as many as CPU. SOLUTION: Updated count values 7a-7c of counters and last count values 8a-8c are comparatively evaluated by a CPU 1 for examination and on the basis of the comparatively evaluated result of the CPU 1 for examination, an abnormality detecting signal 13 of a CPU is outputted by a WDT 5. Thus, since the abnormality detecting signal of the processor can be outputted on the basis of the evaluated result between the updated count values and last count values of counters in memories, the processor, in which a fault occurs, inside the multiprocessor can be easily specified while simplifying the device configuration and reducing the device cost without preparing the counters of hardware as many as processors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor fault detecting device, and more particularly, to a watchdog timer (Wath) in a computer including a plurality of processors.
The present invention relates to a multiprocessor fault detection device that detects a fault in a processor by using a Dog Timer (WDT).

[0002]

2. Description of the Related Art Heretofore, as a method of detecting a system hang of a computer, a method using an H / W timer called WDT is known. In this hang detection method, an H / W timer called WDT is used to periodically reset the timer from 0 seconds, and when the system hangs, this timer is not reset within the set time. , Hangs can be detected.

However, in a multiprocessor computer, even if one of a plurality of processors hangs, the other processor is operating. Therefore, the execution of the program for resetting the WDT is assigned to the operable processor. In such a case, the WDT may be reset although it is not desired that the reset is performed, and a system error due to the hung processor may not be detected.

As a conventional technique for solving such a problem of detecting a system abnormality in a multiprocessor system, there is a multiprocessor fault detection system reported in Japanese Patent Application Laid-Open No. 57-55461, for example. In this conventional multiprocessor failure detection system, a monitoring counter by H / W corresponding to each processor is provided,
Each processor periodically resets the monitoring counter, thereby detecting an abnormality of each processor.

The contents of the monitoring counter are constantly counted up by a count-up circuit, and each processor periodically clears the contents of the corresponding monitoring counter at a period sufficiently shorter than the counter overflow time. If there is an abnormality in a certain processor, the corresponding content of the monitoring counter is not cleared, so that an overflow occurs and the abnormal state is displayed on the display unit.

A conventional multi-microprocessor system failure detecting device is disclosed in, for example,
No. 3169 is reported. In this conventional failure detection device, a WDT flag corresponding to each processor is provided in the shared memory, and each processor periodically sets the WDT flag, and resets the WDT in all flag sets.

[0007] The WDT flag on the shared memory is set only when each processor performs a normal operation within a predetermined operation time. Among the plurality of processors, a representative processor can check the normal / abnormal operation of other processors based on the presence / absence of the WDT flag set, and can detect a failure of the multiprocessor.

[0008]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No.
In the conventional multiprocessor failure detection method reported in Japanese Patent No. 55461, the number of hardware counters must be prepared for the number of processors, which causes a problem that the device configuration becomes complicated and the device cost increases. .

In the conventional multi-microprocessor system fault detecting device reported in the above-mentioned Japanese Patent Application Laid-Open No. 2-53169, as described above, when a fault occurs in one of the multi-processors, the WDT
The presence or absence of the flag set indicates that a failure has occurred in the multiprocessor itself.

[0010] However, when a failure occurs in a certain processor in the multiprocessor, a memory dump is generally performed and analysis is performed.
Since the flag is used, it is difficult to know which processor in the multiprocessor has failed from the memory dump, and it is difficult to specify the failed processor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and can eliminate the need to prepare hardware counters by the number of processors, thereby simplifying the apparatus configuration and reducing the apparatus cost. It is another object of the present invention to provide a multiprocessor failure detection device that can reduce the number of failed processors and can easily identify a failed processor among multiprocessors.

[0012]

According to the present invention, there is provided a multiprocessor fault detecting apparatus comprising: a plurality of processors to be inspected; a memory provided with a plurality of counters corresponding to each of the processors to be inspected; And a failure detection signal output means for outputting a failure detection signal of the processor based on a comparison evaluation result of the inspection processor. It is assumed that.

Further, the multiprocessor failure detection device has reset signal output means for outputting a reset signal when the test processor detects that the updated value of the count value and the previous value are all different values. The abnormality detection signal output means outputs an abnormality detection signal of the processor when the inspection processor detects that the updated value of the count value and the previous value are the same, respectively. .

In the multiprocessor failure detection device, the failure detection signal output means may output a failure detection signal of the processor when a failure occurs in the test processor and the reset signal is not output by the reset signal output means. It is characterized by the following.

Further, the multiprocessor failure detection device has a memory dump means for dumping the updated value of the count value of the counter and the previous value from the memory when the abnormality detection signal of the processor is output from the abnormality detection signal output means. It is characterized by the following.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a block diagram showing the configuration of the multiprocessor fault detection device according to the first embodiment of the present invention. The illustrated multiprocessor fault detection device can be applied to a computer system such as a server. In FIG. 1, reference numerals 1 to 4 denote CPUs of a system composed of a multiprocessor of N CPUs, a CPU 1 is a CPU for inspection, and CPUs 2 to 4 are Cs to be inspected.
PU.

Reference numeral 5 denotes a WDT. The WDT 5 is reset by a WDT reset signal 12 from the inspection CPU 1, and when the WDT reset signal 12 is not output from the inspection CPU 1 for a predetermined time, a CPU failure detection signal 13 Is output. 6 is each CPU 2 to be inspected
4 is a memory provided with a plurality of counters respectively corresponding to 4.

Reference numerals 7a to 7c denote count values (update values) that are updated by the counters in the memory 6 being counted up by the CPUs 2 to 4 to be inspected, respectively.
c indicates that the inspection CPU 1 has finally counted 7
This is the count value (previous value) at which each of a to 7c was read when it was read.

Reference numerals 9a to 9c denote CPUs 2 to 4 to be inspected.
To write the count values 7a to 7c of the respective counters on the memory 6 respectively. Here, the count values 7a to 7c are updated values of the updated count value.
For example, the writing 9a of the count value 7a indicates that the count value 7a of the counter on the memory 6 corresponding to the CPU 2 is written from the CPU 2 to be inspected.

Reference numerals 10a to 10c indicate that the count values 7a to 7c of the respective counters on the memory 6 are read from the inspection CPU 1 respectively. Here the count value 7a
7c are updated values of the updated count value. For example, the reading 10a of the count value 7a is performed by the inspection CP.
This indicates that the count value 7a of the counter on the memory 6 corresponding to the CPU 1 is read from U1.

Numerals 11a to 11c indicate that the count values 8a to 8c of the respective counters on the memory 6 are written and read from the inspection CPU 1 respectively.
Here, the count values 8a to 8c are the previous values counted last time with respect to the updated count values 7a to 7c.
For example, reading and writing 1 of the previous count value 7a
1a indicates that the inspection CPU 1 writes or reads the count value 8a of the counter on the memory 6 corresponding to the CPU 1.

The operation of the multiprocessor fault detecting device shown in FIG. 1 will be described below. Each CPU 2 to be inspected
Numeral 4 increments the count values 7a to 7c of the counters provided on the memory 6 by one at regular intervals. For example, the CPU 2 to be inspected increases the count value 7a of the corresponding counter on the memory 6 by one at regular intervals,
The CPU 3 to be inspected increases the count value 7b of the corresponding counter on the memory 6 by one at regular intervals.

The inspection CPU 1 compares and checks the count values 7a to 7c of the updated values of the counters in the memory 6 with the count values 8a to 8c of the previous values, and determines that the updated value of the count value is different from the previous value. When it is determined, the count values 7a to 7c of the different update values are changed to the count values 8a to 8
8c. For example, the update value count value 7a
Is copied to the previous count value 8a.

The inspection CPU 1 compares and checks the count values 7a to 7c of the updated values of the counters in the memory 6 with the count values 8a to 8c of the previous values. If it is determined that the value is different, a WDT reset signal 12 is output to WDT5. W
DT5 is reset by the WDT reset signal 12.

The inspection CPU 1 compares and checks the count values 7a to 7c of the updated values of the counters in the memory 6 with the count values 8a to 8c of the previous values. If any one of the updated values and the previous count value is determined to be the same, the WDT reset signal 12 is not output to the WDT 5.

When a fault occurs in the CPUs 7a to 7c to be inspected, the updated value of the corresponding counter in the memory 6 is not updated, so that the updated value becomes the same as the previous value. In such a case, the inspection CPU 1 does not output the WDT reset signal 12 to the WDT 5.

The WDT 5 is transmitted from the inspection CPU 1 to the WDT 5.
When a preset time elapses without outputting the reset signal 12, an abnormality detection signal 13 of the CPU is output. Then, the system uses the abnormality detection signal 13 of the CPU to display on a display unit (not shown) that a failure has occurred in the CPU, and notifies the system administrator of the abnormality of the CPU.

When a failure occurs in the CPU 1 for inspection, the WDT reset signal 12 from the CPU 1 for inspection
Not output to DT5. In such a case, WDT5
Since the WDT reset signal 12 is not acquired from the inspection CPU 1 even after the preset time has elapsed, the CPU abnormality detection signal 13 is output. Similarly, the system:
In response to the CPU abnormality detection signal 13, the fact that a failure has occurred in the CPU is displayed on a display unit (not shown) or the like to notify the system administrator of the CPU abnormality.

In addition to displaying the abnormality of the CPU on the display unit, the system administrator may be notified by lamp display, or may be notified by sound, buzzer sound, or the like to the system administrator. May be. Further, the system may be configured so that the system abnormality is notified not only to the system administrator itself but also to a remote monitoring terminal by communication.

Here, a method for specifying which of the CPUs 1 to 4 has actually failed when the WDT 5 outputs the CPU abnormality detection signal 13 will be described. C by WDT5
When the PU abnormality detection signal 13 is output, the updated value of the count value of the counter in the memory 6 and the previous value are dumped from the memory 6 in order to analyze the contents of the memory 6 for a failure.

If the count values 7a to 7c of the updated values of the counters in the memory 6 are larger than the previous count values 8a to 8b, the CPUs 2 to 2 for the inspection are checked.
Since no failure has occurred in No. 4, it can be seen that a failure has occurred in the CPU 1 for inspection.

It is assumed that the count values 7a to 7c of the updated values of the counters in the memory 6 correspond to the previous count values 8a to 8c.
b, if there is an updated value having the same value and the CPU to be inspected corresponding to the previous value
It can be seen that two to four have failed. In this way, the failed CPUs 1-4 can be identified by dumping the memory 6.

As described above, in this embodiment, the count values 7a to 7a of the updated counter are
7c is compared with the previous count value 8a to 8c of the counter, and the WDT 5 is used to output the CPU abnormality detection signal 13 based on the comparison evaluation result of the CPU 1 for inspection. CPU abnormality detection signal 1 based on the updated value of the value and the evaluation result of the previous value
3 can be output. For this reason, it is possible to simplify the device configuration and reduce the device cost without preparing hardware counters by the number of CPUs, and replace the failed CPU in the multiprocessor with the memory 6.
Can be easily specified by dumping.

In this embodiment, the CPU 1 for inspection is used.
When the CPU 1 detects that the updated value of the count value of the memory 6 and the previous value are all different values, it outputs a WDT reset signal 12 to the WDT 5, and the CPU 1 for inspection checks the updated value of the count value of the memory 6 with the updated value. Since the WDT5 outputs the CPU abnormality detection signal 13 when it is detected that each of the previous values is the same value, WD
The output of the T reset signal 12 indicates that a failure has not occurred in the CPU, and the output of the abnormality detection signal 13 of the CPU can notify the system administrator that a failure has occurred in the CPU. Moreover, by dumping the contents in the memory, it is possible to specify that a failure has occurred in the CPU to be inspected corresponding to the counter of the updated value of the same value and the count value of the previous value.

In this embodiment, the inspection CPU is used.
If the WDT reset signal 12 is not output from the inspection CPU 1 due to the failure of the
When the contents of the memory 6 are dumped, a failure occurs in the inspection CPU 1 because the updated value of the count value and the previous value are all different values. Can be identified.

Further, in this embodiment, when the WDT 5 outputs the CPU abnormality detection signal 13, the memory 6
Since the updated value of the count value of the counter and the previous value are dumped from the memory 6, it is possible to specify which CPU in the multiprocessor has a fault. If the updated value of the corresponding count value of the counter of the memory 6 and the previous value have the same value, a failure occurs in the CPUs 2 to 4 corresponding to the updated value of the same value and the counter of the previous count value. It can be specified that it has occurred. If the updated value of the count value in the memory 6 and the previous value are all different values, it can be specified that a failure has occurred in the test processor 1.

[0037]

According to the present invention, a plurality of processors to be inspected, a memory provided with a plurality of counters corresponding to each processor to be inspected, the updated counter value and the previous counter An inspection processor for comparing and evaluating the count value, and an abnormality detection signal output unit for outputting an abnormality detection signal of the processor based on a comparison and evaluation result of the inspection processor, wherein the counter updated by the inspection processor By comparing and evaluating the count value of the counter with the count value of the previous counter, and outputting the abnormality detection signal of the processor by the abnormality detection signal output means based on the comparison and evaluation result of the processor for inspection, Since the processor error detection signal can be output based on the updated count value of the counter and the evaluation result of the previous value, Without preparing counter hardware the number of processors, while realizing a reduction in simplified and the apparatus cost of the device configuration, a processor failure has occurred in the multi-processor can be easily specified.

When the test processor detects that the updated value of the count value and the previous value are all different values, a reset signal is output by the reset signal output means, and the count value is output by the test processor. When it is detected that the updated value and the previous value are the same, the abnormality detection signal output means outputs the abnormality detection signal of the processor. Thus, it is possible to notify the system administrator that a failure has occurred in the processor by outputting the abnormality detection signal of the processor. Moreover, by dumping the contents in the memory, it is possible to specify that a failure has occurred in the processor to be inspected corresponding to the counter of the updated value of the same value and the count value of the previous value.

Further, when a failure occurs in the test processor and the reset signal is not output by the reset signal output means, the abnormality detection signal output means outputs an abnormality detection signal of the processor, so that the content of the memory can be improved. Is dumped, the updated value of the count value and the previous value are all different values, so that it is possible to specify that a failure has occurred in the test processor.

When the abnormality detection signal output means outputs a processor abnormality detection signal, the memory dump means dumps the updated value of the count value of the counter and the previous value from the memory. It is possible to specify which of the processors has a fault. If the updated value of the corresponding count value of the counter and the previous value have the same value, a failure has occurred in the CPU to be inspected corresponding to the counter of the updated value of the same value and the count value of the previous value. Can be specified. If the updated value of the count value and the previous value are all different values, it can be specified that a failure has occurred in the test processor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor fault detection device according to a first embodiment of the present invention.

[Explanation of symbols]

1 CPU for inspection, 2 to 4 CPUs to be inspected, 5
WDT, 6 memories, 7a-7c count value (update value), 8a-8c count value (previous value), 9a-9c
Write count value, 10a-10c Read count value, 11a-11c Read and write previous count value, 12 WDT reset signal, 13 C
PU failure detection signal.

Claims (4)

[Claims] 1. A processor provided with a plurality of processors to be inspected, a memory provided with a plurality of counters corresponding to each processor to be inspected, and a count value of an updated counter and a count value of a previous counter are compared and evaluated. A multiprocessor failure detection device, comprising: a processor for inspection; and an abnormality detection signal output unit that outputs an abnormality detection signal of the processor based on a comparison evaluation result of the processor for inspection. 2. The multiprocessor fault detection device according to claim 1, wherein a reset signal is output when the test processor detects that the updated value of the count value and the previous value are all different values. A reset signal output unit configured to output an abnormality detection signal of the processor when the inspection processor detects that the updated value of the count value and the previous value are the same value. A multiprocessor failure detection device characterized by the following. 3. The multiprocessor failure detection device according to claim 1, wherein the failure detection signal output means outputs the error signal to the processor when a failure occurs in the test processor and the reset signal is not output by the reset signal output means. A multiprocessor failure detection device that outputs an abnormality detection signal. 4. The multiprocessor failure detection device according to claim 1, wherein when the abnormality detection signal output means outputs an abnormality detection signal of the processor, the updated value of the count value of the counter and the previous value are stored in the memory. A multiprocessor fault detection device comprising a memory dump unit for dumping.