JPH0415825A - Micro branch processing system - Google Patents

Abstract

PURPOSE:To increase the system processing speed and to improve the general usefulness by providing a logic circuit which generates a signal which executes the branch processing by AND among a flag, a branch code, and a branch condition code field. CONSTITUTION:The address of a CROM 7 (memory) is accessed by a machine language instruction 1, and a decoder 9 decodes a select signal used for execution of the branch processing of a micro instruction 3. A selector 13 selects a flag corresponding to the branch processing of the micro instruction 3 from a flag group of condition flags 11 in accordance with this select signal, and a logic circuit 15 generates a signal which executes the branch processing by AND among the selected flag, the branch code of the micro instruction 3, and a branch condition code field BCF decoded by the decoder 9. Thus, the extension of the area of the branch condition code field is prevented, and the processing speed of the system is increased and the general usefulness is improved.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention particularly relates to a micro-branch processing method that executes a branch processing using a micro-instruction specified by an instruction code of a machine language instruction. The present invention relates to a micro-branch processing method that improves system processing speed by reducing the area of a branch condition code field.

(Prior Art) The above-mentioned micro-branch processing method will be explained with reference to FIGS. 3 and 4.

First, when executing branch C of instruction W in FIG. 3, machine language instruction 25 specifies microinstruction 27 by an instruction code. The specified microinstruction 27 refers to the branch code and branch condition code field (hereinafter referred to as BCF), and when the branch code is set to "1" indicating the presence of branch processing, the fifth BCF is specified. The decoder 29 decodes ro 010J of branch C of the branch condition shown in the figure. On the other hand, a condition flag 31 indicating conditional elements of branch processing set by firmware
C is set to "1" when the branch code is present. The condition flag 31 is "1".

When the branch code is "1" and BCF is ro 010J, the AND circuit 33C becomes high level and the reor circuit 35 also becomes high level, so that the branch execution signal (BrGO
signal) is generated. Similarly, other instructions w, x, y, z
15 types of branch processing, including branches A, B, and DP, are executed. When handling many types of branch processing, it is not easy to suppress the increase in the number of pids in the BCF.

(Problem to be solved by the invention) The conventional micro branch processing method is based on the BCF of micro instructions.
Since 4 bits are used for
The increase in the number of bits used for F also increases the memory capacity used for BCF. If the memory capacity used by the BCF increases, the memory capacity used for firmware that stores microinstructions will decrease, which may impede the processing of the firmware or cause a delay in processing speed. there were.

The present invention has been made in view of the above, and its purpose is to prevent the area of the branch condition code field from increasing even when processing many types of branch processing, and to save the area where the increase is prevented. It is an object of the present invention to provide a micro-branch processing method that improves the processing speed and versatility of a system by executing parallel operations using other processing.

Configuration of the Invention C (Means for Solving the Problems) In order to achieve the above object, the present invention provides a branch condition code field indicating a condition for branch processing of a microinstruction specified by an instruction code of a machine language instruction. A memory that stores a select signal for selecting an element of a branch condition in a process, a decoder that decodes a select signal used to execute a branch process by the microinstruction among the select signals stored in this memory, and this decoder. a selector that selects a flag corresponding to the branch processing of the microinstruction from a group of conditional flags indicating the establishment of the branch processing in response to a select signal decoded from the microinstruction; The present invention further comprises: a logic circuit that generates a signal for executing a branch process based on a logical product of a branch code and a branch condition code field indicating whether or not a branch process is to be performed.

(Operation) In the micro branch processing system having the above configuration, the select signal used to execute the branch processing of the microinstruction is decoded from among the select signals that select the element of the branch condition among the branch processing stored in the memory. do. In response to this decoded select signal, a flag corresponding to the branch processing of the microinstruction is selected from the flag group of condition flags. The signal to execute the branch processing is generated by the AND of the selected flag, the branch code indicating whether or not branch processing is to be performed for the microinstruction, and the branch condition code field indicating the conditions for the branch processing, so the branch condition code field area can be reduced.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the micro-branch processing method of the present invention.

In the micro-branch processing method described above, for example, micro-instruction 3 of instruction W of each micro-instruction shown in FIG. 3 is specified by an instruction code indicating the type of instruction of machine language instruction 1. The specified microinstruction 3 is a 1-bit branch code (
B C) and 2 B,.

Branch condition code field (hereinafter referred to as BC)
It's called F. ). The branch code is set to "1" when the branch processing instruction W is present, and "0" when the branch processing instruction W is absent.

In addition, the BCF is the corresponding BC shown in Table 21 in Figure 2 (a).
16 of branch A-P of branch condition indicating the state of F
When the branch is rAJ, it is "00", when it is branch B, it is "01", and when it is branch, it is "11". Similarly, the branch is E.

When it is 1 or M, it is "00" and the branch processing is H or L.

When P, it is "11".

Returning to FIG. 1, the branch condition set in the 2 bits of the BCF is decoded by the decoder 5, and
It is output to AND circuits 17a to 17d, which will be described later.

The CROM 7 (memory) has in advance 2-bit data of the branch condition code field shown in Table 23 shown in FIG. 2(b) in response to the instruction code specified by the machine language instruction 1. That is, branch A-D is r
ooJ, branch E-H is rolJ, branch I-L is rlOJ
, branch M-P is "11".

The decoder 9, for example, uses the instruction W of the microinstruction shown in FIG.
In the case of branch C, the address of CROM 7 is accessed by the instruction code of machine language instruction 1, and the address shown in Table 2 is
Decode “00” of 3.

The condition flag 11 corresponds to branch A-P, A to D, and E.
It has four groups of flags -H, I to L, and MP. For example, in the case of instruction C of the above-mentioned instruction W, flag C is set to "1" among flags A to D.

The selector 13 is connected to AND circuits 17a to 17d, which will be described later, and selects the select signal of flags A to D from the flag group of the condition flags 11 based on the "00" select signal decoded by the decoder 9 to the AND circuits 17a to 17d. 17
Output to d.

Logic circuit 15 includes AND circuits 17a to 17d and OR circuit 19. The AND circuits 17a to 17d are
They are connected to the branch code of the microinstruction 3, the decoder 5, and the selector 13, respectively. For example, when executing branch C of instruction W, the branch code is "1" and the decoder 5
is "1o", and the select signal from the selector 13 causes the AND circuits 17a to 17d to go high level.

When the AND circuits 17a to 17d become high level, the OR circuit 19 outputs a branch execution signal (BrG
O signal) is generated.

Next, the operation of this embodiment will be explained.

First, after starting the system, when executing branch C of instruction W pointed to by machine language instruction 1, the instruction code of machine language instruction 1 is
Access the address of CROM 7 and write “0” to decoder 9.
0” is decoded. The decoder 9 selects the decoded rooJ to the selector 13 and sets the condition flag 1.
The select signal of the corresponding flag A-D of 1 is output to the AND circuit. The microinstruction 3 specified by the instruction code of the machine language instruction 1 refers to the branch code and the BCF and decodes "1o" in the BCF to the decoder 5.

When the AND circuits 17a to 17d of the logic circuit 15 reach a higher level than the logical product of the branch codes F and BCF of the microinstruction 3 and the selector 13, the OR circuit 19 also becomes a high level, and the branch execution signal of the branch C of the instruction W ( BrGO signal)
generate.

Similarly, for example, when executing branch H of instruction Y, CR
"11" is decoded by the decoder 9 from OM7, flag E of the condition flag 11 is set to "1", and selected by the selector 13. Then, the branch code is set to "1", the BCF is set to "01", and the OR circuit 19 generates a branch execution signal for branch H of instruction Y. Other branch processing is also processed according to the procedure described above.

This reduces the number of BCF bits from the conventional 4 bits to 2.
Since the reduced number of bits can be applied to other branch processing, it is possible to perform a wide variety of branch processing.

Furthermore, by applying the reduced bits to another process, parallel operations can be made possible and the versatility of the system can be improved.

As described above, the present invention can be implemented with various modifications within the scope of the invention.

[Effects of the Invention] As explained above, according to the present invention, even when processing many types of branch processing, an increase in the area of the branch condition code field is prevented, and the area where the increase was prevented is transferred to another area. By using the system to perform parallel operations, it is possible to improve the processing speed of the system and improve its versatility.

[Brief explanation of drawings]

FIG. 1 is a blower diagram showing the configuration of an embodiment of the micro-branch processing method of the present invention, FIG. 2 is a diagram showing the state of the branch condition code field of the present invention, and FIG. The flowcharts shown in FIGS. 4 and 5 are diagrams showing a conventional micro-branch processing method. 1... Machine language instruction 3... Micro instruction 5.9... Decoder 7... CROM 13... Selector 15... Logic circuits 17a to 17d... Ann 19... OR circuit de circuit

Claims (1)

[Scope of Claims] A branch code indicating whether branch processing is to be performed for a microinstruction specified by an instruction code of a machine language instruction, and a branch condition code field indicating conditions for the branch processing;
A micro branch processing method having a condition flag of a flag group indicating an element of a branch condition of the branch processing, a memory for storing a select signal for selecting an element of the branch condition among the branch processing of the branch condition code field; A decoder that decodes a select signal used for execution of branch processing by the microinstruction among the select signals stored in the memory; a selector that selects a flag applicable to branch processing of an instruction; a logic circuit that generates a signal for executing branch processing by ANDing the flag selected by the selector, a branch code of the microinstruction, and a branch condition code field; A micro-branch processing method characterized by: