JPH04157572A - Correction system for interactive arrangement - Google Patents

Abstract

PURPOSE:To prevent high TAT(man-hours) from being requested for delay analysis and correction by using a method to perform the delay analysis immediately after the completion of arrangement. CONSTITUTION:This system is equipped with a control means 1, a router constant ratio/arrangement information/connection bus information/delay constraint information input means 2, a bus wiring length calculation means 3, a delay analysis means 4, a violence bus detection means 5, a violence bus block display means 6, an arrangement correction means 7, a router constant ratio storage means 8, an arrangement information storage means 9, a connection bus information storage means 10, and a delay constraint information storage means 11. Since the delay analysis is performed by a value near to real wiring length immediately after the completion of arrangement by using a ratio value (constant ratio) of virtual wiring length at every router obtained by past experience to the real wiring length, violence bus and block can be immediately recognized, and arrangement correction can be performed. In such a way, it is possible to reduce the man-hours to return processing to arrangement processing again by performing the arrangement processing and the delay analysis.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interactive layout correction system for LSIs, printed circuit boards, etc.

[Conventional technology]

Traditionally, this type of interactive placement modification method uses
Since the method of performing delay analysis immediately after the completion of placement was not used, delay analysis was performed after actually attempting the wiring process.
As a result of analysis, if there is a path that violates the delay constraint,
It was necessary to go back to the placement process and correct the placement of the block on the violating path.

References include “Logical Device CADj (Information Processing Society of Japan)”
can be mentioned.

[Problem to be solved by the invention]

In the conventional interactive placement correction method described above,
Since delay analysis cannot be performed with only placement information, it is necessary to perform wiring processing.Also, if a violation path is found as a result of delay analysis, the initial placement is necessary to correct the placement again while viewing the results in a list etc. The feedback loop from the draft to the revision is large and requires a huge TAT for delay analysis and revision (
The disadvantage is that it takes a lot of man-hours.

Means for Solving the Two Problems] The interactive placement correction method of the present invention includes a router fixed rate storage means for storing the ratio between the virtual wiring length and the actual wiring length for each router, which has been aggregated from past results. , a placement information storage means for storing block placement information, a connection path information storage means for storing connection path information between each block,
a delay constraint information storage means for storing delay constraint information of a path; an information input means for reading router fixed rate, placement information, connection path information, and delay constraint information; A path wiring length calculation means calculates the virtual wiring length of the path by multiplying by a constant ratio of .A delay analysis means performs delay analysis based on the calculated wiring length. The method includes a violation path detection means for detecting a violation path, a violation path block display means for highlighting the violation path and the blocks constituting it, and a placement correction means for interactively correcting the placement of the highlighted block. .

〔Example〕

, FIG. 1 shows a block diagram of an interactive layout correction method that is an embodiment of the present invention. This processing consists of several processing procedures, which are controlled by the control means l.

First, the information input means 2 reads the constant rate for each router obtained from past results, placement information, connection path information, and delay side "contract information", and each router constant rate storage means 8. Placement information storage means 9. Connection information storage. The delay constraint information is stored in the means 10 and the delay constraint information storage means 11.

Next, the path wiring length calculation means 3 calculates the Manhattan length of the net constituting each path, and multiplies it by the fixed rate of the interactively selected router to obtain the path wiring length.

Delay analysis means 4 performs delay analysis based on the determined path wiring length, and violation path detection means 5 detects a path that violates the delay constraint. The detected violation path and the blocks connected thereto are highlighted by violation path block display means 6.

The highlighted block is interactively selected and the arrangement of the block is corrected by the arrangement correction means 7. Delay analysis is performed again on the path of the block that has been moved due to the placement correction, and if the delay constraint is satisfied, the display of the violating path is deleted.

FIG. 2 is an example of displaying blocks and their connection path information.

As shown in FIG. 2(a), blocks 101 and 102°1
09.107 is connected by path 301. Similarly, blocks 105, 106, 103° 104 are connected by path 302, and blocks 105, 108, 1
10 and 111 are connected by a path 303.

First, the information input means 2 reads this information as well as fixed rate and delay constraint information for each router obtained from past performance, and stores them respectively in the router fixed rate storage means 8 and the arrangement information storage means 9.
．． Connection path information storage means 10, delay constraint information storage means 1
Store in 1.

Next, the path wiring length calculation means 3 calculates the Manhattan length of the net constituting each path, and multiplies it by the fixed rate of the interactively selected router to obtain the path wiring length.

As a result of the delay analysis performed by the delay analysis means 4 based on the obtained path wiring length, the paths 301 and 303 that violate the delay constraints are detected by the violation path detection means 5, and the violation path block display means 6 displays paths 301. 303 and blocks 101, 102゜109, 107, 105, 108, 1
10 and 111 are highlighted (FIG. 2(b)).

The arrangement correction means 7 selects block 111 from among these blocks and exchanges the arrangement with block 114, and similarly selects block 107 and exchanges arrangement with block 112. As a result, paths 301 and 303 are delayed respectively. The constraints are now satisfied, the violation path and block display disappear, and the placement result shown in FIG. 2(c) is obtained.

〔Effect of the invention〕

As explained above, the present invention uses a ratio value (constant ratio) between the virtual wiring length and the actual wiring length for each router obtained from past experience.
By using , it is possible to perform delay analysis with a value close to the actual wiring length immediately after the placement is completed, so there is an advantage that the violating path and its blocks can be immediately identified and the placement can be corrected. That is, it is possible to reduce the TAT (man-hour) required to perform wiring processing, delay analysis, and return to placement processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interactive layout correction method according to an embodiment of the present invention, and FIG. 2(a) is a block diagram of an interactive layout correction method. FIG. 2(b) and FIG. 2(c) are diagrams showing the arrangement modification of the present invention. 1... Control means, 2... Router fixed rate,
Arrangement information, connection path information, delay constraint information input means, 3.
. . . Path wiring length calculation means, 4 . . Delay analysis means, 5 . . . Violation path detection means, 6 . .
...Violation passb p. display means, 7... arrangement correction means, 8...
. . . Router fixed rate storage means, 9 . . . Placement information storage means, IO . . . Connection path information storage means, 11.
...Delay constraint information storage means. Agent Patent Attorney Uchihara Otoden 1 z IOf~IIIJ Near °D-/7 -1) / + t l”X (1”, DH47,:
￥ -10Z -m 9-a 7F! ), sentence and 11'
, K (1”D-,7IO!-/(g-103-101
1B) Conclusion 11ζI\1 Standing: Iλ (fi(:J, -47f5-108-/10
4/E) Yi 2 0(Q) 101~1f4: Aro/7. t) / 30J: Different, fχ nest 2 Figure (b) far-/F4; 7'lots 7 jγ~303: H° Z diagram (Z)

Claims (1)

[Claims] In an interactive placement correction method for blocks that are placement units for LSIs, printed circuit boards, etc., the ratio between the virtual wiring length and the actual wiring length for each router, which has been aggregated from past results, is stored. a router constant rate storage means for storing block placement information; a connection path information storage means for storing connection path information between each block; and a delay constraint information storage means for storing path delay constraint information. and an information input means for reading the router fixed rate, placement information, connection path information, and delay constraint information, and the virtual wiring length of the path is calculated by multiplying the Manhattan length of the net constituting each path by the selected router fixed rate. a path wiring length calculation means; a delay analysis means for performing delay analysis based on the calculated wiring length; a violation path detection means for detecting a path that violates a delay constraint as a result of the analysis; What is claimed is: 1. An interactive placement correction method comprising: a violation path block display means for highlighting blocks constituting the block; and a placement correction means for interactively correcting the placement of the highlighted blocks.