JPH04157557A - Memory protecting method - Google Patents

Abstract

PURPOSE:To obtain a memory protecting method with small in circuit scale and in which no system reset is performed while shared memory is being accessed by attaching a priority decision circuit. CONSTITUTION:When a system reset signal is inputted to a system reset control signal 10-3, a main bus master 10 sends a preset signal to a bus acquisition circuit 10-2 at a time when no system bus is used by using the priority decision circuit 10-6, and a bus request signal is outputted, and a bus use permission signal can be obtained, thereby, all the sub bus masters 1, 2... can recognize the nonuse of the system bus. Since no access to the shared memory 11 is performed at that time, the system reset signal is sent to the main bus master 10 and the sub bus masters 1, 2,.... In such a way, the circuit scale can be reduced, and the system reset can be prevented from being performed while the shared memory is accessed.

Description

[Detailed Description of the Invention] [Summary] A processor, a bus acquisition circuit that outputs a bus use request signal when a bus acquisition command is input from the processor, and a main bus master and all secondary bus masters when a system reset command is input. The main bus master has a system reset control circuit that outputs a system reset signal to the main bus master, and the sub bus master has a plurality of processors and bus acquisition circuits.
A master and a shared memory are connected by a system bus, and when each bus master uses the system bus to access the shared memory, each bus acquisition circuit sends a bus use request signal to the bus. A multi-bus system that accesses the shared memory after receiving a bus use permission signal from the control unit.
Regarding the memory protection method for master type systems, the purpose is to provide a memory protection method that has a small circuit scale and does not cause a system reset while accessing shared memory. Upon receiving the command, it outputs a pre-reset signal requesting acquisition of the system bus, outputs a system reset signal after inputting the bus use permission signal, and also outputs a bus acquisition request signal from the processor and the corresponding pre-reset signal. A pre-reset signal from a system reset control circuit is input, and if a bus acquisition request signal is input first, the output of the bus acquisition request signal by the pre-reset signal to the bus acquisition circuit is suspended until there is no more input; A priority determination circuit is provided which suspends the output of the bus acquisition request signal if the pre-reset signal is input first and outputs the bus acquisition request signal by the pre-reset signal, and when the system reset command is input to the system reset control circuit. , outputs a bus acquisition request signal based on a pre-reset signal to the priority determination circuit, and in the priority determination circuit, if the bus acquisition request signal is input first, the bus acquisition request signal is outputted as soon as the bus acquisition request signal disappears. If the signal is not input, at the time of inputting the pre-reset signal, input the bus acquisition request signal by the pre-reset signal to the bus acquisition circuit, output the bus acquisition request signal, and obtain the bus use permission signal from the bus control unit. At that point, the system reset control circuit is configured to output a system reset signal to the main bus master and all sub-bus masters.

[Industrial application field]

The present invention includes a processor, a bus acquisition circuit that outputs a bus use request signal when a bus acquisition command is input from the processor, and a system reset signal that outputs a system reset signal to a main bus master and all sub-bus masters when a system reset command is input. A main bus master having a system reset control circuit, a plurality of sub bus masters having a plurality of processors and a bus acquisition circuit, and a shared memory are connected by a system bus, and each bus master is connected to the shared memory by a system bus. When using the system bus to access the shared memory, each bus acquisition circuit sends a bus use request signal to the bus control unit, obtains a bus use permission signal, and then accesses the shared memory.
In a master type system, when the main bus master outputs a system reset signal to the main bus master and all sub bus masters,
This invention relates to an improvement in a memory protection method that resets the shared memory after access is completed in order to prevent data destruction.

[Conventional technology]

FIG. 3 is a block diagram of an example system, and FIG. 4 is a block diagram of a conventional main bus master and sub-bus master.

A multi-bus master type system, as shown in FIG. 3, has main bus masters 10. A shared memory 11 that stores communication data between the sub-bus masters 1゜...n and the bus masters,
connected to the system bus 13, each bus master 10,1
．． . . n acquires the system bus 13, it sends a bus use request signal BRQ to the bus control unit 12.

The bus control unit 12 determines the priority of bus use requests (normally, the first input is given priority), and assigns the system bus 13 to a bus master with a higher priority so that the system bus 13 is used by a single bus master. A bus use permission signal BACK is sent to the host.

The bus master receiving the use permission signal BACK is enabled to access the system bus 13, such as to access the shared memory 11.

In this system, a primary bus master 10 and a secondary bus master 1 . ...outputs a system reset signal to n,
When a reset is performed, each bus master 10, 1 .・
- It is necessary to protect the memory so that it is not reset while n is accessing the shared memory 11.

For this purpose, conventionally, the main bus master 10 is configured as shown in FIG. 4(A), and the sub bus masters l-n are configured as shown in FIG. 4(B).
).

In FIGS. 4(A) and 4(B), processors 10-1. of main bus master 10. For example, when the processor 11-1 of the sub-bus master l uses the system bus 13, it outputs the bus use request signal HDRQ to the bus acquisition circuit 10-2.11-2. -2 outputs bus use request signals BRQI and BRQ2 to the bus control unit 12.

Bus acquisition circuit 10-2.11-2 receives bus use permission signal B
Upon receiving ACKI and BACK2, the processor 10-
1.11-1 will use the system bus 13.

The main bus master 10 has a system reset control circuit 10
-5, and when a system reset command is input from the processor l0-1 or a manual switch, the system reset control circuit 10-5 controls the processors 10-1 . l l-
1,...-1n-1, a system reset signal is output.

The main bus master 109 and the sub bus masters 1 to n are provided with memory protection circuits 10-4, 11-4°, and In-4 to prevent resets during access to the shared memory 11. .

The memory protection circuits to-4, 1l-4, . . . 1n-4 receive bus use request signals BRQI, BRQ2@... and bus use permission signal BACK1 from the processors 10-1, 11-1 to In-1, respectively. ．． BACK2... is input, bus use request signal BRQ, bus use permission signal BACK
It is determined whether the system bus 13 is being used, and if it is, it is determined that the bus use is complete when the bus use request signal BRQ becomes null (when the shared memory 11 is not accessed). , system reset signals are sent to the processors lO-1, 11-1=ln-1, respectively, to perform system reset.

By doing this, the system will not be reset while the shared memory 11 is being accessed (this will protect the memory).

[Problem to be solved by the invention]

However, the primary bus master 10. Sub-bus master
~n requires a memory protection circuit, which poses a problem of increasing the circuit scale of the multi-bus master type system.

An object of the present invention is to provide a memory protection method in a multi-bus master type system that has a small circuit scale and that does not cause a system reset during shared memory access.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, there is a processor 10-1, a bus acquisition circuit 10-2 which outputs a bus use request signal when a bus acquisition command is input from the processor 10-1, and a main bus master circuit 10-2 which outputs a bus use request signal when a system reset command is input. a main bus master 10 having a system reset control circuit 10'-3 that outputs a system reset signal to all sub-bus masters 1, 2, . . .;
Master l, 2. - The fist and the shared memory 11 are connected by a system bus 13, and each bus master 10. I, 2. When using the system bus 13 to access the shared memory 11, each bus acquisition circuit sends a bus use request signal to the bus control unit 12, obtains a bus use permission signal, and then uses the system bus 13 to access the shared memory 11. In the main bus master 10 of the multipath master type system that accesses the shared memory 11, upon receiving the system reset command, the system reset control circuit 10-3 outputs a pre-reset signal requesting acquisition of the system bus. Also, the system reset signal is output after the bus use permission signal is input, and the bus acquisition request signal from the processor 10-1 and the pre-reset signal from the system reset control circuit 10-3 are input, and the bus use permission signal is input. If the acquisition request signal is input first,
The output of the bus acquisition request signal by the pre-reset signal to the bus acquisition circuit 10-2 is suspended until there is no input, and if the pre-reset signal has been input first, the output of the bus acquisition request signal is suspended and the pre-reset signal is output. A priority determination circuit 10-6 is provided which outputs a bus acquisition request signal based on the pre-reset signal, and when a system reset command is input to the system reset control circuit 10-3, the priority determination circuit 10-6 outputs a bus acquisition request signal based on the pre-reset signal. and the priority determination circuit 1O
-6, if the bus acquisition request signal has been input first, the time when access to the shared memory 11 is finished and the bus acquisition request signal disappears; if the bus acquisition request signal has not been input, the time when the pre-reset signal is input. inputting a bus acquisition request signal based on the pre-reset signal to the bus acquisition circuit 1O-2, causing the bus acquisition request signal to be output;
When the bus use permission signal is obtained from the bus control unit 12, the system reset control circuit 1O-3 outputs a system reset signal to the main bus master 1G and all the sub bus masters l, 2°, etc. I'll do what I do.

[For production]

According to the invention, the processor 10 of the primary bus master 10
-1 or a system reset command is input to the system reset control circuit 10-3 from the outside, the system reset control circuit 10-3 outputs a pre-reset signal requesting bus use to the priority determination circuit 10-6.

In the priority determination circuit 10-6, if the bus acquisition request signal is inputted first, when the shared memory 11 is accessed and the bus acquisition request signal disappears, if the bus acquisition request signal is not inputted, the priority determination circuit 10-6 At the time of inputting the reset signal, inputting a bus acquisition request signal based on the pre-reset signal to the bus acquisition circuit 1O-2, causing the bus acquisition request signal to be output;
At the time when the bus use permission signal is obtained from the bus control unit 12, the system reset control circuit 10-3 sends the system reset signal to the main bus master 10 and all the sub bus masters l, 2. Make it output to...

That is, when the system reset signal is input to the system reset control circuit 10-5, the main bus master 10 uses the priority determination circuit 10-6 to transmit the pre-reset signal to the bus acquisition circuit when the system bus is not in use. 10-2
, outputs a bus use request signal, and obtains a bus use permission signal, thereby all secondary bus masters l, 2. ... is not using the system bus, and since the shared memory 11 is not being accessed at this point, the system reset signal is sent to the main bus master 10. Sub bus master 1
．． 2. ...Send to -.

In this way, it is not necessary to provide a memory protection circuit for each bus master, and the system reset control circuit 10-3 of the main bus master 10 can be improved and the priority determination circuit 10-6
Since memory protection can be achieved by adding , the circuit configuration of a multi-bus master type system capable of memory protection can be reduced in size.

〔Example〕

FIG. 2 shows a main bus master and a sub bus master according to an embodiment of the present invention.
FIG. 2 is a block diagram of a master.

In the present invention, the main bus master 1o in FIG. 3 is replaced with the main bus master 1o in FIG.
), and the sub bus masters l to n are configured as shown in FIG. 2(B) without a memory protection circuit but with a processor 11-1 and a bus acquisition circuit 11-2,
The system reset signal is directly input to the processor 11-1, and upon input, the system is reset.

In FIG. 2(A), the system reset control circuit 10-3
When a system reset command is received from the processor 10-1 or a manual switch, a pre-reset signal requesting acquisition of the system bus is output, and a system reset signal is output after a bus use permission signal is input.

Also, a bus acquisition request signal HDRQ from the processor 10-1
and the pre-reset signal RFL for the bus acquisition request from the system reset control circuit 1o-3 is input, and if the bus acquisition request signal HDRQ is input first, the bus acquisition request signal by the pre-reset signal RFL is input until the bus acquisition request signal HDRQ is inputted. If the output to the bus acquisition circuit 10-2 is suspended and the pre-reset signal RFL is input first, the bus acquisition request signal HD
A priority determination circuit 10 is provided which suspends the output of RQ and outputs a bus acquisition request signal based on a pre-reset signal RFL.

Normally, bus acquisition request signal H from processor l0-1
When DRQ is input to the priority determination circuit 10-6, the priority determination circuit 10-6 outputs a bus acquisition request signal IRQ, which is sent to the AND circuit 21 and the OR circuit 20, and the bus acquisition request signal IRQ is sent to the AND circuit 21 and the OR circuit 20. A bus use request signal BRQI is sent to the acquisition circuit l0-2 and output to the bus control unit h12.

Then, when the bus use permission signal BACK1 is input, the bus acquisition circuit 10-2 transfers the bus use permission signal to the AND circuit 2.
1.22, the bus use permission signal HDAK is sent from the output of the AND circuit 21 to the processor 10-1, and the processor 0-1 uses the system bus 13 to access the shared memory 1.

When a system reset command is input to the system reset control circuit 10-3 by the processor TO-1 or a manual switch, a bus acquisition request signal based on the pre-reset signal RFL is sent to the priority determination circuit 1O-6.

In the priority determination circuit 10-6, the bus acquisition request signal HDRQ
If the bus acquisition request signal HDRQ is inputted first, the pre-reset signal RFL is inputted when the access to the shared memory 11 is finished and the bus acquisition request signal HDRQ disappears.If the bus acquisition request signal HDRQ is not input, the pre-reset signal RFL is inputted. A bus acquisition request signal is input to the bus acquisition circuit 10-2, the bus acquisition request signal is outputted, and the bus control unit 12 outputs the bus use permission signal BAC.
When K1 is input, the bus acquisition circuit 10-2 sends a bus use permission signal to the AND circuits 21 and 22.
A bus use permission signal RACK is sent to the system reset control circuit 10-3 from the output of the system reset control circuit 10-3, and a system reset signal is sent to the processor 10-1 and sub-bus masters 1 to n to perform a system reset.

In this way, it is not necessary to provide a memory protection circuit for each bus master, and the system reset control circuit 10-3 of the main bus master 10 can be improved and the priority determination circuit 10-6 can be improved.
By adding , memory can be protected, so the circuit configuration of a multi-bus master type system can be made smaller.

〔Effect of the invention〕

As explained in detail above, according to the present invention, multi-bus
In a master type system, the circuit configuration can be made small in order to avoid system reset during shared memory access.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a main bus master and sub bus master according to an embodiment of the present invention.
Master Block Diagram FIG. 3 is a block diagram of an example system, and FIG. 4 is a block diagram of a conventional main bus master and sub-bus master. In the figure, 1.2. ~n is the secondary bus master, 10 is the main bus master, 10-1.11-'1 is the processor, 10-2.11-2 is the bus acquisition circuit, 10-3.10-5 is the system reset control circuit ,lo
-6 is a priority determination circuit, 11 is a shared memory, 10-4.11-4 is a memory protection circuit, 12 is a bus control unit, 13 is a system bus, 20 is an OR circuit, and 21.22 is an AND circuit. Conventional '1 Kivajin 7 Lv: Hatake °1 Basmas 9 of 7
´口...Jff diagram Figure 4

Claims (1)

[Claims] A processor (10-1) and the processor (10-1)
The bus acquisition circuit (10-2) outputs a bus use request signal when a bus acquisition command is input from the bus master (10), and the main bus master (10) and all secondary buses when a system reset command is input.
The main bus master (10) has a system reset control circuit (10-3) that outputs a system reset signal to the masters (1, 2, . . . ), and a sub-bus has a plurality of processors and bus acquisition circuits.・
The masters (1, 2,...) and the shared memory (11) are connected by a system bus (13), and each bus master (10, 1, 2,...) connects to the shared memory (11). In order to access the system bus (1
3), a multi-bus master type in which each bus acquisition circuit sends a bus use request signal to the bus control unit (12) and accesses the shared memory (11) after obtaining a bus use permission signal. The system's primary bus master (
In 10), when the system reset control circuit (10-3) receives the system reset command, it outputs a pre-reset signal requesting acquisition of the system bus, and after the bus use permission signal is input, it outputs the system reset signal. In addition, the bus acquisition request signal from the processor (10-1) and the pre-reset signal from the system reset control circuit (10-3) are input, and if the bus acquisition request signal is input first, , holds the output of the bus acquisition request signal by the pre-reset signal to the bus acquisition circuit (10-2) until there is no more input, and holds the output of the bus acquisition request signal if the pre-reset signal has been input first. A priority determination circuit (10-6) that outputs a bus acquisition request signal based on a pre-reset signal is provided, and a system reset command is issued to the system reset control circuit (10-6).
10-3), outputs a bus acquisition request signal based on the pre-reset signal to the priority determination circuit (10-6);
In the priority determination circuit (10-6), if the bus acquisition request signal is input first, the bus acquisition request signal is no longer present, and if the bus acquisition request signal is not input, the pre-reset signal is input. , inputs a bus acquisition request signal based on a pre-reset signal to the bus acquisition circuit (10-2), outputs the bus acquisition request signal, and when a bus use permission signal is obtained from the bus control unit (12), the system Reset control circuit (10-3)
A memory protection method characterized in that a system reset signal is output to the main bus master (10) and all the sub bus masters (1, 2, . . . ).