JPH04155866A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04155866A JPH04155866A JP2279003A JP27900390A JPH04155866A JP H04155866 A JPH04155866 A JP H04155866A JP 2279003 A JP2279003 A JP 2279003A JP 27900390 A JP27900390 A JP 27900390A JP H04155866 A JPH04155866 A JP H04155866A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- photodiode
- oeic
- protrudent
- recessed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 239000010931 gold Substances 0.000 claims abstract description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052737 gold Inorganic materials 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 19
- 229910000679 solder Inorganic materials 0.000 abstract description 15
- 239000006023 eutectic alloy Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 241000406668 Loxodonta cyclotis Species 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はハイブリッド型半導体装置の組立て方法に関す
るものである。特に、Si、GaAs。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for assembling a hybrid semiconductor device. In particular, Si, GaAs.
InP等のICまたは0EICの上に単体ホトダイオー
ドや半導体レーザをフリップチップボンディングする場
合の位置決めと電気的接続法に関する。This article relates to positioning and electrical connection methods when flip-chip bonding a single photodiode or semiconductor laser onto an InP or other IC or 0EIC.
ICとホトダイオードや半導体レーザチップをフリップ
チップボンディングするためには、これらを逆さまにし
てSnなどのハンダ材を用いて熱圧着しなければならな
い。チップを逆さまにするため電気接点が接触する様子
が見えない。In order to perform flip-chip bonding between an IC, a photodiode, or a semiconductor laser chip, these must be turned upside down and thermocompressed using a solder material such as Sn. Because the chip is upside down, you cannot see the electrical contacts making contact.
従来のフリップチップボンディング法は第2図の様に○
EIC5の上に形成された電極用金メッキ2の上にSn
ハンダ3を乗せておき、その上にホトダイオード4に形
成された電極用金メッキ1を乗せ、加熱圧着する。この
際の0EICの電極とホトダイオードの電極との位置合
わせは第3図の様な位置合わせマーク7を用いてだいた
いの位置を決めておき、ハーフミラ−を用いた両面アラ
イナ−を利用して正確な位置決めを行う。しかし、この
方法では作業者の目視によるので高精度の位置合わせが
困難である。そこで、○EIC電極とホトダイオード電
極とが自己整合的に位置決めできる方法を用いる必要が
ある。The conventional flip chip bonding method is as shown in Figure 2.
Sn is applied on the electrode gold plating 2 formed on the EIC5.
The solder 3 is placed on top of the solder 3, and the electrode gold plating 1 formed on the photodiode 4 is placed on top of the solder 3, and the solder 3 is heated and pressed. At this time, to align the electrodes of the 0EIC and the photodiode, use the alignment marks 7 as shown in Figure 3 to determine the approximate position, and then use a double-sided aligner using a half mirror to accurately align the electrodes. Perform positioning. However, this method requires visual inspection by the operator, making it difficult to achieve highly accurate positioning. Therefore, it is necessary to use a method that allows the EIC electrode and the photodiode electrode to be positioned in a self-aligned manner.
第4図、第S図はPb5nハンダを用いた従来よく知ら
れているセルフアライメント方式の一例である。このハ
ンダを用いると第4図の様に位置がずれていても加熱す
るとハンダの表面張力で第5図の様に正しい位置に修正
される。FIG. 4 and FIG. S are examples of a conventionally well-known self-alignment method using Pb5n solder. If this solder is used, even if the position is shifted as shown in Fig. 4, when heated, the surface tension of the solder will correct it to the correct position as shown in Fig. 5.
なお、この種の半導体装置として関連するものには例え
ばアプライド・ワイズイッス・レター(Appl、Ph
ys、Lett、)第40巻第7号、1982年4月1
日、P568〜570等が挙げられる。Note that related semiconductor devices of this type include, for example, Applied Wisdom Letters (Appl, Ph.
Lett, Vol. 40, No. 7, April 1, 1982
day, P568-570, etc.
従来のセルフアライメント方式では、Pb5nハンダの
体積が充分大きくないと表面張力の効果が得られない。In the conventional self-alignment method, the effect of surface tension cannot be obtained unless the volume of Pb5n solder is sufficiently large.
一方、超高速光通信用のホトダイオードでは電極の径が
30μm以下と小さいためこの方法は用いることができ
ない。On the other hand, this method cannot be used in photodiodes for ultrahigh-speed optical communication because the diameter of the electrode is as small as 30 μm or less.
本発明の目的は超高速光通信用ホトダイオードやレーザ
の様な小型のものをセルフアライメント的に0EIC等
にフリップチップボンディングできる方法を提供するも
のである。An object of the present invention is to provide a method for flip-chip bonding small-sized devices such as photodiodes and lasers for ultra-high-speed optical communication to 0EICs and the like in a self-alignment manner.
上記目的を達成するために本発明では金メッキ電極を用
いて○EICの電極を凸型(または凹型)ホトダイオー
ドの電極を凹型(または凸型)に形成し、これらをはめ
合う構造にしたものである(第1図参照)。In order to achieve the above object, the present invention uses gold-plated electrodes to form the EIC electrode in a convex (or concave) shape, and the photodiode electrode in a concave (or convex shape), and has a structure in which these are fitted. (See Figure 1).
第1図の様に0EICの電極を凹形(または凸型)、ホ
トダイオードの電極を凸形(または凹型)に形成し、一
方にSnハンダを蒸着しておき、通常のフリップチップ
ボンディングと同様に両面合わせアライナを用いてフリ
ップチップボンディングする。このとき凸型、凹型の金
メッキ電極がはめ合いにより容易に高精度な位置合わせ
ができ、加熱圧着するとSnハンダが両者の金メッキ層
とAuSn共品合金品合金してしっかりと結合する。As shown in Figure 1, the 0EIC electrode is formed in a concave (or convex) shape, the photodiode electrode is formed in a convex (or concave) shape, Sn solder is vapor-deposited on one side, and the same process as normal flip chip bonding is carried out. Flip chip bonding is performed using double-sided aligners. At this time, the convex and concave gold-plated electrodes fit together to easily achieve highly accurate positioning, and when they are heated and pressed together, the Sn solder forms an AuSn alloy with the gold-plated layers of both, and the two are firmly bonded.
また、電気的にも接触抵抗の小さい良好な電気接点が得
られる。Further, good electrical contacts with low contact resistance can also be obtained.
以下、第1図の実施例の工程を説明する。 The steps of the embodiment shown in FIG. 1 will be explained below.
第6図から第8図は凹型の金メッキを作製する工程であ
る。第6図の様に0EIC5上に下地電極6 (A u
G e / N i / A uなど)を2000人
程蒸形成6゜次に、ポジレジスト11で金メンキパター
ンを作る。次に、Auメッキの下地電極となるTl /
A u膜10を200o人程全面に蒸着する。この上
にネガレジスト9を形成するのだが、このネガレジスト
の形成のし方で凹型ができるかが決まる。すなわち、第
6図の様にポジレジスト11の側壁にT i / A
u膜1oが露出する様にネガレジスト9を形成すると、
T i / A uの底面と側面の両側から金メッキが
行われるので凹型が得られる。一方、第9図の様に側壁
のT i / A u膜を覆う様にしてネガレジストを
形成すると、底面だけから金メッキが行われるので凸型
が得られる。FIGS. 6 to 8 show the steps for producing concave gold plating. As shown in Fig. 6, a base electrode 6 (A u
Ge/Ni/Au, etc.) were evaporated for about 2,000 degrees at 6°.Next, a gold coating pattern was made with positive resist 11. Next, Tl/
An Au film 10 of about 200 degrees is deposited over the entire surface. A negative resist 9 is formed on this, and the manner in which this negative resist is formed determines whether a concave shape will be formed. That is, as shown in FIG.
When the negative resist 9 is formed so that the u film 1o is exposed,
Since gold plating is performed from both the bottom and side surfaces of T i / A u, a concave shape is obtained. On the other hand, if a negative resist is formed to cover the Ti/Au film on the sidewall as shown in FIG. 9, gold plating is performed only from the bottom surface, resulting in a convex shape.
この後、S−502A等のレジスト剥離液中で煮沸して
やり、レジストを除去すると第8図、第11図の様な金
メッキ電極が得られる。Thereafter, the resist is removed by boiling in a resist stripping solution such as S-502A, and gold-plated electrodes as shown in FIGS. 8 and 11 are obtained.
第12図は第2の実施例である。ドーム形PINホトダ
イオード14に凸型電極を形成し、OE工C5側に凹型
電極を形成した例である。FIG. 12 shows a second embodiment. This is an example in which a convex electrode is formed on the dome-shaped PIN photodiode 14, and a concave electrode is formed on the OE C5 side.
本発明の方法により、超高速光通用ホトダイオードの様
に電極の径が30μm以下とノ」)さいものでも自己整
合的に高精度な位置合わせてフリップチップボンディン
グできる。By the method of the present invention, flip-chip bonding can be performed with highly accurate positioning in a self-aligned manner even for small electrodes such as ultra-high-speed optical photodiodes with a diameter of 30 μm or less.
第1図は本発明の第1の実施例を示す図、第2図は従来
のフリップチップボンディング法の一例を示す図、第3
図から第5図はセルフアライメント方式を用いたフリッ
プチップボンディング法の一例を示す図、第6図から第
8図は凹型の電極を作製する工程を示す図、第9図がら
第11図は凸形の電極を作製する工程図、第12図は第
2の実施例を示す図である。
1・・・ホトダイオードの電極用金メッキ、2・・・0
EICの電極用金メッキ、3・・・Snハンダ、4・・
・ホトダイオード、5−OEIC56・・・下地電極、
7・・・位置合わせマーク、8・・・Pb5nハンダ、
9・・・ネガレジスト、10・・・T i / A u
金メッキ下地層、11・・ポジレジスト、12・・・金
メッキ電極(凹型)、13・金メッキ電極(凸型)、1
4・・ドーム型箔Δ 図
第3図
系l1図
〜、。梧い、
ト象
第 12回FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing an example of a conventional flip chip bonding method, and FIG.
Figures 5 to 5 are diagrams showing an example of the flip chip bonding method using the self-alignment method, Figures 6 to 8 are diagrams showing the process of producing a concave electrode, and Figures 9 to 11 are convex. FIG. 12 is a process diagram for producing a shaped electrode, and is a diagram showing a second example. 1...Gold plating for photodiode electrodes, 2...0
EIC electrode gold plating, 3...Sn solder, 4...
・Photodiode, 5-OEIC56... base electrode,
7... Positioning mark, 8... Pb5n solder,
9...Negative resist, 10...T i / A u
Gold plating base layer, 11...Positive resist, 12...Gold plating electrode (concave type), 13.Gold plating electrode (convex type), 1
4...Dome-shaped foil Δ Figure 3, Figure 11~,. Great,
Elephant No. 12
Claims (1)
、LSI、OEICウェハあるいはチップの上に半導体
レーザ、ホトダイオード等をフリップチップボンディン
グしてハイブリッドICを作製する場合に、金メッキを
利用して凹型と凸型の電気接点と位置決めマークを形成
することにより高精度にかつ、自己整合的に接続できる
電気接点を作製することを特徴とする半導体装置。1. IC fabricated on a substrate such as Si, GaAs, InP, etc.
When manufacturing hybrid ICs by flip-chip bonding semiconductor lasers, photodiodes, etc. onto LSI, OEIC wafers or chips, high performance can be achieved by forming concave and convex electrical contacts and positioning marks using gold plating. A semiconductor device characterized by manufacturing electrical contacts that can be connected accurately and in a self-aligned manner.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2279003A JPH04155866A (en) | 1990-10-19 | 1990-10-19 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2279003A JPH04155866A (en) | 1990-10-19 | 1990-10-19 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04155866A true JPH04155866A (en) | 1992-05-28 |
Family
ID=17605049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2279003A Pending JPH04155866A (en) | 1990-10-19 | 1990-10-19 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04155866A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5405809A (en) * | 1992-10-02 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, an image sensor device, and methods for producing the same |
US6281445B1 (en) | 1998-07-13 | 2001-08-28 | Nec Corporation | Device and method for connecting two electronic components |
US11916047B2 (en) | 2018-11-06 | 2024-02-27 | Samsung Electronics Co., Ltd. | Display apparatus |
-
1990
- 1990-10-19 JP JP2279003A patent/JPH04155866A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5405809A (en) * | 1992-10-02 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, an image sensor device, and methods for producing the same |
US5408121A (en) * | 1992-10-02 | 1995-04-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, an image sensor device, and methods for producing the same |
US6281445B1 (en) | 1998-07-13 | 2001-08-28 | Nec Corporation | Device and method for connecting two electronic components |
US11916047B2 (en) | 2018-11-06 | 2024-02-27 | Samsung Electronics Co., Ltd. | Display apparatus |
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