CN110310895A - A kind of three-dimensionally integrated packaging method of embedment TSV switching chip silicon substrate fan-out-type and structure - Google Patents
A kind of three-dimensionally integrated packaging method of embedment TSV switching chip silicon substrate fan-out-type and structure Download PDFInfo
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- CN110310895A CN110310895A CN201910701970.7A CN201910701970A CN110310895A CN 110310895 A CN110310895 A CN 110310895A CN 201910701970 A CN201910701970 A CN 201910701970A CN 110310895 A CN110310895 A CN 110310895A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 61
- 239000010703 silicon Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 32
- 239000011521 glass Substances 0.000 claims abstract description 27
- 238000005538 encapsulation Methods 0.000 claims abstract description 18
- 239000004033 plastic Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 229910000679 solder Inorganic materials 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 7
- 239000003292 glue Substances 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910010272 inorganic material Inorganic materials 0.000 claims description 6
- 239000011147 inorganic material Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims description 2
- 238000006116 polymerization reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 13
- 229920000642 polymer Polymers 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 230000009897 systematic effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention discloses a kind of three-dimensionally integrated packaging method of embedment TSV switching chip silicon substrate fan-out-type and structure, belongs to integrated antenna package technical field.Silicon substrate is provided first, in its front deposition cutoff layer；Glass support plate is bonded on the cutoff layer；Go out groove in the silicon substrate back-etching, be embedded to chip in a groove and filled up with dry film material；Then it is open at the pad of chip and completes first surface rewiring, and pass through micro convex point and heterogeneous chip face-down bonding；The back side of silicon substrate described in plastic packaging wraps up the side of chip completely, disassembles the glass support plate and exposes the cutoff layer；Then remove the cutoff layer, press dry film filling surface with vacuum, be open at pad；Second surface rewiring, solder mask and salient point are finally successively made, single encapsulation chip is finally cut into, completes final encapsulation.
Description
Technical field
The present invention relates to integrated antenna package technical field, in particular to a kind of embedment TSV switching chip silicon substrate fan-out-type
Three-dimensionally integrated packaging method and structure.
Background technique
Currently, electronic product mostly develops towards light, thin, short, small direction, the producers of electronics industry are also continuous
Ground seeks that the method for electronic product size can be reduced.As semiconductor technology develops, has already appeared and three-dimensional stacked partly led
Body device technology, such as Taiwan Semiconductor Manufacturing Co. CoWos, InFO and Intel EMIB.
In recent years, fan-out-type wafer-level packaging is due to having many advantages, such as miniaturization, low cost and high integration, in each movement
In the manufacturers such as device manufacturer, attention rate with higher.As " Moore Law " reaches its physics limit, maintained based on three
" More Moore " epoch of irrespective of size integration packaging arrive.Its main technical thought is by the heterogeneous core of different function, processing procedure
Piece is integrated into a functional module using three-dimensionally integrated encapsulation technology.Three-dimensionally integrated encapsulation technology is regardless of from manufacturing cost, manufacturing
Period still considers from properties of product, is all extraordinary selection compared to SOC technology.
It is all in reconstruct wafer substrate top production TSV through hole to complete three that traditional application, which is fanned out to the three-dimensionally integrated of encapsulation,
Dimension interconnection, this mode complex process are with high costs.
Summary of the invention
The purpose of the present invention is to provide a kind of three-dimensionally integrated packaging method of embedment TSV switching chip silicon substrate fan-out-type and knots
Structure, to solve the problems, such as that traditional application is fanned out to the three-dimensionally integrated complex process, with high costs of encapsulation.
In order to solve the above technical problems, the present invention provides a kind of embedment TSV switching three-dimensionally integrated envelope of chip silicon substrate fan-out-type
Dress method, comprising:
Silicon substrate is provided, in its front deposition cutoff layer；Glass support plate is bonded on the cutoff layer；
Go out groove in the silicon substrate back-etching, be embedded to chip in a groove and filled up with dry film material；
It is open at the pad of chip and completes first surface rewiring, and pass through micro convex point and heterogeneous chip face-down bonding；
The back side of silicon substrate described in plastic packaging wraps up the side of chip completely, disassembles the glass support plate and exposes the cutoff layer；
Remove the cutoff layer, press dry film filling surface with vacuum, be open at pad；
The successively rewiring of production second surface, solder mask and salient point, are finally cut into single encapsulation chip, complete final encapsulation.
Optionally, the glass support plate includes that bonding glass and the interim bonding laser being formed on the bonding glass are anti-
Layer is answered, the interim bonding laser reactive layer is bonded by temporarily bonding glue with the cutoff layer；Wherein,
The thickness of the bonding glass is not less than 100 μm；The thickness of the interim bonding glue is not less than 1 μm, the interim bonding
The thickness of laser reactive layer is not less than 0.1 μm.
Optionally, go out groove in the silicon substrate back-etching, be embedded to chip in a groove and filled up with dry film material and include:
By silicon substrate thinning back side to target thickness and groove is etched by the method grinding or etch, the recess etch to institute
State cutoff layer；
Embedment TSV switching chip and the heterogeneous chip of high density I/O in a groove, the TSV switching chip pass through temporary adhesion glue
Bonding, the heterogeneous chip of high density I/O pass through permanent adhesive glue sticking；
The gap between chip and silicon substrate is filled up with dry film material using vacuum film pressing technology, and surface is made smooth.
Optionally, the quantity of the groove is one or more, and the size of groove determines that depth exists according to chip size
10 μm or more.
Optionally, the TSV switching chip and the heterogeneous chip of high density I/O are one or more；
It is embedded to a chips in each groove or is embedded to multiple chips simultaneously；
The height error of chip is formed after embedment chip height and the silicon-base plane is no more than 5 μm.
Optionally, the dry film material is the polymerizable material including resinae and polyimide.
Optionally, remove the cutoff layer, press dry film filling surface with vacuum, opening includes: at pad
Remove the cutoff layer by lithographic technique, and clean the temporary adhesion glue, exposes the TSV of the TSV switching chip
Metal passage；
Film filling surface is pressed dry with vacuum, and is planarized；
It is open at the TSV metal passage using photoetching technique, the width and depth of the opening are at 1 μm or more.
Optionally, the material of the cutoff layer is the one or more or metal material one or more of inorganic material,
Its thickness is not less than 0.1 μm,
The inorganic material includes SiO2, SiC and SiN；
The metal material includes Al, Cu, Ni, Sn and Au.
Optionally, by the back side of silicon substrate described in capsulation material plastic packaging, the capsulation material be include resinae and polyamides
Polymer including imines.
The present invention also provides a kind of embedment TSV switching three-dimensionally integrated encapsulating structures of chip silicon substrate fan-out-type, by above-mentioned
The embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type is prepared.
A kind of three-dimensionally integrated packaging method of embedment TSV switching chip silicon substrate fan-out-type and structure are provided in the present invention,
Silicon substrate is provided first, in its front deposition cutoff layer；Glass support plate is bonded on the cutoff layer；In the silicon substrate back-etching
Groove out is embedded to chip in a groove and is filled up with dry film material；Then it is open at the pad of chip and completes first surface
It reroutes, and passes through micro convex point and heterogeneous chip face-down bonding；The back side of silicon substrate described in plastic packaging wraps the side of chip completely
It wraps up in, disassembles the glass support plate and expose the cutoff layer；Then remove the cutoff layer, press dry film filling surface with vacuum,
It is open at pad；Second surface rewiring, solder mask and salient point are finally successively made, single encapsulation chip is finally cut into, is completed
Final encapsulation.
The present invention proposes that the TSV that will contain TSV metal passage switching chip is embedded in silicon substrate as a module, same to function
Energy chip reconstructs wafer together, eliminates subsequent TSV through hole production, and modularization assembling greatly reduces production cost and period,
Production efficiency improves, and scale of mass production is suitble to use.
Detailed description of the invention
Fig. 1 is the process signal of the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type provided by the invention
Figure；
Fig. 2 is the schematic diagram of the front deposition cutoff layer of silicon substrate；
Fig. 3 is the schematic diagram of glass support plate；
Fig. 4 is schematic diagram after glass support plate and Bonded on Silicon Substrates；
Fig. 5 is the schematic diagram of silicon substrate back-etching groove；
Fig. 6 is that TSV switching chip and the heterogeneous chip schematic diagram of high density I/O are embedded in groove；
The schematic diagram that Fig. 7 is to fill up dry film material and is open；
Fig. 8 is to form the schematic diagram that first surface reroutes in opening；
Fig. 9 is the heterogeneous chip schematic diagram of face-down bonding high density I/O；
Figure 10 is capsulation material plastic packaging silicon substrate schematic rear view；
Figure 11 is the schematic diagram disassembled glass support plate and clean interim bonding glue；
Figure 12 is the schematic diagram for exposing TSV metal passage after removing the interim bonding glue-line of cutoff layer cleaning；
Figure 13 is the schematic diagram for pressing dry film filling surface with vacuum and being open；
Figure 14 is the schematic diagram for making second surface and rerouting；
Figure 15 is production solder mask and salient point and is cut into schematic diagram after single packaging body.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of embedment TSV switching chip silicon substrate fan-out-type three proposed by the present invention
Dimension integrated encapsulation method and structure are described in further detail.According to following explanation and claims, advantages of the present invention and
Feature will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to side
Just, the purpose of the embodiment of the present invention is lucidly aided in illustrating.
Embodiment one
The present invention provides a kind of embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type, process such as Fig. 1 institutes
Show, includes the following steps:
Step S11, silicon substrate is provided, in its front deposition cutoff layer；Glass support plate is bonded on the cutoff layer；
Step S12, go out groove in the silicon substrate back-etching, be embedded to chip in a groove and filled up with dry film material；
Step S13, it is open at the pad of chip and completes first surface rewiring, and pass through micro convex point and heterogeneous flip-chip
Welding；
Step S14, the back side of silicon substrate described in plastic packaging wraps up the side of chip completely, disassembles described in the glass support plate exposing
Cutoff layer；
Step S15, remove the cutoff layer, press dry film filling surface with vacuum, be open at pad；
Step S16, second surface rewiring, solder mask and salient point are successively made, single encapsulation chip is finally cut into, is completed final
Encapsulation.
Specifically, providing silicon substrate 101 first, in its front deposition cutoff layer 108, as shown in Figure 2.Preferably, described section
Only the material of layer 108 is the one or more or metal material one or more of inorganic material, and thickness is not less than 0.1 μm；
Wherein, the inorganic material includes SiO2, SiC and SiN；The metal material includes Al, Cu, Ni, Sn and Au.Such as Fig. 3 is provided
Shown in glass support plate, the glass support plate include be bonded glass 201 and be formed in it is described bonding glass 201 on interim bonding
Laser reactive layer 202, the interim bonding laser reactive layer 202 are bonded by temporarily bonding glue 203 with the cutoff layer 108,
As shown in Figure 4.Specifically, the thickness of the bonding glass 201 is not less than 100 μm；The thickness of the interim bonding glue 203 is not small
In 1 μm, the thickness of the interim bonding laser reactive layer 202 is not less than 0.1 μm.
Referring to Fig. 5,101 thinning back side of silicon substrate to target thickness and is etched groove by the method for grinding or etching
109, the groove 109 is etched to the cutoff layer 108.The quantity of the groove 109 is one or more, groove 109
Size determines that depth is at 10 μm or more according to chip size.
Such as Fig. 6, it is heterogeneous that TSV switching chip 303, TSV switching chip 304 and high density I/O are embedded in the groove 109
Chip 305, the TSV metal passage 306 of TSV switching chip and the metal pad 307 of the heterogeneous chip of high density I/O are exposed.
Wherein, the TSV switching chip 303 and TSV switching chip 304 are bonded by temporary adhesion glue 204, the high density I/
The heterogeneous chip 305 of O is bonded by permanent adhesive glue 205；The height that chip is formed after embedment chip and 101 plane of silicon substrate
Height error is no more than 5 μm.Specifically, TSV switching chip and the heterogeneous chip of high density I/O are one or more, it is each recessed
It is embedded to a chips in slot or is embedded to multiple chips simultaneously.
The gap dry film material 104 between chip and silicon substrate is filled up using vacuum film pressing technology, and surface is made and is put down
Whole, the dry film material 104 is the polymerizable material including resinae and polyimide.By photoetching technique in chip
TSV metal passage and metal pad at be open, as shown in fig. 7, opening width and depth are at 1 μm or more；It is completed in opening
First surface as shown in Figure 8 reroutes 102, and it is different by micro convex point 308 and high density I/O that the first surface reroutes 102
Heterogeneous 302 face-down bonding of chip of matter chip 301, high density I/O, as shown in Figure 9.
As shown in Figure 10, by the back side of silicon substrate 101 described in 110 plastic packaging of capsulation material, wrap the side of chip completely
It wraps up in, to improve package reliability.The capsulation material 110 is polymer, including resinae and polyimide.Institute is disassembled later
It states glass support plate and cleans up the interim bonding glue 203, expose the cutoff layer 108, such as Figure 11.
Remove the cutoff layer 108 by lithographic technique, and clean the temporary adhesion glue 204, exposes the TSV metal
Channel 307, such as Figure 12；Then film 107 is pressed dry with vacuum and fill surface, and planarized；Using photoetching technique in the TSV
It is open at metal passage 307, the width and depth of the opening are at 1 μm or more, as shown in figure 13.
Figure 14 and Figure 15 are please referred to, second surface is successively made and reroutes 103, solder mask 105 and salient point 106, will complete
The wafer of three-dimensional systematic encapsulation is cut into single encapsulation chip, completes final encapsulation.
Embodiment two
Second embodiment of the present invention provides a kind of embedment TSV switching three-dimensionally integrated encapsulating structure of chip silicon substrate fan-out-type, such as Figure 15
It is shown, including silicon substrate 101, the first face of the silicon substrate 101 be provided with groove, be embedded with chip in the groove.Further, described
The quantity of groove is one or more, and the size of groove is determined according to chip size, and depth is at 10 μm or more；Further
, it is embedded to a chips in each groove or is embedded to multiple chips simultaneously；Be embedded to chip after chip formed height with it is described
The height error of 101 plane of silicon substrate is no more than 5 μm.Dry film material 104 is filled in the gap of the groove and the chip,
Described in dry film material 104 be polymerizable material including resinae and polyimide.
Specifically, the chip includes TSV switching chip 303, TSV switching chip 304 and the heterogeneous chip of high density I/O
305.Wherein, the TSV switching chip 303 and TSV switching chip 304 pass through temporary adhesion glue sticking；The high density
The heterogeneous chip 305 of I/O is bonded by permanent adhesive glue 205.
Specifically, TSV metal passage 306, the height of the TSV switching chip 303 and TSV switching chip 304
The metal pad 307 of the heterogeneous chip 305 of density I/O reroutes 102 with first surface and connect, and the first surface reroutes 102
Pass through micro convex point 308 and the heterogeneous chip face-down bonding of high density I/O.Further, the first surface reroutes 102 by micro-
Plastic packaging has capsulation material 110 between salient point 308 and the heterogeneous chip of high density I/O, wraps up the side of chip completely, to improve
Package reliability；Further, the capsulation material 110 is the polymer including resinae and polyimide.
Second face of the silicon substrate 101 press dry film 107 filled with vacuum, and successively production there is second surface to reroute 103,
Solder mask 105 and salient point 106.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
- The three-dimensionally integrated packaging method of chip silicon substrate fan-out-type 1. a kind of embedment TSV transfers characterized by comprisingSilicon substrate is provided, in its front deposition cutoff layer；Glass support plate is bonded on the cutoff layer；Go out groove in the silicon substrate back-etching, be embedded to chip in a groove and filled up with dry film material；It is open at the pad of chip and completes first surface rewiring, and pass through micro convex point and heterogeneous chip face-down bonding；The back side of silicon substrate described in plastic packaging wraps up the side of chip completely, disassembles the glass support plate and exposes the cutoff layer；Remove the cutoff layer, press dry film filling surface with vacuum, be open at pad；The successively rewiring of production second surface, solder mask and salient point, are finally cut into single encapsulation chip, complete final encapsulation.
- 2. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as described in claim 1, which is characterized in that The glass support plate includes the interim bonding laser reactive layer for being bonded glass and being formed on the bonding glass, the ephemeral key Laser reactive layer is closed to be bonded by temporarily bonding glue with the cutoff layer；Wherein,The thickness of the bonding glass is not less than 100 μm；The thickness of the interim bonding glue is not less than 1 μm, the interim bonding The thickness of laser reactive layer is not less than 0.1 μm.
- 3. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as described in claim 1, which is characterized in that Go out groove in the silicon substrate back-etching, be embedded to chip in a groove and filled up with dry film material and include:By silicon substrate thinning back side to target thickness and groove is etched by the method grinding or etch, the recess etch to institute State cutoff layer；Embedment TSV switching chip and the heterogeneous chip of high density I/O in a groove, the TSV switching chip pass through temporary adhesion glue Bonding, the heterogeneous chip of high density I/O pass through permanent adhesive glue sticking；The gap between chip and silicon substrate is filled up with dry film material using vacuum film pressing technology, and surface is made smooth.
- 4. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as claimed in claim 3, which is characterized in that The quantity of the groove is one or more, and the size of groove is determined according to chip size, and depth is at 10 μm or more.
- 5. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as claimed in claim 3, which is characterized in that The TSV switching chip and the heterogeneous chip of high density I/O are one or more；It is embedded to a chips in each groove or is embedded to multiple chips simultaneously；The height error of chip is formed after embedment chip height and the silicon-base plane is no more than 5 μm.
- 6. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as claimed in claim 3, which is characterized in that The dry film material is the polymerizable material including resinae and polyimide.
- 7. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as claimed in claim 3, which is characterized in that Remove the cutoff layer, press dry film filling surface with vacuum, opening includes: at padRemove the cutoff layer by lithographic technique, and clean the temporary adhesion glue, exposes the TSV of the TSV switching chip Metal passage；Film filling surface is pressed dry with vacuum, and is planarized；It is open at the TSV metal passage using photoetching technique, the width and depth of the opening are at 1 μm or more.
- 8. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as described in claim 1, which is characterized in that The material of the cutoff layer is the one or more or metal material one or more of inorganic material, and thickness is not less than 0.1 μm,The inorganic material includes SiO2, SiC and SiN；The metal material includes Al, Cu, Ni, Sn and Au.
- 9. the embedment TSV switching three-dimensionally integrated packaging method of chip silicon substrate fan-out-type as described in claim 1, which is characterized in that By the back side of silicon substrate described in capsulation material plastic packaging, the capsulation material is the polymerization including resinae and polyimide Object.
- The three-dimensionally integrated encapsulating structure of chip silicon substrate fan-out-type 10. a kind of embedment TSV transfers, which is characterized in that pass through claim The described in any item embedment TSV switching three-dimensionally integrated packaging methods of chip silicon substrate fan-out-type of 1-9 are prepared.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957269A (en) * | 2019-11-08 | 2020-04-03 | 广东佛智芯微电子技术研究有限公司 | Manufacturing method for improving electroplating performance of embedded fan-out type packaging structure |
| CN111128979A (en) * | 2019-11-22 | 2020-05-08 | 中国电子科技集团公司第十三研究所 | Wafer-level 3D chip preparation method |
| CN111769099A (en) * | 2020-07-09 | 2020-10-13 | 中国科学院微电子研究所 | Packaging structure and packaging method for realizing multi-chip integration based on multiple transfer boards |
| CN111769098A (en) * | 2020-07-09 | 2020-10-13 | 中国科学院微电子研究所 | Packaging structure and packaging method for realizing integration of multiple chips |
| CN113113540A (en) * | 2021-03-01 | 2021-07-13 | 北京大学 | Flexible hybrid electronic system processing method and flexible hybrid electronic system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221936A (en) * | 2007-01-03 | 2008-07-16 | 育霈科技股份有限公司 | Wafer level package with die receiving through-hole and method of the same |
| CN102915983A (en) * | 2011-08-05 | 2013-02-06 | 欣兴电子股份有限公司 | Package substrate embedded with interposer and method for fabricating the same |
| US20140070396A1 (en) * | 2012-09-12 | 2014-03-13 | Shinko Electric Industries Co., Ltd. | Semiconductor package and manufacturing method |
| CN108074883A (en) * | 2016-11-09 | 2018-05-25 | 三星电机株式会社 | Semiconductor package part, its manufacturing method and use its electronic component modular |
| CN210296360U (en) * | 2019-07-31 | 2020-04-10 | 中国电子科技集团公司第五十八研究所 | Silicon-based fan-out type three-dimensional integrated packaging structure with embedded TSV (through silicon via) adapter chip |
-
2019
- 2019-07-31 CN CN201910701970.7A patent/CN110310895A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221936A (en) * | 2007-01-03 | 2008-07-16 | 育霈科技股份有限公司 | Wafer level package with die receiving through-hole and method of the same |
| CN102915983A (en) * | 2011-08-05 | 2013-02-06 | 欣兴电子股份有限公司 | Package substrate embedded with interposer and method for fabricating the same |
| US20140070396A1 (en) * | 2012-09-12 | 2014-03-13 | Shinko Electric Industries Co., Ltd. | Semiconductor package and manufacturing method |
| CN108074883A (en) * | 2016-11-09 | 2018-05-25 | 三星电机株式会社 | Semiconductor package part, its manufacturing method and use its electronic component modular |
| CN210296360U (en) * | 2019-07-31 | 2020-04-10 | 中国电子科技集团公司第五十八研究所 | Silicon-based fan-out type three-dimensional integrated packaging structure with embedded TSV (through silicon via) adapter chip |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957269A (en) * | 2019-11-08 | 2020-04-03 | 广东佛智芯微电子技术研究有限公司 | Manufacturing method for improving electroplating performance of embedded fan-out type packaging structure |
| CN111128979A (en) * | 2019-11-22 | 2020-05-08 | 中国电子科技集团公司第十三研究所 | Wafer-level 3D chip preparation method |
| CN111769099A (en) * | 2020-07-09 | 2020-10-13 | 中国科学院微电子研究所 | Packaging structure and packaging method for realizing multi-chip integration based on multiple transfer boards |
| CN111769098A (en) * | 2020-07-09 | 2020-10-13 | 中国科学院微电子研究所 | Packaging structure and packaging method for realizing integration of multiple chips |
| CN111769099B (en) * | 2020-07-09 | 2022-03-04 | 中国科学院微电子研究所 | Packaging structure and packaging method for realizing multi-chip integration based on multiple transfer boards |
| CN113113540A (en) * | 2021-03-01 | 2021-07-13 | 北京大学 | Flexible hybrid electronic system processing method and flexible hybrid electronic system |
| WO2022183584A1 (en) * | 2021-03-01 | 2022-09-09 | 北京大学 | Flexible hybrid electronic system processing method and flexible hybrid electronic system |
| CN113113540B (en) * | 2021-03-01 | 2022-11-11 | 北京大学 | Flexible hybrid electronic system processing method and flexible hybrid electronic system |
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