JPH04155862A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance a semiconductor integrated circuit device provided with a complementary MISFET in electrostatic breakdown strength when a high voltage is applied to a well region by a method wherein a third semiconductor region which is of the same conductivity type with a first well region or a first semiconductor region and higher than the first well region in impurity concentration is provided to the primary surface of a semiconductor substrate. CONSTITUTION:An N-type well region 2 and a P-type well region 3 are provided onto the different regions of the primary surface of a P<->-type semiconductor substrate 1 respectively. The P<->-type semiconductor substrate 1 is set as low in impurity concentration as 1X10<15>[atoms/cm<2>] or so. The N-type well region 2 is made to serve primarily as a region where a P channel MISFET Qp of a complementary MISFET is arranged and set as intermediate in impurity concentration as 2X10<16>[atoms/cm<2>] or so. The P-type well region 3 is made to serve as a region where a N channel MISFET Qn of the complementary MISFET is arranged and set as intermediate in impurity concentration as 5X10<15>[atoms/cm<2>] or so higher than that of the P<->-type semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a complementary M circuit device.
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having an ISFET.

[Conventional technology]

pRAM (Dynamic
Ordinary and.

va Access Memory) is a series circuit of MO8FET for memory cell selection and capacitive element for information storage.
[A memory cell for storing bitl information is configured. The memory cells are arranged in rows and columns to form a memory cell array. The DRAM includes direct peripheral circuits such as a driver circuit and a decoder circuit around the memory cell array,
Arrange indirect peripheral circuits such as control system circuits, buffer system circuits, and redundant circuits.

Each of the direct peripheral circuit and indirect peripheral circuit is a complementary MO5FET (0MO
8). A DRAM is mainly composed of a P-type semiconductor substrate made of single-crystal silicon, and an n-type well region and an n-type well region are respectively formed in different regions of the main surface of the p-type semiconductor substrate.

In other words, the DRAM currently being developed by the present inventor employs a twin-well structure, although it is not limited to this structure. The n-type well region has a higher impurity concentration than the p-type semiconductor substrate, and an n-channel MO3FET is arranged therein. A P-channel MO3FET is arranged in the n-type well region. DRAM is
A memory cell array occupies most of the occupied area and is located within the n-type well region. As a result, in the DRAM, the area occupied by the P-type well region is larger than that of the n-type well region, together with the n-type well region in the peripheral circuit area.

In the operating state, the DRAM applies a negative substrate potential (for example, -2.5 to -3°5 [V]) to the p-type semiconductor substrate.
is supplied. Since the p-type semiconductor substrate and the P-type well region are each in an electrically conductive state, the substrate potential is supplied to the pn between the source region and drain region (n-type semiconductor region) of the n-channel MO5FET and the n-type well region. Parasitic capacitance added to the junction can be reduced. The n-channel MO
The source region and drain region of the 8FET each have a higher impurity concentration than the n-type well region in order to increase the signal transmission speed.

When complementary MO8FETs are used to configure, for example, an inverter circuit, the n-type semiconductor region corresponding to the source region of the n-channel MO3FET is connected to the ground potential of the circuit, for example 0[v].
] is supplied. This ground potential is supplied through a reference power supply wiring (for example, an aluminum alloy wiring) arranged above the complementary MO8FET.

The n-type semiconductor region corresponding to the source region of the p-channel MO8FET of the inverter circuit is supplied with a circuit operating potential of, for example, 5 [V]. This operating potential is supplied through the operating power supply wiring. The n-type semiconductor region, like the n-type semiconductor region of the n-channel MO8FET, has a higher impurity concentration than the n-type well region. The n-type well region in which this p-channel MO8FET is arranged is supplied with an operating potential that serves as a reverse bias potential to each of the p-type semiconductor substrate and the n-type well region. The operating potential is supplied from the operating power supply wiring to the n-type well region via the n-type semiconductor region in order to reduce the resistance value in the connection region. This n-type semiconductor region is a source region of an n-channel MO8FET,
It is formed in the same manufacturing process as each of the drain regions, and has a higher impurity concentration than the n-type well region.

A DRAM having this type of complementary MO8FET is described, for example, in Japanese Patent Application No. 1-65848.

[Problem to be solved by the invention]

The inventor of the present invention conducted an electrostatic breakdown strength test in which a high voltage was applied to the power supply terminal of the DRAM described above, and found the following problem.

When a positive high voltage is applied to the reference power supply terminal, a reverse breakdown current occurs due to the pn of the n-type semiconductor region corresponding to the source region of the n-channel MO8FET and the n-type well region.
An excessive current flows through the junction, and this excessive current is absorbed by the n-type well region and the p-type semiconductor substrate, respectively. The pn junction is composed of an n-type semiconductor region with a high impurity concentration and a p-type well region with a medium impurity concentration, and has a voltage of about 15[V].
] is set to a low junction breakdown voltage. Since the p-type well region and the p-type semiconductor substrate are electrically connected, the junction breakdown voltage of the p-n junction is determined by the p-type well region having a high impurity concentration. In this case, electrostatic breakdown does not occur because excessive current can be absorbed at a voltage lower than the dielectric breakdown strength of the gate insulating film of the n-channel MO8FET.

On the other hand, when a positive high voltage is applied to the operating power supply terminal, an excessive current flows through the pn junction between the n-type well region and the p-type well region as a reverse breakdown current. It can be predicted that the particles are absorbed in each of the p-type semiconductor substrate and the p-type semiconductor substrate. However, this pn junction is composed of an n-type well region with an intermediate impurity concentration and a p-type well region with an intermediate impurity concentration, and as a result of measurement, approximately 70%
[v] is set to a high junction breakdown voltage. Since the p-type well region and the p-type semiconductor substrate are electrically connected, the junction breakdown voltage of the p-n junction is determined by the p-type well region having a high impurity concentration. Therefore, when a high voltage is applied to the operating power supply terminal, the p-channel MO8
A high voltage is applied between the source region and the gate electrode of the FET, causing so-called electrostatic breakdown, which destroys the gate insulating film. Alternatively, a reverse breakdown current flows first through the pn junction between the train region of the p-channel MO8FET and the n-type well region, and in the case of an inverter circuit, a high voltage is applied between the drain region of the n-channel MO5FET and the gate electrode through wiring. is applied, the gate insulating film is destroyed.

An object of the present invention is to provide a technique that can improve electrostatic breakdown strength when a high voltage is applied to a well region in a semiconductor integrated circuit device having complementary MISFETs.

Another object of the present invention is to provide a technique that can achieve the above object and improve the degree of integration of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can reduce the manufacturing process of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of increasing the operating speed of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can improve the latch-up withstand voltage of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) An impurity concentration of the same conductivity type as the first well region and higher than that of the first well region is formed on the main surface of a first well region formed in a region of the main surface of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate. A first semiconductor region is configured, and power is supplied to the first well region through the first semiconductor region.
In a semiconductor integrated circuit device having a complementary MISFET, a second impurity having the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate, which is formed in another region of the main surface of the semiconductor substrate or in another region. a third semiconductor region having the same conductivity type as the first well region or the first semiconductor region and having a higher impurity concentration than the first well region; The same power is supplied to each of the first well region and the first semiconductor region.

(2) The third semiconductor region on the main surface of the semiconductor substrate or second semiconductor region of the means (1) is the first semiconductor region of the first well region.
Constructed integrally with the semiconductor region.

(3) The semiconductor substrate of the means (1) or (2) or the second
The third semiconductor region on the main surface of the semiconductor region is formed in the same manufacturing process as the first semiconductor region of the first well region.

(4) The third semiconductor region on the main surface of the semiconductor substrate or second semiconductor region of any one of the means (1) to (3) is arranged between each of the n-channel MISFET and the n-channel MISFET of the complementary MISFET. Placed.

(5) The third semiconductor region on the main surface of the semiconductor substrate or second semiconductor region of any one of the means (1) to (3) is arranged around the complementary MISFET with the intervening one.

[For production]

According to the above-mentioned means (1), the pn junction breakdown voltage between the semiconductor substrate or the second semiconductor region and the third semiconductor region is set lower than the pn junction breakdown voltage between the semiconductor substrate and the first well region, When excessive current (static electricity) is applied to the first well region (power supply wiring connected to the first well region), the semiconductor The MIS placed on the main surface of the first well region can absorb excessive current with a lower withstand voltage than the pn junction between the substrate and the first well region.
It is possible to reduce electrostatic breakdown of FETs and improve electrostatic breakdown strength of semiconductor integrated circuit devices.

According to the above-mentioned means (2), since the element isolation area and wiring connection area between the third semiconductor region and the first semiconductor region can be eliminated, the semiconductor integrated circuit can be reduced by an amount corresponding to the eliminated area. The degree of device integration can be improved.

According to the above-mentioned means (3), since the third semiconductor region can be formed using the step of forming the first semiconductor region, the amount of time required for forming the semiconductor integrated circuit device is equivalent to the step of forming the third semiconductor region. Manufacturing process can be reduced.

According to the above-mentioned means (4), the distance between the third semiconductor region and the semiconductor substrate or the region that supplies power to the second semiconductor region is made close to reduce the parasitic resistance of the semiconductor substrate or the second semiconductor region. Since the value can be reduced, the third semiconductor region,
It is possible to shorten the excessive current path between the power supplies intervening in the semiconductor substrate or the second semiconductor region and the power supply region, thereby further improving the electrostatic breakdown strength. Further, since the excessive current path between the power supplies can be shortened and fluctuations in the base potential of the parasitic thyristor can be reduced, the latch-up withstand voltage of the semiconductor integrated circuit device can be improved.

According to the above-mentioned means (5), the complementary MISFET
Since the n-channel MISFET and the n-channel MISFET can be arranged close to each other and the wiring connection distance between them can be shortened, the signal transmission speed can be increased and the operation speed of the semiconductor integrated circuit device can be increased.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a DRAM having complementary MISFETs.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Embodiment I) The configuration of a complementary MISFET (CMO8) arranged in the peripheral circuit of a DRAM, which is Embodiment 2 of the present invention, is shown in Fig. 2 (main part plan view) and Fig. 1 (!- of Fig. 2). ■Cross-sectional view taken along the cutting line).

As shown in FIGS. 1 and 2, a DRAM is mainly constructed from a p-type semiconductor substrate made of single crystal silicon. An n-type well region 2 and a p-type well region 3 are formed in different regions of the main surface of the p-type semiconductor substrate 1, respectively. p
- type semiconductor substrate 1 has, for example, 1×101s [atoms/
The impurity concentration is as low as [aJ]. The n-type well region 2 is mainly used for p-channel MISFET of complementary MISFET.
It is used as the area where S F E T Q p is placed, for example 2 x 1016 [at.

It is composed of a medium impurity concentration of about as/a&1.

The P-type well region 3 is used as a region where an n-channel MISFET Qn of a complementary MISFET is arranged, and has a size of, for example, 5×10” [atoms/a
The p-type semiconductor substrate 1 has a medium impurity concentration that is higher than that of the p-type semiconductor substrate 1, which has an impurity concentration of about &].

Complementary MISFETs constituting each of the direct peripheral circuit and indirect peripheral circuit of DRAM are n-channel MISFETQn
and p-channel MISFETQP. The direct peripheral circuit directly controls the memory cells arranged in the memory cell array, and includes, for example, a driver circuit, a decoder circuit, a sense amplifier circuit, and the like. The indirect peripheral circuit controls the direct peripheral circuit, and includes, for example, an input/output circuit, a clock system control circuit, a buffer circuit, a substrate potential generation circuit (VBB generator), a redundant circuit, and the like.

n-channel MISFETQn of the complementary MISFETs
is formed on the main surface of the n-type well region 3 in a region surrounded by the element isolation insulating film (field insulating film) 4 and the p-type channel stopper region 5 . In other words, the n-channel MISFET Qn includes a P-type well region (channel formation region) 3, a gate insulating film 6, a gate electrode 7, a pair of n-type semiconductor regions 8 which are a source region and a drain region, and a pair of n°-type semiconductor regions. Consists of 9.

The gate insulating film 6 of the n-channel MISFETQn is composed of, for example, a silicon oxide film formed by a thermal oxidation method. The gate insulating film 6 is formed to have a thickness of about 15 to 20 [nm], for example, and has a dielectric breakdown voltage of about 15 to 20 [nm].
V] diameter is set. The gate electrode 7 is composed of, for example, a single layer of a polycrystalline silicon film or a refractory metal silicide film, or a laminated film thereof. The n-type semiconductor regions 8 of the source region and the drain region each have an LDD (Lightly
(Doped Drain) structure. The n-type semiconductor region 8 has a lower impurity concentration than the n-type semiconductor region 9 and a higher impurity concentration than the n-type well region 2, for example, 2 x 10''ratoms/al?
It is composed of an impurity concentration of approximately . n° type semiconductor region 9
is 2
It is composed of a high impurity concentration of about I O” [atows/d].

The element isolation insulating film 4 is composed of a silicon oxide film formed by oxidizing the main surface of the non-active region of the p-type semiconductor substrate 1.

In the p-type channel stopper region 5, the surface of the n-type well region 3 in contact with the element isolation insulating film 4 is likely to be inverted to n-type, and the parasitic M
Since O5FET is easy to form, this parasitic MO8FET
Constructed for the purpose of preventing the formation of P-type channel stopper region 5 has a higher impurity concentration than P-type well region 3.

A reference power supply wiring (Vss) 17 is connected via a wiring 14 to the n' type semiconductor region 9 corresponding to the source region of the n-channel MISFETQn. The wiring 14 is connected to the n'' type semiconductor region 9 through the connection hole 13 formed in the interlayer insulating film 12.
It is formed in the wiring formation process of the second layer.

The wiring 14 has a laminated structure of, for example, aluminum and a high melting point metal silicide film or a high melting point metal film. The reference power supply wiring 17 is connected to the wiring 14 through a connection hole 16 formed in the glabella insulating film 15. The reference power supply wiring 17 is formed in the second layer wiring formation step in the manufacturing process. The reference power supply wiring 17 has a laminated structure of, for example, aluminum and a high melting point metal silicide film or a high melting point metal film. Reference power supply wiring 17 is an external terminal for reference power supply (ponding pad)
A circuit reference potential, for example 0 [V], is supplied from the internal circuit to the internal circuit.

p-channel MISFETQp of the complementary MISFET
is formed on the main surface of the n-type well region 2 in a region surrounded by the element isolation insulating film 4 . In other words, the p-channel MISFET Qp consists of an n-type well region (channel formation region) 2, a gate insulating film 6, a gate electrode 7, and a pair of p-type semiconductor regions l serving as a source region and a drain region.
O and a pair of p type semiconductor regions! ! Consists of.

Each p-type semiconductor region 10 of the source region and drain region of the P-channel MISFET QP is an n-channel MISFET QP.
Construct an LDD structure similarly to I S F E T Q n. The P-type semiconductor region 10 is, for example, 6×10” [at
oms/al? ] Consisting of an impurity concentration of approximately . p・
The type semiconductor region 11 is, for example, 6×10” [ato
ms/aJ] with a high impurity concentration.

An operating power supply wiring (Vcc) 17 is connected via a wiring 14 to the p° type semiconductor region 11 corresponding to the source region of the P-channel MISFET Qp. The operating power supply wiring 17 supplies a circuit operating potential of, for example, 5 [V] to the internal circuit from an external terminal for operating power supply (ponding pad).

Although not specifically shown in Figures 1 and 2, D
A memory cell of a RAM is constituted by a series circuit of a memory cell selection MISFET and an information storage capacitive element. The memory cell selection MISFET is the n-channel MISFET.
It has substantially the same structure as Qn. Although the information storage capacitive element is not limited to this structure, a lower electrode (polycrystalline silicon film), a dielectric film, and an upper electrode (polycrystalline silicon film) are sequentially formed on the main surface of a p-type semiconductor substrate l. Consists of a stacked structure.

In the vicinity of the complementary MI 5FET n-channel MISFET Qn constituting the aforementioned peripheral circuit, as shown in FIGS. 1 and 2, there is a A diode element D2 is arranged. This diode element D2 has an anode region that is an n-type well region 3 that is electrically connected to a P°-type semiconductor substrate, and a reference power supply wiring 1 that is configured on its main surface.
The n-type semiconductor region 9 connected to the electrode 7 via the wiring 14 is configured as a cathode region. In the diode element D2, when the DRAM is not in operation, when a high voltage applied to the reference power external terminal is supplied to the n゛-type semiconductor region 9 corresponding to the cathode region through the reference power supply wiring 17 and the wiring 14, As forward current or reverse breakdown current, p
- type semiconductor substrate l can absorb it. p-type semiconductor substrate engineering,
Each of the P-type well regions 3 that are electrically connected thereto is supplied with a substrate potential V B B generated by a substrate potential generation circuit, for example, -2,5 to -3,5 [V] during operation of the DRAM. When not in operation, it is at a floating potential.

The diode element D2 has a p-type semiconductor region 9 with a high impurity concentration and an n-type well region 3 with a medium impurity concentration.
It is constituted by an n junction (actually also includes a pn junction between the n° type semiconductor region 9 and the P type channel stopper region 5). In other words, the reverse breakdown voltage (junction breakdown voltage) at the pn junction of the diode element D2 can be set as low as, for example, about 15 [V], which is lower than the dielectric breakdown voltage of the gate insulating film 6 described above. For example, the diode element D2 has a large planar area in addition to the area occupied by the n-channel MISFET Qn, and as a result, the pn junction area and the peripheral length are large. In the diode element D2 of this embodiment, since the junction breakdown voltage is substantially determined by the pn junction between the n-type semiconductor region 9 and the p-type channel stopper region 5, the increase in the occupied area is due to the periphery of the active region. This results in an increase in length and an increase in the pn junction area. This increase in the pn junction area and peripheral length of the diode element D2 can reduce the amount of excessive current flowing per unit area of the pn junction.

Thermal damage at the pn junction can be reduced.

On the other hand, the p-channel MISF of the complementary MISFET mentioned above
In the vicinity of the ETQP, the n-type well region 2 is connected from the operating power supply wiring (Vcc) 17 to the wiring 14 and the n°-type semiconductor region 9.
An operating potential is supplied through each of them.

In other words, power is supplied to the n-type well region 2 from the surface side (well power supply). The n'-type semiconductor region 9 interposed between the n-type well region 2 and the wiring 14 is configured for the purpose of reducing the connection resistance value between the two.

In the vicinity of the P-channel MISFET Qp, p
A diode element DI is arranged between the - type semiconductor substrate 1 and the operating power supply wiring (Vcc) 17. Diode element D1 has p
The n-type well region 3 electrically connected to the °-type semiconductor substrate 1 is used as an anode region, and is formed on the main surface thereof.

The n-type semiconductor region 9 connected to the operating power supply wiring 17 via the wiring member 4 is configured as a cathode region. The diode element D1 has a high voltage applied to an external terminal for an operating power supply when the DRAM is not operating.
If the current is supplied to the n° type semiconductor region 9 corresponding to the cathode region through each of these, it can be absorbed into the p type semiconductor substrate 1 as a forward current or a reverse breakdown current.

The diode element D1, like the diode element D2, is composed of a pn junction between an n° type semiconductor region 9 with a high impurity concentration and a P type well region 3 with a medium impurity concentration. That is, this diode element D1 can set the junction breakdown voltage at the pn junction portion to be substantially as low as that of the diode element D2. In other words, when looking at the junction breakdown voltages of the diode elements D1 and D2 from the p'-type semiconductor substrate 1 side, they are substantially equal. The pn junction breakdown voltage between the n-type well region 2 and the n-type well region 3 (or the p-type semiconductor substrate 1) is, for example, about 70 [V], whereas the diode element D
1 is set to a low junction breakdown voltage of about 15 [V].

In the manufacturing process, each of the n° type semiconductor region 9 configured for the purpose of supplying an operating potential to the n type well region 2 and the n° type semiconductor region 9 corresponding to the cathode region of the diode element D1 is I S F E T
n°, each of the source region and drain region of Q n
It is formed in the same manufacturing process as the type semiconductor region 9. Also, n
n° type semiconductor region 9 on the main surface of type well region 2. Each of the n' type semiconductor regions 9 of the diode element D1 is integrally constructed. In other words, the n° type semiconductor region 9 of the diode element D1 extends from the main surface of the n-type well region 2 to the main surface of the n-type well region 3.

As shown in FIG. 3 (schematic layout diagram), each of the aforementioned diode elements D1 and D2 has a plurality of P-channel M
Arrangement region 20 of ISFETQp and plural n-channel M
It is arranged between the array region 21 of I S F E T Q n. The respective layouts of the diode elements D1 and D2 allow them to be close to each other.

Further, for example, wiring 14 (for example, an address signal line, a clock system control signal line, etc.) can be extended in the upper layer of each of the diode elements D1 and D2.

In addition, the n-channel M I S F E T Q n is
Based on physical differences in mobility, p-channel MISFE
Compared to TQp, the gate width can be set to about one-third, and the occupied area can be reduced. Therefore, the diode element D1 can be arranged between the array regions 20, 21, and the diode element D2 can be arranged between every predetermined number of n-channel MISFETQn in the array region 21.

In this way, the main surface of the n-type well region 2 formed in one region of the main surface of the p-type semiconductor substrate 1 is doped with an impurity having the same conductivity type as the n-type well region 2 and having a higher concentration than that of the n-type well region 2. In a DRAM having a complementary MISFET, in which an n-type semiconductor region 9 is formed, and an operating potential Vcc is supplied to the n-type well region 2 through the n-type semiconductor region 9, the p-type semiconductor substrate 1 In other areas of the main surface of the p
- type semiconductor substrate 1 and a p-type well region (diode element D
An impurity concentration of the same conductivity type as the n-type well region 2 or the n°-type semiconductor region 9 formed on the main surface thereof and higher than that of the n-type well region 2 is applied to the main surface of the anode region) 3 of D1. n° type semiconductor region (diode element D1
(cathode region) 9, and this n-type semiconductor region 9
is the same operating potential Vcc as the operating potential Vcc supplied to each of the n-type well region 2 and the n°-type semiconductor region 9 on its main surface.
cc is supplied.

With this configuration, compared to the pn junction breakdown voltage between the n-type well region 2 and the n-type well region 3 (or the P°-type semiconductor substrate 1), the If the pn junction breakdown voltage between the − type semiconductor substrate 1) and the n° type semiconductor region 9, which is the cathode region, is set low and an excessive current (static electricity) is applied to the n type well region 2, the n° Through the pn junction between the n-type well region 3 and the n-type semiconductor region 9, excessive current can be absorbed with a lower junction breakdown voltage than the pn junction between the n-type well region 2 and the n-type well region 3. Electrostatic damage to the p-channel MISFET Qp or n-channel MISFET Qn disposed in the type well region 2 can be prevented. The excessive current absorbed in the n-type well region 3 (or the p-type semiconductor substrate 1) through the diode element D1 is transferred through the diode element D2 as a forward current or reverse breakdown current, and immediately becomes a reference current. Potential Vs
It is released to the s side. As a result, p-channel MISFET
Since the electrostatic breakdown of each of Qp and n-channel MISFET Qn can be reduced, the electrostatic breakdown strength of the DRAM can be improved.

Further, the n' type semiconductor region 9 corresponding to the cathode region of the diode element D1 is formed integrally with the n' type semiconductor region 9 which supplies the operating potential Vcc to the n type well region 2. With this configuration, the element isolation area (the area occupied by the element isolation insulating film 4) between the n-type semiconductor region 9 of the diode element D1 and the n-type semiconductor region 9 on the main surface of the n-type well region 2, and Since the wiring connection area (the area of the wiring 14, the connection hole 13, and their margins) can be eliminated, the degree of integration of the DRAM can be improved by an amount corresponding to this eliminated area.

Further, the n'-type semiconductor region 9 corresponding to the cathode region of the diode element D1 is formed in the same manufacturing process as the n'-type semiconductor region 9 that supplies the operating potential Vcc to the n-type well region 2. With this configuration, the n° type semiconductor region 9 of the diode element D1 can be formed using the process of forming the n° type semiconductor region 9 on the main surface of the n type well region 2. The DRAM manufacturing process can be reduced by the amount corresponding to the step of forming region 9.

Further, the n-type semiconductor region 9 corresponding to the cathode regions of the diode elements D1 and D2 is connected to the complementary MISF
ET's n-channel MISFETQn, P-channel MIS
placed between each of the FETQPs. With this configuration,
The n° type semiconductor region 9 to which the operating potential vcc of the diode element D1 is supplied, and the reference potential V of the diode element D2.
The distance between each of the n° type semiconductor regions 9 to which ss is supplied (between the operating potential Vcc and the reference potential Vss) is made close to reduce the parasitic nature of the P type well region 3 (or the p- type semiconductor substrate l) between the two. Since the resistance value can be reduced, it is possible to shorten the excessive current paths between the n-type semiconductor region 9, the p-type well region 3, and the n-type semiconductor region 9, thereby further improving the electrostatic breakdown strength. Further, since the excessive current path is shortened, fluctuations in the base potential of the parasitic thyristor can be immediately reduced during operation of the DRAM, and the latch-up withstand voltage of the DRAM can be improved.

(Example 2) Example 2 is a second example of the present invention in which the diode element of Example I is arranged around a complementary MISFET.

Complementary MISFET of DRAM which is Embodiment ① of the present invention
The structure of the diode element is shown in FIG. 4 (schematic layout diagram).

As shown in FIG. 4, the DRAM of this embodiment
Diode elements D1 and D2 are arranged around the array region 20 of ISFETQP, respectively. As a result, complementary MIS
FET n-channel MISFETQn, p-channel MI
The SFETQp can be arranged close to each other, and the length of the wiring 14 can be shortened, for example, when configuring an inverter circuit.

The DRAM configured in this manner can produce substantially the same effects as those of the embodiment I described above.

Furthermore, each of the diode elements D1 and D2 is arranged around the complementary MISFET (array regions 20 and 21) with the intervening one. With this configuration, the complementary MI
The SFET n-channel MI 5FETQn and p-channel MISFETQp can be arranged close to each other, and the wiring length of the wiring 14 connecting them can be shortened, thereby increasing the signal transmission speed and increasing the circuit operation speed of the DRAM. .

(Embodiment 2) This embodiment 2 is a third embodiment of the present invention in which the anode region of the diode element of the embodiment 2 is formed of a semiconductor substrate.

Complementary MISFET of DRAM which is Embodiment ① of the present invention
The structure of the diode element is shown in FIG. 5 (cross-sectional view of main parts).

As shown in FIG. 5, each of the diode elements D1 and D2 of the DRAM of this embodiment (2) has an anode region formed of a p° type semiconductor substrate, and a cathode region formed on the main surface of the P− type semiconductor substrate. It is composed of the formed n-type semiconductor region 9. Each of the diode elements D1 and D2 is connected to an n-type well region 3.
Although the junction breakdown voltage is slightly higher than when the anode region is used as the anode region, as in Example I, the n-type well region 2 and the
The junction breakdown voltage can be set lower than the junction breakdown voltage of the pn junction with the type well region 3.

The DRAM configured in this manner can produce substantially the same effects as those of the embodiment I described above.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the present invention, each of the n° type semiconductor region 9 on the main surface of the n type well region 2 of Example I and the n° type semiconductor region 9 corresponding to the cathode region of the diode element D1 is connected to the element isolation insulating film 4. It may be separated by

Similarly, one aspect of the present invention is the n-channel MISF of Embodiment I.
an n-type semiconductor region 9 corresponding to the source region of ETQn;
Each of the n° type semiconductor regions 9 corresponding to the cathode region of the diode element D2 may be formed integrally. in this case,
n corresponding to the source region of n-channel MISFETQn
The ゛-type semiconductor region 9 also serves as a diode element D2.

Further, the present invention provides a p° type semiconductor region 11 on the main surface of the p type well region 3 in the embodiment (2), and supplies a reference potential Vss to each of the p type well region 3 and the p° type semiconductor substrate 1. It can be applied to semiconductor integrated circuit devices.

Further, the present invention can be applied to a single well structure in which only an n-type well region is formed on the main surface of a P-type semiconductor substrate.

The present invention also provides a semiconductor integrated circuit device that employs a twin well structure in which an n-type well region and a p-type well region are provided on the main surface of an n-type semiconductor substrate, or a p-type well region on the main surface of an n-type semiconductor substrate. The present invention can be applied to a semiconductor integrated circuit device that employs a single well structure with a well region.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Electrostatic breakdown strength can be improved in a semiconductor integrated circuit device having complementary MISFETs.

Furthermore, the degree of integration of the semiconductor integrated circuit device can be improved.

Furthermore, the manufacturing process of the semiconductor integrated circuit device can be reduced.

Further, the operating speed of the semiconductor integrated circuit device is high.

You can measure the speed ratio.

Further, the latch-up withstand voltage of the semiconductor integrated circuit device can be improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view of essential parts of a complementary MISFET and a diode element arranged in a peripheral circuit of a DRAM according to Embodiment I of the present invention. FIG. 2 is a plan view of essential parts of the complementary MISFET and diode element. , FIG. 3 is a schematic layout diagram of the complementary MISFET and diode elements, and FIG. 4 is a complementary MISFET of the DRAM according to the embodiment
A schematic layout diagram of ISFET and diode elements, FIG.
FIG. 3 is a cross-sectional view of main parts of an ISFET and a diode element. In the figure, 1... semiconductor substrate, 2, 3... well region,
4... Element isolation insulating film, 5... Channel stopper region. 6... Gate insulating film, 7... Gate electrode, 8, 9,
10°11...Semiconductor region, 14.17...Wiring,
20.21...Arrangement area, Q...MISFET, D
...It is a diode element.

Claims (1)

[Claims] 1. A first well region formed in a region of a main surface of a semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate is provided with a first well region.
A semiconductor integrated circuit comprising a first semiconductor region having the same conductivity type as the well region and having a higher impurity concentration than the well region, and having a complementary MISFET, in which power is supplied to the first well region through the first semiconductor region. In the circuit device, on the main surface of a second semiconductor region formed in another region of the main surface of the semiconductor substrate or in another region, the second semiconductor region has the same conductivity type as the semiconductor substrate and has a higher impurity concentration than that of the semiconductor substrate, a third semiconductor region having the same conductivity type as the first well region or the first semiconductor region and having a higher impurity concentration than the first well region; A semiconductor integrated circuit device characterized in that the same power supply as that supplied to each of one semiconductor region is supplied. 2. The semiconductor integrated circuit according to claim 1, wherein the third semiconductor region on the main surface of the semiconductor substrate or the second semiconductor region is configured integrally with the first semiconductor region of the first well region. Device. 3. The third semiconductor region on the main surface of the semiconductor substrate or the second semiconductor region is formed in the same manufacturing process as the first semiconductor region of the first well region. The semiconductor integrated circuit device described in . 4. The third semiconductor region on the main surface of the semiconductor substrate or the second semiconductor region is connected to the n-channel MISFET of the complementary MISFET.
4. Each semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged between an SFET and a p-channel MISFET. 5. Claims 1 to 3, wherein the third semiconductor region on the principal surface of the semiconductor substrate or the second semiconductor region is arranged around the complementary MISFET with the intervening one therebetween.
Any of the semiconductor integrated circuit devices described in .