JPH0415494B2 - - Google Patents

Info

Publication number
JPH0415494B2
JPH0415494B2 JP60131792A JP13179285A JPH0415494B2 JP H0415494 B2 JPH0415494 B2 JP H0415494B2 JP 60131792 A JP60131792 A JP 60131792A JP 13179285 A JP13179285 A JP 13179285A JP H0415494 B2 JPH0415494 B2 JP H0415494B2
Authority
JP
Japan
Prior art keywords
data
memory
memories
read
hierarchical storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60131792A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61290550A (ja
Inventor
Yasuhiko Matsura
Junichi Takuri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60131792A priority Critical patent/JPS61290550A/ja
Publication of JPS61290550A publication Critical patent/JPS61290550A/ja
Publication of JPH0415494B2 publication Critical patent/JPH0415494B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP60131792A 1985-06-19 1985-06-19 階層記憶制御方式 Granted JPS61290550A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60131792A JPS61290550A (ja) 1985-06-19 1985-06-19 階層記憶制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60131792A JPS61290550A (ja) 1985-06-19 1985-06-19 階層記憶制御方式

Publications (2)

Publication Number Publication Date
JPS61290550A JPS61290550A (ja) 1986-12-20
JPH0415494B2 true JPH0415494B2 (OSRAM) 1992-03-18

Family

ID=15066237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60131792A Granted JPS61290550A (ja) 1985-06-19 1985-06-19 階層記憶制御方式

Country Status (1)

Country Link
JP (1) JPS61290550A (OSRAM)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2714952B2 (ja) * 1988-04-20 1998-02-16 株式会社日立製作所 計算機システム
JPH0661068B2 (ja) * 1989-07-18 1994-08-10 株式会社日立製作所 記憶再配置方法および階層化記憶システム
FR2707774B1 (fr) * 1993-07-15 1995-08-18 Bull Sa Procédé de gestion cohérente des échanges entre des niveaux d'une hiérarchie de mémoires à au moins trois niveaux.
FR2707776B1 (fr) 1993-07-15 1995-08-18 Bull Sa Procédé de gestion de mémoires d'un système informatique, système informatique mémoire et support d'enregistrement mettant en Óoeuvre le procédé.
US5530832A (en) * 1993-10-14 1996-06-25 International Business Machines Corporation System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
EP0661638A1 (en) * 1993-12-28 1995-07-05 International Business Machines Corporation Method and apparatus for transferring data in a computer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394731A (en) * 1980-11-10 1983-07-19 International Business Machines Corporation Cache storage line shareability control for a multiprocessor system

Also Published As

Publication number Publication date
JPS61290550A (ja) 1986-12-20

Similar Documents

Publication Publication Date Title
KR100318104B1 (ko) 공유 인터벤션을 지원하는 비균등 메모리접근 데이터처리시스템
EP0598535B1 (en) Pending write-back controller for a cache controller coupled to a packet switched memory bus
US6826653B2 (en) Block data mover adapted to contain faults in a partitioned multiprocessor system
US6260117B1 (en) Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency
JPH11282820A (ja) スイッチをベースとするマルチプロセッサシステムに使用するための順序サポート機構
JPH11282821A (ja) 同時トランザクションを依存性で管理するための低占有度プロトコル
JP2000227908A (ja) 共用介入サポ―トを有する不均等メモリ・アクセス（ｎｕｍａ）デ―タ処理システム
JPH0576060B2 (OSRAM)
US6266743B1 (en) Method and system for providing an eviction protocol within a non-uniform memory access system
US6751705B1 (en) Cache line converter
JP2000010860A (ja) キャッシュメモリ制御回路及びプロセッサ及びプロセッサシステム及び並列プロセッサシステム
JP2005539282A (ja) 単一のコヒーレントなシステム内の分散コンピュータ・ノードにキャッシュ・コヒーレンスを提供するのにグローバル・スヌープを使用する方法および装置
JP2000250883A (ja) 不均等メモリ・アクセス・システムにおいてトランザクションのキャンセルによるデータ損失を避けるための方法およびシステム
JPH1031625A (ja) マルチ・プロセッサ・システムにおける改良されたコピーバック性能のためのライトバック・バッファ
US6546465B1 (en) Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol
US7024520B2 (en) System and method enabling efficient cache line reuse in a computer system
JPH0319976B2 (OSRAM)
JPH0415494B2 (OSRAM)
JPH05324468A (ja) 階層化キャッシュメモリ
US6895476B2 (en) Retry-based late race resolution mechanism for a computer system
JPS6154547A (ja) ３レベルの階層メモリを備えたデ−タ処理システム
US20050198438A1 (en) Shared-memory multiprocessor
US6397295B1 (en) Cache mechanism for shared resources in a multibus data processing system
JPH0529943B2 (OSRAM)
JPS6131495B2 (OSRAM)