JPH0415494B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the control of hierarchical storage, and particularly to a hierarchical storage control method that employs a store-in method as store control between the memory concerned and a lower memory.

[Background of the invention]

Conventionally, as a method to bridge the speed difference between a high-speed arithmetic processing unit and a low-speed, large-capacity main memory (hereinafter referred to as MS), a high-speed, small-capacity buffer memory, as described in Japanese Patent Application Laid-open No. 48-38036, has been proposed. A method has been put into practical use in which a BS (hereinafter referred to as BS) is provided in an arithmetic processing unit to form a two-layer memory device.

In recent years, due to advances in semiconductor technology, arithmetic processing devices and
While BS is getting faster every year, the speed of MS has hardly improved due to the demand for large capacity and low price, and the speed gap between the two is widening, making it difficult to improve performance as the speed of MS becomes an obstacle.

As an improvement measure, as shown in the above-mentioned known example,
A new medium-speed, medium-capacity work memory (hereinafter referred to as WS) is installed between BS and MS, and level 1 is
There is a method of creating a three-layer memory device in which BS, level 2 is WS, and level 3 is MS.

In general, when data at a certain level is updated, the corresponding data at a lower level is immediately updated, which is called the "store-through" method, and updating when returning the data to a lower level is called the "store-through" method. This is called the "in" method.

When controlling between BS and MS, between BS and WS, or between WS and MS using the store-in method, if the desired data is not in the memory, it is stored in another memory at the same level (another BS or another WS). Latest data may exist. Therefore, in this case, a request is issued to read the data from the memory at the lower level, and at the same time, queries are made to other memories at the same level to check whether the latest data for the data exists. , if the latest data exists, the memory must capture this latest data and replace the data in the lower level memory with this latest data. In this way, BS→MS(WS)
The transfer of the latest data such as →BS or WS→MS→WS and writing to each memory will be referred to as bypass operation hereinafter.

[Purpose of the invention]

An object of the present invention is to efficiently perform a bypass operation in hierarchical storage using the store-in control method as described above. In other words, in the case of a cache miss, data is transferred between store-in memories or between a store-in memory and a lower memory. Improving transfer control,
The purpose is to improve memory overhead.

[Summary of the invention]

In the present invention, a plurality of first memories at the same level and a second memory at a lower level commonly connected to the first memories constitute a hierarchical memory, and a store from the first memory to a second memory is a store. The premise is a hierarchical storage control method that is controlled based on the In method.

In such a manner, the present invention provides that when the data requested for one of the first memories is not present in the one of the first memories, the one of the first memories is transferred to the second memory. Issue a read request for the data to the second memory to read the data from the second memory, and at the same time update data that is an updated version of the data to the other first memory. If the update data exists as a result of the inquiry, the update data is transferred from the other first memory to a second memory, and the second memory reads the update data from the memory. the updated data is replaced with the updated data and the updated data is transferred to one of the first memories, and when the data replacement is completed, the data is sent from one of the requesting first memories. The present invention is characterized by a hierarchical storage control method configured to suspend data transfer to the request source until a transfer permission signal is received.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall block diagram of this embodiment, in which 0 to 3 are arithmetic processing units (hereinafter referred to as IP0 to 3), and 4-0 to 4-3 are buffer memories (hereinafter referred to as IP0 to 3) of each of IP0 to IP3. BS4-0~4-3
), and 5-0 to 5-3 are BS4-0 to
The buffer address array (hereinafter referred to as BAA5-0) stores the addresses of the data stored in 4-3.
~5-3). 6-0 and 6-1 are
The work memory (hereinafter referred to as WS6-0, 6-1) is shared by each set of IP0 and IP1, and IP2 and IP3, and 7-0 and 7-1 are the control circuits (hereinafter referred to as WS6-0 and WS6-1) of each of WS6-0 and 6-1. WSC7-0, 7-1). 17 is a main memory (hereinafter referred to as MS) shared by the WSs 6-0 and 6-1. 18
-24 are interface cables (hereinafter referred to as CB18-24) that connect the units as shown in FIG. The above are the constituent elements, of which
A multi-layer memory device is constituted of three layers: BS (hereinafter, when referring to the entire BS without considering individual BSs, the reference numerals are omitted) as level 1, WS as level 2, and MS as level 3. In the following description of the embodiment, it is assumed that control between BS and WS is performed using a store-through method, and control between WS and MS is performed using a store-in method. Here, CB18-21 and CB23,
24 is shown with a thick solid line, and only CB 22 is shown with a thin solid line to distinguish that the former consists of data lines and control lines, while the latter consists of only control lines.

Next, the guarantee of data consistency between memories shown in this embodiment will be explained. Data match guarantee is BS−
It can be divided into consistency guarantees between BSs, between BSs and WSs, between WSs and WSs, and between WSs and MSs.

FIG. 2 shows a matching guarantee circuit between BS and BS and BS and WS when controlling BS and WS using the store-through method. Figure 2 shows a part of WSC7-0 in more detail, with 25 and 26 being front address arrays (hereinafter referred to as FAA25 and 26);
27 is a determination circuit, and 28 is a work address array (hereinafter referred to as WAA 28). Here, the F.A.A.A.
25 and FAA26 are copies of BAA5-0 and BAA5-1, and WAA28-0 is WS
6-0 is stored. When a store request occurs at IP0 shown in Figure 1, BAA5-0 is searched, and if there is an address of data to be stored, BS4-0
If there is, it is not stored. Next, since it is a store-through method, WS6-0 has BS4-0
This data is stored regardless of whether the
WSC7-0 searches for WAA28-0, and if the address is found, it is stored in the WS unconditionally; if not, it is stored in the WS.
The address data is read from the MS and then stored, but reading from the MS will be described later. In this state, if data for the address also exists in BS4-1, the contents of BS4-1 are outdated, and BS4-0 and WS6-0 match, but BS4-1 and BS4 -0, which is inconsistent with WS6-0. Next, search FAA26 to check whether the address exists in BS4-1, and if it exists, cancel the address in FAA26 and use CB19 to cancel the address in BAA5-1, BS4-1.
Cancel the corresponding address of 1. In this state, IP1 can no longer use the data at the address in BS4-1, and if it wants to use it, it will have to read it from WS6-0.
4-0-WS6-0 and BS4-1-WS6-0 are guaranteed.

Concordance can be guaranteed between BS4-2, 4-3 and WS6-1 by thinking in the same way. In addition, in the case of data read operation, BS4-0 and BS4-
Since no discrepancy occurs with 1, BS4-0, WS6-
It is searched in the order of 0 and if it is not found in WS6-0, it is read from MS. The WS6-1 series is also the WS6-0 shown in Figure 2.
It is similar to the system.

In the above example, it was expressed that if the relevant data was not present in either BS4-0 or WS6-0, it would simply be read from the MS, but in reality, the latest data is stored in WS6-1 because of the store-in method between WS and MS. There is a possibility that it exists. Therefore, the WSC 7-0 has a table with a memory configuration shown in FIG. 3 to control the timing between the WSs.

In FIG. 3, numeral 31 is an address register which stores the address requested by IP0, the lower bits indicate the column address of WAA 28-0, and the upper bits are registered as entries. 32-0 is an exclusive bit array (hereinafter referred to as EXA32-0) and is a WAA
Each entry in 28-0 indicates whether there is a possibility of it existing in BS4-1 and WS6-1. If it is "1", there is no possibility (exclusive), and if it is "0", there is a possibility. It shows that there is. 33-0 is a change bit array (CBA33-0), WAA
Each 28-0 entry has information on whether or not it has been stored, and if it has been stored, "1" is written. 34
is a comparator that compares the entry registered in the WAA 28-0 with the upper bit of the address register 31, determines whether or not the address exists in the WS 6-0, and outputs "1" if the address exists. here,
WAA28-0, EXA32-0, CBA33-0
Both have a 4-row configuration, but the number of rows is arbitrary, and the WSC7-1 also has a WAA28-
1, EXA32-1, CBA33-1 are available.

FIG. 4 shows control between memories at each level when data at the address does not exist in either BS4-0 or WS6-0. is BAA5 in Figure 1
As a result of searching for -0, it indicates that it has not reached BS4-0 (NiBS; Not in BS).
Inquires of WS6-0, and also sends write data in case of store. As a result of searching WAA28-0 shown in Figure 3, "0" is output from the comparator 34.
Not in WS6-0 (NiWS; Not in
WS).

When NiWS is detected, WS6-0 is MS1
At the same time as requesting 7 to read the data,
Sends the address of the data to WS6-1 and verifies whether the latest data is available. WSC7-1 is third
As shown in the figure, the address register and WAA28-1,
Has EXA32-1, CBA33-1 and a comparator,
The address sent from WS6-0 is stored in this address register, and WAA28-1, EXA32
-1, the search sequence for CBA33-1 is activated. There are 8 possible search results, of which:
If WS6-1 or BS4-1 has the latest data, the output of the comparator becomes "1" and WS6
-1 indicates that the relevant data exists (WS; in WS), and the EX bit of EXA32-1 is 1.
WS6-0 indicates that there is no relevant data, and the C bit of CBA33-1 is 1, and WS6-0
This is only the case where 1 indicates that the data has been updated. In the remaining seven cases, the data in the MS is the latest, and the data read from the MS is sent to the WS 6-0 upon request. When the state of 0, C bit = 0. It also reports to WS6-0 that the bypass operation has been activated. The MS sends this bypass data as read data to the WS 6-0 in place of the old data read at the request of the MS, and at the same time, the MS itself stores the data at the corresponding address to update the data. Note that this is not a required operation, and the latest data may be managed while still existing in the WS without being written to the MS.
The data sent from the MS is stored in WS6-0, but if the request from IP0 is a read request, this stored data is transferred to BS4-0,
If the request is for a store, data from IP0 is further stored in this stored data.

FIG. 5 is a time chart showing .about. in FIG. 4. What should be noted here is that
The busy signal sent from WS6-0 is latched in MS17, suspending the sending of read data,
If the bypass is activated as a result of the search, WS6
-1 reports this to WS6-0, and WS6-0 receives the bypass data and sends it to the MS.
The purpose is to drop the busy signal and make it possible to accept bypass data by determining the time until it can be sent from the MS in place of the read data. On the other hand, if the bypass operation is not started, the busy state is immediately dropped and read data is accepted.

Contrary to Figure 4, if WS6-1 does not have the relevant data and WS6-0 has the latest data, WS6-1
This activates the bypass operation, but is handled in the same way as described above.

FIG. 6 shows a circuit configuration for realizing the operations shown in FIGS. 4 and 5. As in FIG. 2, 27 is a determination circuit, and ~ is a fourth circuit.
This means the same operation as in FIG. A request control circuit 61 sends a read request to the MS 17 when NiWS is detected. 62 is a busy control circuit, when MS
A busy signal is sent at 17, and the busy signal is reset at 17. 63 is an inquiry control circuit shown in FIG. 3, which checks the possibility that the data exists in BS4-1 and WS6-1, and if there is a possibility, makes an inquiry. 64 is also an inquiry circuit, which judges whether or not the latest data of the relevant data exists in WS6-1 in response to an inquiry, and if it exists, it sends it to WS6-1.
0 and activates simultaneous bypass operation;
Send the latest data to 68 data registers. 65
is a request acceptance latch, and when a read request is accepted, data is read from the RAM 71 and set in the read data register 69. The busy reception latch 66 latches the busy signal sent from the busy control circuit 62 and sends it to the selector 67. When the busy signal is set, the selector 67 stops data transfer to WS6-0, and when the busy signal is set, the selector 67 stops data transfer to the read data register 6.
9 is selected, the data register 68 is selected and the data is transferred to the WS 6-0. Therefore, as described above, by keeping the busy signal in the set state until the bypass data is sent to the MS, the sending of read data can be suppressed. Note that resetting the busy signal is equivalent to the MS receiving a transfer permission signal. 70 is a write data register, and the latest data in the data register 68 may be transferred and written to the RAM 71 at any time.

Note that when applying the present invention to a two-layer memory of BS-MS, the following precautions must be taken. first
BS-MS shall be controlled in a store-in manner;
Second, a control line corresponding to CB22 that conveys the above control information is provided between the BS and another BS, or a memory control unit (MSC) is interposed between the BS and the MS, and in this MSC, one B.S.
Receives NiBS signal from and transmits it to other BS,
The above bypass control is performed when an iBS signal is obtained from another BS. In the latter case, the busy control circuit 62, inquiry control circuit 63 and inquiry control circuit 64 shown in FIG. 6 are provided within this MSC.

Furthermore, when the present invention is applied to a three-layer memory of BS-WS-MS, and the BS-WS is controlled by a store-in method, the above-mentioned BS-MS 2
Same as for hierarchical memory, but with the above in WS
It is sufficient to combine the functions of MSC and MS.

〔Effect of the invention〕

According to the present invention, when writing update data to the bypass operation and the lower level memory itself, each operation can be executed independently, and other memories at the same level as the memory concerned can report on the presence or absence of the latest data. Since the transfer of data read from a memory at a lower level can be suspended until the data is updated, an efficient bypass operation can be performed and memory overhead can be reduced.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram of an embodiment of the present invention, Fig. 2 is a block diagram showing a matching control method between BS-BS and BS-WS, and Fig. 3 is a block diagram showing a method of controlling inquiries between WSs. Figure 4 is a diagram showing the control flow of the bypass operation, Figure 5 is a time chart showing the control status of ~ in Figure 4, and Figure 6 is related to Figures 4 to 5. FIG. 0 to 3... Arithmetic processing unit, 4-0 to 4-3...
Buffer memory, 6-0, 6-1...work memory, 7-0, 7-1...work memory control, 17...main memory, 18-24...interface cable.

Claims (1)

[Scope of Claims] 1. A plurality of first memories at the same level and a second memory at a lower level commonly connected to the first memories constitute a hierarchical storage, and a plurality of first memories at the same level and a second memory at a lower level commonly connected to the first memories constitute a hierarchical storage, and the first memory is connected to the second memory from the first memory to the second memory. In a hierarchical storage control scheme in which stores are controlled based on a store-in scheme, when data requested for one of the first memories does not exist in one of the first memories, the first memory one of them issues a read request for the data to the second memory to read the data from the second memory, and at the same time requests the other first memory to read the data from the second memory.
A query is made as to whether or not updated data that is an updated version of the data exists in the memory, and if the updated data exists as a result of the query, the updated data is transferred from the other first memory to the second memory. the second memory replaces the data read from the memory with the update data and transfers the update data to one of the first memories;
and a hierarchical memory configured to suspend data transfer to the request source until a transfer permission signal is received from one of the request source first memories when the data replacement is completed. control method. 2. In the hierarchical storage control system according to claim 1, the second memory transfers the updated data to one of the first memories and also writes the updated data to itself. Features a hierarchical storage control method. 3. In the hierarchical storage control system according to claim 1, if the update data does not exist as a result of the inquiry, the second memory transfers the data read from the memory to the first memory. A hierarchical storage control method characterized in that data is transferred in one layer.