JPH04154345A - Preferential processing system - Google Patents

Abstract

PURPOSE:To execute the preferential processing by the simple control by sending out data in accordance with data sent out previously and existence of a competition state, and using a clock to be inputted in common. CONSTITUTION:At the time of rise of each data, some of AND circuits 14-18 are masked by inverters 11-13, and a control part 1 sends out information of a fact that they are masked, and each data to a discriminating part 2. The discriminating part 2 sends out data corresponding to data D1-D1 in accordance with competition information from the control part 1 and a value of holding data in a converting part 3. In such a way, in accordance with which of the data D1-D3 become a binary one level, one data sent out preferentially in the data D1-D3 by outputs of data S1, S2 is displayed.

Description

TECHNICAL FIELD The present invention relates to a priority processing system, and more particularly to a priority processing system that sends out data corresponding to one of N types of input data.

Conventional technology In general, when performing supervisory control in optical communications, a process is performed in which multiple input signals are received and priority is given on a first-come, first-served basis depending on the input signal, and a process is performed in which priority is given to the youngest number in the event of conflicting input signals. ing. In order to realize these image processes, conventional priority processing systems detect each input signal using a plurality of sampling clocks having mutually different timings.

The conventional priority processing system will be explained with reference to FIG. FIG. 3 is a circuit diagram of the main parts of a conventional priority processing system.

In the figure, the conventional priority processing system inputs three types of data D1 to D3 and outputs data B1 and S2 in accordance with these inputs.

The data input into this system from the outside is valid data for the two-way label, and if this is detected, priority processing is performed regardless of the input values of other data. In this priority processing, priority is given to the data for which the binary level signal was received first, but in the case of simultaneous occurrences, that is, in the case of conflict, the priority order is Di > D2 > D3 from the highest to lowest, and this is called the youngest priority processing. It has become. In order to realize this process of giving priority to the smallest number, the timings of the clocks C2 to C4 supplied from the outside are set in ascending order of C2>C3>C4.

In other words, D-type flip-flops (hereinafter DF
Three types of clocks 02 to C4 are inputted from the outside in order to hold data in the clocks 117 to 119 (abbreviated as F) with priority given to the smallest number. And each D FP117-119
Data S1 and S2 are sent out by the output, and the next stage circuit is controlled.

7”-9Sl and US2 Ha, 111M110 (D
This is the result of converting the outputs of DFFLLs 7 to 119 by OR circuits 211 and 212 in converter 2[. That is, D
When the output of FFf17 is a binary level, the OR circuit 21.
Only the output of 1 is a binary level, and the data Sl is -1"
S2 fr becomes “0”. Mata, DFPIIfl
) When the output is a binary level, only the output of the OR circuit 212 is a binary level, and data Sl is “0” and S2 is “1”.
”.Furthermore, when the output of DFFI 19 is a binary level, the outputs of OR circuits 211 and 212 are both 2
road level, data s1 is “1” and S2 is “l”
becomes.

In addition, the control unit 1f (inside of 1 is an AND circuit [4 to If6
and inverters 01-113 are provided, and mask processing of input data is performed by these. for example,
If data DI becomes valid first, clock c
2, the output is inverted by the inverter 113, and the AND circuit 215 and 1
The output of 16 is masked to a binary 0 level. This masked data then becomes non-priority.

Similarly, inverter 111 masks the outputs of AND circuits 114 and 115, and inverter 112 masks the outputs of AND circuits 116 and 114.

By the way, in the above-mentioned conventional priority processing system, when there is a conflict between input data, if the conflicting data includes the previously transmitted data, the previous data is transmitted, and if the conflicting data does not include the previously transmitted data, the previous data is transmitted; If you try to perform a process of transmitting data with priority, multiple controls will be required. In other words, since the timing of the three sampling clocks that detect data differs depending on the corresponding data, if the next valid data has a lower number than the previously sent data, this valid data is Not a priority. Therefore, there is a drawback that the control unit 110 must be cleared once.

For example, consider a case where after data D3 becomes valid, data D3 becomes invalid in the next frame.

In such a case, even if the data D■ or D2, which has a lower number than the data D3, is binary level data, the timing of the clock c4 is later than that of C2 and C3, so
At the latch timing of clocks C2 and C3, data D1 and D2 are still masked by D3 held in the DFP 119, and each D
This method requires operations such as clearing the FF, and has the disadvantage that it is difficult to implement the system.

Note that the reset signal RO is set to 2 when the system is powered on.
AND circuit 1o because it becomes a forward level.

Resetting is performed by setting only the reset signal R1 of one input to a binary level.

Furthermore, since the clock timing differs for each data, there is also a drawback that the changing points and frequencies of the transmitted data s1 and s2 are not constant.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a priority processing system that can perform the above-mentioned priority processing with simple control.

Structure of the Invention The priority processing system according to the present invention has N types of input (
N is an integer greater than or equal to 2)), the priority processing system includes a holding means for holding the data sent immediately before by the own system;
a conflict detection means for detecting that a plurality of types of data are input in conflict; When the data held in the holding means is included, the held data is sent, and when the data held in the holding means is not included, one selected according to a predetermined priority order is sent. and means for transmitting data corresponding to the input data when the conflict detection means does not detect a conflict state.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of a priority processing system according to the present invention. In the figure, the priority processing system according to an embodiment of the present invention includes a control unit 1 that detects a conflicting state of three types of data D1 to D3, and a conversion unit that retains the data sent immediately before and converts the data. 3, and a determining unit 2 that performs priority processing and transmits data based on the presence or absence of a conflict condition and the data transmitted immediately before, and the control signals include a clock C1 and a reset signal R.
There is only 1.

The converter 3 includes OR circuits 31 and 32 and DFFs 33 and 3.
4, and the output of DFP3B is data SL, D
The output of FF34 becomes data S2. 0FF33.34
Both hold data at the rising timing of the clock CI, and clear the held data at the falling timing of the reset signal R1.

The control unit 1 includes AND circuits 14 to 18 and an inverter 11
- 13, and when inputting data D1 to D3, sends the data to the determining unit 2 and detects a data conflict state. That is, at the rising edge of each data, some of the AND circuits 14 to 18 are masked by the inverters 11 to 13, and information indicating that the data is masked and each data are sent to the determining section 2. For example, if there is a conflict between data D2 and D3, the AND circuit 1
4, 15, 17, and 18 are masked and their outputs are all binary O level. Therefore, the fact that the data D2 and D3 have become a binary level and that the output of the AND circuit 16 has become a binary level is input to the discriminator 2, and the discriminator 2 detects the conflict state between the data D2 and D3. It can be recognized.

The determination unit 2 includes three selectors 21, 22 and 23, and selects data corresponding to data D1 to D3 according to the conflict information from the control unit 1 and the value of the data held in the conversion unit 3. Send. The selection condition for each selector is the fourth
As shown in the figure. That is, each selector outputs the data input to the four input terminals dO to d4 from the Y terminal according to the values of the control input terminals A and B, and when both A and B are "0", the input terminal d.

data at terminal d1 when A is "1" and B or "0", data at terminal d2 when A is "0" and B is "1", and data at terminal d2 when both A and B are "1". Select data at input terminal d4.

Returning to FIG. 1, the output of the selector 21 is input to the DFF: 33 via the OR circuit 31, and the output of the selector 22 is input to the DFP 34 via the OR circuit 32.
The outputs of 3 are input to DFFs 33 and 34 via OR circuits 31 and 32. That is, the values of data S1 and S2 are determined by the outputs of selectors 21 to 23.

In such a configuration, in this system, data D1 to D
Depending on which one of the data Di-DB becomes the binary level (valid), one of the data Di-DB that is sent out with priority is displayed by the output of the data SL and S2. The values of data D1 to D3 in the priority processing and data 5ISS2
The relationship with the value of will be explained using FIG. FIG. 2 is a table showing the relationship between the value of data DI-D3 and the values of data Sl and S2, and shows a case where processing is performed in chronological order in the order of items 1 to 2.

First, item (2) shows the initial state, and all data values are at binary 0 level. Since data S1 and S2 are both "O", nothing is sent out, and "0" is input to both terminals A and B of each selector.

Therefore, each selector is in a state of selecting dO.

In this state, only data D1 is “
1'', the AND circuits 16 to 17 are masked by the inverters 11 and 12.

Therefore, the data Dl is input as is to the selector 21, and its Y terminal becomes "1". At this time, selector 22
Since the Y terminals of and 23 are "0", when the clock CI rises, "1" is held in the DFF33 and "0" is held in the DFF34, and the data Sl is sent out as "1" and the data S2 as "0".

At this time, “1” is placed on terminal A of each selector, and “0” is placed on terminal B of each selector.
” is input. Therefore, each selector is in a state of selecting dl.

In that state, only data D2 is 1 as in item ■.
#, the inverter 12 causes the AND circuit 14.
18 is masked. Therefore, the data D2 is input to the selector 22 via the AND circuit 16, and its Y terminal becomes "
1". At this time, since the Y terminals of selectors 21 and 23 are "0", the DPF
33 is 0” DFF34 is held as “1” and data S
1 is sent as "0" and S2 is sent as "1".

In other words, last time, data 81 "1" corresponding to data D1
"S2 "0" was sent, so this was given priority, but since data DI was not input, data s1 and s2 corresponding to data D2 were sent.

At this time, terminal A of each selector is set to "0" and terminal B is set to "0".
1' is input. Therefore, each selector is in a state of selecting dl.

In that state, only data D3 is “
1”, the AND circuit 15 is activated by the inverter 13.
．． 17 is masked. Therefore, the data D3 is input to the selector 23 via the AND circuit 18, and its Y terminal becomes 1". At this time, since the Y terminals of the selectors 21 and 22 are 0", the DFF 33 is inputted at the rising edge of the clock C1.
, DFF34 both hold "1", and data SL is "
1” S2 is sent as “1”.

In other words, last time, data SI “0” corresponding to data D2
Since "821" was sent, this has priority, but
Since data D2 was not input, data S1 and S2 corresponding to data D3 were sent out.

At this time, the terminal A of each selector is set to "1m terminal B".
1'' is input. Therefore, each selector is in a state where it selects d3.

In that state, data D1 and D2 are
compete and both become "L", the AND circuits 16 to 18 are masked by the inverter 11, and the inverter 1
2, the AND circuit 14.degree. 18 is masked. Therefore, the data DI is sent to the selector 21 via the AND circuit 15.
is input, and its Y terminal becomes "1". At this time, the Y terminals of the selectors 22 and 23 are "0", so when the clock CI rises, "1" is held in the DFF33 and "0" is held in the DFF34, so that the data s1 is "1" and the data s2 is "0".
Sent as .

In other words, last time, data S "1" corresponding to data D3
Since "S2""1" was sent out, this was given priority, but since data D3 was not input, data s1 and S2 corresponding to data DI were sent out with priority given to the smallest number.

At this time, the terminal A of each selector is "1" and the terminal B is "1".
0'' is input. Therefore, each selector is in a state of selecting dl.

In that state, data D2 and D3 as in item
compete and both become "1", AND circuits 14 and 18 are masked by inverter 12, and inverter 1
3, the AND circuit 15°17 is masked. Therefore, the data D2 is sent to the selector 22 via the AND circuit 16.
is input, and its Y terminal becomes "1". At this time, since the Y terminals of the selectors 21 and 23 are "0", the DFF33 is set to "0" at the rising edge of the clock C1.
"1" is held in "1", data Sl is "0" and S2 is "1"
Sent as .

In other words, last time, the data Sl “1” corresponding to the data DI
``S2 ``Since 0'' was sent out, priority was given to this one, but since data D1 was not input, data S1 and S2 corresponding to data D2 were sent out with priority given to the smallest number.

At this time, terminal A of each selector is set to "0" and terminal B is set to "0".
1" is input. Therefore, each selector is in a state of selecting d2.

In this state, data D1 to D3 compete as shown in item
13, AND circuits 14 to 18 are masked.

Therefore, data D2 is input as is to the selector 22,
The Y terminal becomes "1". At this time, the Y terminals of selectors 21 and 23 are "0", so when the clock Ct rises, DFF33 holds "0", DFF34 holds "1°", and data S1 is sent as "0" and S2 is "1". be done.

In other words, last time data S1 “0” corresponding to data D2
"S2 "1" has been sent, so this is given priority, and the data Sl and S corresponding to data D2 are given priority instead of the smallest number priority.
2 was sent out.

At this time, terminal A of each selector is set to "0" and terminal B is set to "0".
1'' is input. Therefore, each selector is in a state of selecting d2.

In this state, when all of the data D1 to D3 become 0'' as in item (3), all the AND circuits 14 to 18 are not masked. Therefore, nothing is input to the selectors 21 to 23, and each Y terminal is set to 0. ” becomes. Therefore, clock C1
“0” to DFP33 and “0” to DFF34 at the rising edge of
” is held, and data S1 is sent as “0” and data S2 as “0”.

In other words, last time, data Sl “0” corresponding to data D2
" 82 "1" was sent, so this was given priority, but data D2 was not input, and data D1 and D3 were not input either, so data S1 and S2 indicating the initial state were sent.

At this time, the terminal A of each selector is “0” and the terminal B is “0”.
0'' is input. Therefore, each selector is in a state where it selects dO, that is, an initial state.

In this state, data D1 to D3 compete as shown in item
13 masks AND circuits 14-18. Therefore, the data DI is directly input to the selector 21,
The Y terminal becomes "1". At this time, since the Y terminals of selectors 22 and 23 are "0", at the rising edge of clock CI, "1" is held in DFF33 and "0" is held in DFF34, and data S1 is held as "1" and data S2 is held as "0". Sent out.

In other words, since the data S1 and S2 indicating the initial state were sent out last time, the data S1 and S2 corresponding to the data Di were sent out by giving priority to the smallest number.

At this time, the terminal A of each selector is "1" and the terminal B is "1".
0'' is input. Therefore, each selector is in a state of selecting dl.

Thereafter, data transmission is performed based on the same priority conditions.

In short, in conventional systems, the control unit must be cleared at an appropriate timing before processing, taking into consideration the case where the input valid data has a lower number than the previously sent data. In contrast, in the system of this example, there is no need to clear the control section.

In addition, in conventional systems, clocks with different timings were input from the outside in order to detect each data while giving priority to the smallest number, but in this example system, the clocks can be shared and the The changing points and frequencies of the data will be constant.

Furthermore, it is clear that the present invention can be widely applied to monitoring and control in various types of communications in addition to optical communications.

Although the present embodiment has been described for the case where three types of data are input, it is obvious that the present invention can be applied to more types of data. In this case, the number of input bits of each selector may be increased and the number of DFFs may be increased.

As described in detail, the present invention is configured to transmit data according to the previously transmitted data and the presence or absence of a race condition, so that the clock to be input can be shared, and priority processing can be performed with simple control. This has the effect of allowing you to do this.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a priority processing system according to an embodiment of the present invention, FIG. 2 is a table showing the operation of the system in FIG. 1, and FIG. 3 shows selection conditions for each selector in FIG. 1. table,
FIG. 4 is a circuit diagram of a conventional priority processing system. Explanation of symbols of main parts 11-13... Inverter 14-18... Ant circuit 21-23... Selector 31° 2... OR circuit 33° 34 ...DFP

Claims (1)

[Claims] (1) A priority processing system that sends out data corresponding to one of N types of input data (N is an integer of 2 or more), and a holding unit that holds the data that the system sent out immediately before. and conflict detection means for detecting that a plurality of data among the N types of data are input in conflict; and when the conflict detection means detects a conflict state, the retained When the data held in the holding means is included, the held data is sent, and when the data held in the holding means is not included, a predetermined priority order is sent. and means for transmitting data corresponding to the input data when the conflict detection means does not detect a conflict state. priority processing system.