JPH04154294A - Color solid state image camera - Google Patents

Abstract

PURPOSE:To make a color solid state image camera possible to protect the occurrence of vertical color dislocation in a color edge section and to obtain a high resolution by using the first and second color difference signals existing on each line to make their concurrency. CONSTITUTION:A red color difference signal R-Y or blue color difference signal -(B-Y) is contained in either output signal of subtractor 10a or that of subtractor 10b for each line. In this case, a red color difference signal R-Y and blue color difference signal -(B-Y) are selected from subtractors 10a and 10b by changeover switches 16 and 17, respectively, and they are treated for concurrency. That is, a red color difference signal and blue color difference signal existing in each line are used to make their concurrency. Thereby, the occurrence of vertical color dislocation in a color edge section can be protected and vertical high resolution can also be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color solid-state imaging device using a single-plate color solid-state imaging device.

[Prior Art] FIG. 8 shows an example of a color solid-state imaging device.

In the figure, image light from a subject (not shown) is supplied via an imaging lens 1 to a single-plate CCD color solid-state image sensor 2 having a complementary color checkerboard color filter.

FIG. 9 is a schematic color coding diagram of this image sensor 2. As shown in FIG. As shown in the figure, field reading is performed. In the A field, charges are mixed in bares such as A1 and A2, and in the B field, charges are mixed in bares such as Bl. Then, in the A field of the horizontal shift register Hreg, At, A2 .・・・
. In the B field, charges are output in the order of Bl . . . .

Here, the order of charges a, b, ... is the 10th
As shown in the figure, in the AI line, (Cy
), (Ye+Mg), ・-・, and on the A2 line, (Cy+Mg), (Ye×G)・
... On the B1 line, (G+Cy).

(Mg+Ye),..., roar.

The charge outputted from the image sensor 2 as described above is supplied to the CDS circuit (correlated double sampling circuit) 3, and this C
The signal is extracted from the DS circuit 3 as an image signal. This CD
By using the S circuit 3, reset noise can be reduced as is well known.

Note that timing pulses necessary for the above-mentioned image sensor 2 and CDS circuit 3 are supplied from a timing generator 4.

Here, processing for obtaining a luminance signal Y and a chroma signal (color difference signal) from the imaging signal output from the CDS circuit 3 will be explained.

Regarding the luminance signal Y, it is obtained by adding the adjacent signals.6 In Fig. 10, a+b, b+c
, c+d, d+e, . . . - addition signals are sequentially formed.

For example, the A1 line is approximated by the following equation. Here, Cy = B + G, Ye = R10, and Mg = B0R.

Y=t(Cy+G)+(Ye×MgNX1/2= (2
B+3G+2R)xi/2 Furthermore, on the A2 line, it is approximated as shown in the following equation.

Y=i(Cy+Mg)+(Ye10NX1/2=(2
B+3G+2R) xi/2 The other lines of the A field and the lines of the B field are similarly approximated.

The chroma signal is obtained by subtracting adjacent signals, and details will be explained with reference to FIGS. 11 and 12.

The AI line is a = (Cy + M), b = (Ye + M
g), ... Pixel signals are output in the order of (11th
The signal on the A1 line is sampled by the sampling pulse 5HPl (shown in Figure E), and
A continuous signal S1 (Cy1G) is formed (shown in B of the same figure), and the signal of the AI line is sampled with a sampling pulse 5HP2 (shown in F of the same figure),
A continuous signal S2 of (Ye + Mg) is formed (as shown in the same figure C), and the signal S1 is subtracted from the signal S2 to obtain the red difference signal RY (as shown in the same figure).

In other words, it is approximated as shown in the following equation.

R-Y=l(Ye+Mg)-(Cy+G)1=(2R-
G) A2 line is a= (Cy+Mg), b= (Y
Pixel signals are output in the order of e (10G), ... (as shown in Figure 12A), and the signal of the A2 line is sampled with a sampling pulse of 5HPI (as shown in Figure 12E), resulting in a sequence of (Cy+Mg). A signal $1 is formed (shown in B in the same figure), and the signal on the A2 line is sampled by a sampling pulse 5HP2 (shown in F in the same figure), and a continuous signal S2 of (Ye + G) is formed. (shown in Figure C), and the signal S1 is changed from the signal S2.
is subtracted.

A blue color difference signal -(B-Y) is obtained (as shown in the figure),
In other words, it is approximated as shown in the following equation.

(B-Y)=((Ye+G)-(Cy+Mg)1=-(
2B-G) Regarding the other lines of the A field and the lines of the B field, the red difference signal R-Y and the blue difference signal -(B-Y) are obtained alternately line-sequentially in the same way.

Returning to FIG. 8, the imaging signal output from the CDS circuit 3 is supplied to the gamma correction circuit 6 via the AGC circuit 5.

The imaging signal output from the gamma correction circuit 6 is
The signal is supplied to a low-pass filter that constitutes a brightness processing section. This low-pass filter 7 averages adjacent signals as shown in equations (1) and (2). Therefore, this low-pass filter 7 outputs a luminance signal Y.

Further, the image signal outputted from the gamma correction circuit 6 is processed by sample and hold circuits 8 and 9 that constitute the chroma processing section.
supplied to Sample and hold circuits 8 and 9 include
Each sampling pulse S from the timing generator 4
HP 1 and 5HP2 (E in Figures 11 and 12)
, F) is supplied.

The sample and hold circuit 8 outputs a continuous signal s1 of (Cy+G) or (Cy + Mg) and is supplied to the subtracter 10 (shown in FIG. 11B and FIG. 12B), a sample and hold circuit 9. From (Ye ten Mg)
A continuous signal S2 of (Ye + G) is output and supplied to the subtracter 10 (as shown in FIG. 11C and FIG. 12C).

The subtracter 10 subtracts 81 from the signal S2.

Therefore, from this subtracter 10, equation (3),
Red difference signal RY, blue difference signal - (B
-Y) are output alternately line-sequentially (as shown in the 11th and 12th diagrams).

Also, although not shown, a luminance signal Y and a color difference signal R-Y/
-(B-Y) is fed to the encoder, e.g. NTSC
A video signal SV of the system is formed.

By the way, in the example shown in FIG.
(see figure).

FIG. 14 shows an example in which a circuit for synchronizing the color difference signals outputted line-sequentially in this manner is added.

In the figure, the output signal of the subtracter 10 (shown in FIG. 15A) is directly supplied to the H side fixed terminal of the changeover switch 16 and the L side fixed terminal of the changeover switch 17. Further, the output signal of the subtracter 10 is supplied to a delay circuit 18 having a delay time of one horizontal period (IH).
The output signal (shown in FIG. B) is supplied to the L-side fixed terminal of the changeover switch 16 and the H-side fixed terminal of the changeover switch 17.

The changeover switches 16 and 17 are supplied with a changeover control signal SWI from the timing generator 4. This switching control signal S
WI is at a high level "H" during the horizontal period when the output signal of the subtracter 10 is the red difference signal R-Y, and is at a low level during the horizontal period when the output signal is the blue difference signal -(B-Y) (see FIG. (Illustrated in C).

The changeover switches 16 and 17 are connected to the H side when the changeover control signal SWI is at high level rH, and are connected to Lllll when it is at low level rl and J.

Therefore, the changeover switch 16 outputs the red difference signal R-Y in each horizontal period (as shown in the figure), and the changeover switch 17 outputs the blue difference signal -(B-Y) in each horizontal period (shown in the figure). (Illustrated in E), this provides synchronization.

[Problems to be Solved by the Invention] Here, as shown in FIG. 16A, a case will be considered in which the color of the captured image changes from red to blue with 21 points as the border in the vertical direction. Focusing on A field, 21 points are A3 line and A4
Assume that the position is 1 between the lines (as shown in Figure B)
.

In this case, the output signal of the subtracter 10 becomes as shown in FIG. B, the output signal of the delay circuit 18 becomes as shown in FIG.
In the diagram shown in H, the shaded area is a blue information signal, and the other areas are red information signals.

Here, when observing a horizontal period in which the output signal of the subtracter 10 is the A4 line, the output signal of the changeover switch 16 becomes a red difference signal RY related to red information, and the output signal of the changeover switch 17 becomes a red difference signal RY related to blue information. The blue difference signal related to −(, B
-Y”), resulting in color misalignment.

Conventionally, it has been proposed to suppress the color signal at the color edge portion to make the color shift less noticeable.

In this case, since the color signal is suppressed at the color edge part, the color tone disappears at the color edge part, and a detection circuit for the color edge part, a color signal suppression circuit, etc. are required.
The more complex the circuit configuration, the more expensive it becomes.

Therefore, the present invention basically has two objects: color edge portion C: to prevent color shift from occurring.

[Means for Solving the Problems] The present invention provides a method in which the first and ≦ signals, which become the first and second color difference signals when subtracted from each other, are sequentially output every pixel period. In the second frame, a single-chip σ color solid-state image sensor and a driver shift the position of the image captured by the solid-state image sensor by one pixel in the vertical direction to the first frame. , first and second frame memories that store the first and second frame imaging signals output from the solid-state image sensor t1, and from the first and second frame memories to the first frame memory. On the other hand, a readout control circuit shifts the readout timing of the second frame memory by one horizontal period and reads out the imaging signals of the first and second frames in parallel;
The first frame memory read from the first and second frame memories.
and processing the imaging signals of the second frame to obtain the first and second frames respectively.
and first and second signal processing circuits that line-sequentially obtain second color difference signals; The apparatus includes first and second switch circuits for selecting color difference signals.

[Operation] In the image sensor 2, imaging is performed with the image position shifted vertically by one line interval in the first and second frames.

The read timing from the first and second frame memories 14a and 14b is shifted by one horizontal period, and the first
The imaging signals of the second frame and the second frame are read out in parallel.

The first and second color difference signals are output line-sequentially from the first and second signal processing circuits, respectively.

The first and second color difference signals are synchronized and output from the first and second switch circuits 16 and 17, respectively.

Therefore, since synchronization is performed using the first and second color difference signals existing for each line, color shift in the vertical color edge portion is prevented and high resolution is achieved.

〔Example〕

Hereinafter, with reference to FIG. 1, six embodiments of the present invention will be described, each of which is an example in which a still image is captured.

In FIG. 1, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this example, the pixel shift driver 11 changes the optical path of the image light supplied to the image sensor 2 via the image sensor 1 or moves the position of the image sensor 2, and the image captured by the image sensor 2 is changed. The position is sequentially shifted from frame to frame. In other words, as shown in Figure 2, the second frame is 2m vertically relative to the first frame! Raw pitch P
It is made to shift by v (1 life).

The operation of the pixel shift driver 11 is controlled by a controller 12. This controller 12 is supplied with a horizontal synchronization signal HD and a vertical synchronization signal VD from the timing generator 4.

In addition, the imaging signal output from the gamma correction circuit n6 is A
After being converted into a digital signal by the /D converter 13, it is supplied to frame memories 14a and 14b. Writing and reading of these frame memories 14a and 14b are controlled by the controller 12.

That is, the image signals of the first and second frames, which are imaged with shifted image positions as described above, are sequentially written into the frame memories 14a and 14b, respectively.

Imaging signals are read out in parallel from these frame memories 14&, 14b. In this case, the readout timing of the image signals from each frame memory 14a, 14b is sequentially adjusted in accordance with the amount of shift in the position of the image captured by the image sensor 2. That is, based on the read timing of the frame memory 14b, the read timing of the frame memory 14a is one horizontal period (IH
) is delayed.

Note that the imaging signals of the same frame are repeatedly read out from the frame memories 14a and 14b, and become imaging signals for still images.

The imaging signal output from the frame memory 14a is D/
After being converted into an analog signal by A converter 15a, it is supplied to sample and hold circuits 8a and 9a. The sample and hold circuits 8a and 9a receive sampling pulses SHP 1 and 5 from the timing generator 4, respectively.
HP2 is supplied. And sample hold circuit 8
The output signals of a and 9a are each supplied to a subtracter 10a. The configurations of the sample and hold circuits 8a and 9a and the subtracter 10a are similar to the configurations of the sample and hold circuit 8.9 and the subtracter 10 in the example of FIG. Blue difference signal - (B-Y
) are output alternately in a line-sequential manner (as shown in FIG. 4A).

Further, the image signal outputted from the frame memory 14b is converted into an analog signal by the D/A converter 15b, and then supplied to the sample and hold circuits 8b and 9b.

Sampling pulses 5HP1 and 5HP2 are supplied from the timing generator 4 to sample and hold circuits 8b and 9b, respectively. The output signals of sample and hold circuits 8b and 9b are each supplied to a subtracter 10b. The configurations of the sample and hold circuits 8b and 9b and the subtracter 10b are also similar to the configurations of the sample and hold circuit 8.9 and the subtracter 10 in the example of FIG. Blue difference signal - (B
-Y) are output alternately in line sequence (as shown in Figure 4B).
.

In this way, the red difference signal R-Y and the blue difference signal -(B-Y) are outputted line-sequentially and alternately from both the subtractors 10a and 10b, but the output signal of the subtractor 10a is
It is delayed by one horizontal period from the output signal of b.

Note that FIG. 3 shows the screen pattern of the image sensor 2 and the subtracter 1.
The relationship between the output signals of 0a and 10b is shown.

The output signal of the subtracter 10a is supplied to the H side fixed terminal of the changeover switch 16, and is also supplied to the L side of the changeover switch 17.
Supplied to the fixed terminal on the side. Further, the output signal of the subtracter 10b is supplied to the L side fixed terminal of the changeover switch 16, and is also supplied to the H side fixed terminal of the changeover switch 17.

A switching control signal SWI' is supplied from the timing generator 4 to the switching switches 16 and 17. This switching control signal SWI' indicates that the output signal of the subtracter 10a is the red difference signal R-
The horizontal period of Y is at high level "H", and the horizontal period of blue difference signal -(B-Y) is at low level rL
J (as shown in Figure 4C), selector switch 16.1
7 is connected to the H side when the switching control signal SWI' is at a high level (r) (J), and is connected to the L side when it is at a low level "L".

Therefore, the changeover switch 16 outputs the red difference signal R-Y in each horizontal period (as shown in the figure), and the changeover switch 17 outputs the blue difference signal -(B-Y) in each horizontal period (as shown in the figure). (Illustrated in Figure E).

Further, the image signal outputted from the frame memory 14b is supplied to a low-pass filter via a D/A converter 15b, and adjacent signals are averaged. Therefore, a luminance signal Y is obtained from this low-pass filter 7, similar to the example in FIG.

In this example, for each line, the subtracter 1
Either of the output signals 0a and 10b has a red signal R-Y,
A blue difference signal -(B-Y) is included (see FIG. 3), and a red difference signal R-Y and a blue difference signal -( B-Y) is selected and synchronization is performed. In other words, according to this example, synchronization is performed using the existing red difference signal R-Y and blue difference signal -(B-Y) for each line, so that the color at the vertical color edge portion is It is possible to prevent misalignment from occurring.

Here, as shown in FIG. 5A, consider a case where the color of the captured image changes from red to blue at 21 points in the vertical direction. Focusing on the A field, 21 points are A2 in the first frame.
Assume that it is located between the A3 line and the A3 line (see Figure 3).

In this case, the output signals of the subtracters 10a and 10b are as shown in FIG.
, C, and the output signals of the changeover switches 16 and 17 become as shown in H in the same figure.

In the figure, the shaded area is a blue information signal, and the other areas are red information signals.

As is clear from the figure, the red difference signal R-Y after synchronization
Comparing the blue color difference signal -(B-Y) and the blue color difference signal -(B-Y), it can be seen that each horizontal period has the same color information and no color shift occurs.

In addition, synchronization is performed using the red difference signal R-Y and blue difference signal (B-Y) that exist for each line, and the synchronization is performed by repeating the color difference signals of the same line twice each time. However, it is possible to achieve high resolution in the vertical direction.

Further, the color signal is not suppressed at the color edge portion, and there is no problem such as loss of color at the color edge portion or complicated circuit configuration.

Furthermore, since the synchronization is not performed by repeating the color difference signals of the same line twice, there is an advantage that the delay circuit of (1)H is not required.

In the above-mentioned embodiment, a still image is taken, but it is also possible to take a moving image. FIG. 6 shows an example of this, and parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In this example, the stored contents of the frame memories 14a and 14b are sequentially updated with new imaging signals.

That is, the frame memory 14a is transferred from the controller 12.
, 14b have write control signals WC1, wc, respectively.
2 (shown in FIGS. 7B and 7C). As a result, for the output signal of the A/D converter 13 as shown in FIG. 7A, odd frame signals are stored in the frame memory 14a. Even-numbered frame signals are alternately written and sent to the frame memory 14b (shown in E of the same figure). Note that the numbers 1, 2, 3, . . . in FIG. 7 are as follows:
Shows the frame number.

Then, the frame memories 14a and 14b output signals as shown in F and G in the figure. As a result, the changeover switches 16 and 17 output red difference signals R-Y and -(B-Y) based on the sequentially changed imaging signals, which can be used for moving images.

In this example, D/A converters 15a and 15b
The output signals of the changeover switch 19 are
and Llll. This changeover switch 19 is supplied with a changeover control signal SW2 from the timing generator 4. The switching control signal SW2 is a signal in which a low level "L" and a high level r ) ( ) are repeated every frame (as shown in H in the figure). H when
On the other hand, when it is at low level r l, J, it is connected to the L side.

The changeover switch 19 outputs an image signal updated every frame (as shown in FIG. 1), and this is supplied to the low-pass filter. As a result, the low-pass filter 7 outputs a luminance signal Y updated for each frame, which can be used for moving images.

In addition, in the above embodiment, the image sensor 2 has a complementary color checkered color filter, but it is not limited to this. In other words, when mutually subtracting, the first and second The first and second color difference signals are
The present invention can be similarly applied to any image sensor that sequentially outputs the signals in each screen period.

[Effects of the Invention] As explained above, according to the present invention, since synchronization is performed using the first and second color difference signals existing for each line, the color edge portion in the vertical direction is It is possible to prevent color misregistration and also to achieve high resolution in the vertical direction. Further, the color signal is not suppressed at the color edge portion, and there are no disadvantages such as loss of color at the color edge portion or complicated circuit configuration.

Furthermore, since the synchronization is not performed by repeating the color difference signals on the same line twice, there is an advantage that an IH delay circuit is not required.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of this invention, FIGS. 2 to 5 are diagrams for explaining the same, FIG. 6 is a block diagram showing another embodiment of this invention, and FIG. Diagram for its explanation, No. 8
The figure is a configuration diagram of a conventional example, Figures 9 to 13 are diagrams for explaining the same, Figure 14 is a configuration diagram of the conventional example with a synchronization circuit added, and Figures 15 and 16 are diagrams for explaining the same. This is a diagram for 1...Imaging lens 2...CCD color solid-state image sensor 7...Low pass filter a 0a 4a 16°8b 9a, 9b 0. Sample hold circuit 10b...Subtractor 11...Pixel shift driver 12...Controller 14b...Frame memory 17.19 Changeover switch

Claims (1)

[Claims] (1) When subtracted from each other, the first and second
A single-chip color solid-state image pickup device sequentially outputs first and second signals serving as color difference signals for each pixel period, and the position of the image captured by the solid-state image pickup device is a pixel shift driver that shifts the frame by one line interval in the vertical direction; first and second frame memories that respectively store the first and second frame imaging signals output from the solid-state imaging device; The first and second frame memories read out the imaging signals of the first and second frames in parallel by shifting the read timing of the second frame memory by one horizontal period with respect to the first frame memory. a readout control circuit for reading and processing the first and second frame imaging signals read from the first and second frame memories to obtain the first and second color difference signals in a line-sequential manner, respectively; and a second signal processing circuit, and first and second switches for selecting the first and second color difference signals, respectively, from the output signals of the first and second signal processing circuits at a cycle of one horizontal period. A color solid-state imaging device equipped with a circuit.