JPH04154283A - Solid image pickup apparatus - Google Patents

Abstract

PURPOSE:To miniaturize a solid image pickup apparatus with the means of refining of picture element cells by installing a noise removal means in each vertical line for removing a noise contained in the amplification output of each photo-receptor. CONSTITUTION:Output from noise removal purpose capacitor C0, after passing buffer amplifier 13, is supplied a changeover switch 14 alternatively to sample/ hold purpose capacitors C1 and C2 that are the first and second signal holding means, and treated for sample/hold by capacitors C1 and C2. Changeover control of changeover switch 14 is executed by sample/hold pulse phiSH generated during a blanking period of time for each lines In this case, picture element outputs on even lines are held in capacitor C1, while picture element outputs on odd lines in capacitor C2, respectively. As a result, micro-miniaturization of picture element cell can downsize the apparatus.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device, and particularly to an amplification-type solid-state imaging device having an amplifying element in each light-receiving section.

<Summary of the Invention> The present invention provides an amplification type solid-state imaging device having an amplifying element in each light receiving section, in which a gate electrode and a drain electrode of a reset MOS transistor for resetting the gate input of an amplifying MOS transistor of each light receiving section are provided. In addition to selecting a horizontal line by applying a voltage, a noise removal means is provided for each vertical line for the amplified output of each light receiving section to reduce noise, thereby achieving high sensitivity due to low noise and fineness of pixel cells. This makes it possible to downsize the device.

<Prior art> A basic CCD type solid-state imaging device has a structure in which a signal accumulated in each pixel (photoelectric conversion unit) according to the amount of incident light is transferred to an output unit as a charge using a CCD. Therefore, there was a problem in that the S/N ratio was likely to be 9 due to noise components being mixed into the charge transfer by the CCD.

To solve this problem, the solid-state imaging substrate 1 conventionally includes a photoelectric conversion section that multiplies signal charges according to the amount of incident light, a means for amplifying the signal charges accumulated in this photoelectric conversion section, and a means for amplifying the signal charges accumulated in this photoelectric conversion section. An amplification type solid-state imaging device is known in which a light receiving section having a means for resetting the λ power of the amplification means is provided for each pixel of a plurality of pixels arranged in a 2-bit pattern (
For example, see Japanese Patent Application Laid-Open No. 1-154678).

<Problems to be Solved by the Invention> However, in amplified solid-state imaging devices, although it is possible to reduce fixed pattern noise including quinine defects by improving manufacturing process technology, reset due to device characteristics etc. Since noise is a logical phenomenon, when pixel cells are made smaller in order to make solid-state imaging devices smaller,
There was a problem that the S/N ratio deteriorated.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solid-state imaging device that has high sensitivity due to low noise and can be downsized due to miniaturization of pixel cells.

Means for Solving the Problems> A solid-state imaging device according to the present invention includes a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions.
A photoelectric conversion section that accumulates signal charges according to the amount of incident light, a current collection section that stores the signal charges transferred from this photoelectric conversion section, and an amplification MO that amplifies and outputs the signal charges of this current collection section.
S) A light receiving section having a transistor and a reset MOS transistor for resetting the gate potential of the amplification MOS transistor to a predetermined potential is provided, and the reset MOS
Pixels are selected in the vertical direction by applying voltage to the gate electrode and drain electrode of the transistor, and a noise removal circuit is provided for each vertical line to remove noise contained in the amplified output of the amplification MOS transistor. There is.

<Function> In the solid-state imaging device according to the present invention, the amplification MO of each light receiving section
A horizontal line is selected by applying a voltage to the gate electrode and drain electrode of a reset MOS transistor that resets the gate input of the S transistor. Then, the noise included in the amplified output of each light receiving section is removed by the noise removing means provided for each vertical line.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing only essential parts of an embodiment of a solid-state imaging device according to the present invention. In this figure, for convenience of explanation,
Of the multiple pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions, the circuit configuration of only one pixel in each of the two adjacent lines, nth and n+1st, is shown, but the remaining pixels all have the same circuit configuration. It is assumed that

In the figure, when light enters each pixel, signal charges corresponding to the amount of incident light are stored in a storage (ST) 1.

This storage l and its output gate (OG) switch 2 provide a 1-bit ccD (Charge Coup
LED Device) is configured.

Also, on the same chip as this 〇CD, there is a reset MO3-
FET3 and amplification MO3FET4 of 7-Sho0'7 are made, and the amplification MO3-FET17) gate is a floating diffusion (Fl).

floating diffusion amplifier (FDA) 5.

In this floating diffusion amplifier 5, the gate electrode of the output gate switch 2 is connected to the output gate (OG) signal line 6, and the reset MOS-F
The gate electrode of ET3 is the reset gate (RG) signal line 7
A, reset electrodes are connected to reset drain (RD) signal lines 7b, respectively. Then, an output gate pulse φ is output from the vertical scanning shift register 8 to the gate electrode of the output gate switch 2. , but also MO3 for resetting
- Reset gate pulse φ8 to the gate electrode of FET3.
However, a horizontal line is selected by applying a reset drain pulse φ1 to each drain electrode. In addition, the power supply voltage ■ is applied to the drain electrode of MO3-FET4 for amplification. is applied, and its source electrode is the output terminal ■. It is connected to the vertical signal line 9 as ut.

Then, when one horizontal line is selected, the signal charge of the pixel of the selected horizontal line is transferred to the MO3-FET for amplification.
4 and output to the vertical signal line 9.

A load transistor 11 is connected to the vertical signal line 9 via a transfer gate switch 10, and the amplified output of each pixel output to the vertical signal line 9 is connected to a noise removal capacitor C.
Stored at 0. A clamp switch 12 is connected to the output end of this capacitor C0, and the clamp switch 12 is turned on by applying a clamp pulse φC to its gate electrode, so that the potential at the output end of the capacitor C0 is clamped to the clamp level Vctp.The noise removal capacitor C0 and the clamp switch 12 are used to reduce noise such as reset noise included in the source output of the MO3-FET4 for amplification. A sampling) circuit 15 is configured.

The output of the noise removal capacitor C0Φ passes through the amplifier 13 and then is switched to the first.
The signal is selectively supplied to sample/hold capacitors C1, Cz, which are second signal holding means, and sampled/held by these capacitors c, , C,. Switching control of the changeover switch 14 is performed for each line by a sample/hold pulse φ311 generated during the horizontal blanking period. As a result, for example, the pixel outputs of the even lines are held in the capacitor C1, and the pixel outputs of the odd lines are held in the capacitor C2.

The hold outputs of the capacitors C, ,C, pass through the buffer amplifiers 16-+ and 16-z, and then are connected to the horizontal gate switch 17.
-, , 17-z leads to the horizontal signal line 1 B-0, 18-z. Switching control of the horizontal gate switch 16-616-t is performed using a horizontal shift pulse φ output from the horizontal scanning shift register 19.
It is done by □.

FIG. 2 shows a cross-sectional structure of a solid-state imaging device according to the present invention having such a configuration. In addition, FIG. 2 shows the drain electrode (VDD)-gate electrode-source electrode (■.++1) of 5T-OG-RG-RD...FET4 in one unit cell.
FIG. As is clear from the figure, the solid-state imaging device according to the present invention has a group of electrode elements constituting a floating diffusion amplifier (FDA) disposed on the surface of a thin silicon substrate 20, and a CV D
(Chemical Vapor Depositio
While depositing the Sing film 21 by a method such as n),
As shown in FIG. 4, a reset drain (RD) and an amplification MOS-FET 4 are connected to the horizontal aluminum wire 23 and vertical aluminum wire 24, which are patterned in an XY matrix pattern on the Si wire 11122 arranged on the back surface of the silicon substrate 20. It has a so-called back-illuminated structure in which the output ends (V.ut) of the two are connected to each other, and irradiation light is taken in from the back side of the silicon substrate 20.

In this way, by making the structure of the solid-state imaging device a back-illuminated type, only the horizontal aluminum wire 23 and the vertical aluminum wire 24 are patterned on the back side of the silicon substrate 20, so the aperture ratio can be dramatically increased. This means that you can improve your performance.

Next, in the solid-state imaging device according to the present invention, for each pixel selected by the vertical scanning shift register 8 and the horizontal scanning shift register 19, the following will be described with reference to the cell cross-sectional diagram in FIG. 2 and the potential distribution diagram in FIG. 3. The operation will be explained according to the time chart shown in FIG.

First, during the horizontal blanking period, as shown in FIG. 3, only the RD (reset drain) of the n-th horizontal line selected in the vertical direction is set to a high level (for example,
5V) reset voltage■. Line selection is performed by applying a low level voltage (for example, 1.5V) to the RDs of the remaining horizontal lines. At this time, the gate pulse φ resets the FD of the pixels of the selected horizontal line.
If you reset it with IG, the FD potential becomes high level,
As a result, the gate potential of MO3-FET4 for amplification also becomes high level. On the other hand, in the pixels of the horizontal line that are not selected, by holding the FD potential at a low level, the amplification MOS-FET 4 has its gate potential set to the third level.
As shown by the dotted line in the figure, the level becomes lower than the threshold level (for example, 0.5 V) from about FDt, resulting in a cut-off state.

Next, time point 1. When the reset gate pulse φIIG changes to low level, the reset MO3-FET
3 is the cutoff state. In this state, the clamp switch 12 is turned on by the clamp pulse φ, and the output terminal of the capacitor C0 is set to the clamp level ■. It is fixed at 2. Then, at time t3, the clamp pulse φ disappears, and the clamp switch 12 is turned off.

The effects of the capacitor C0 and the clamp switch 12 in the CDS circuit 15 cause fixed pattern noise (FPN) including scratches, unevenness caused by source follower input offset variations, and source follower low frequency (1/f
) Noise, reset noise generated when resetting the FDA, and smear caused by light entering the signal line or COD can be canceled. This eliminates the need for a frame memory for FPN removal conventionally used in a signal processing system for output signals of a solid-state imaging device.

Then, the output gate pulse φ. By turning on (QC;) 2, the signal charge stored in the storage (ST) 1 is transferred to the FD and the output gate pulse φ is generated. All signal charges are transferred to the FD until time t5 when G disappears. After that, sample/hold pulse φ! +1, the changeover switch 14 is switched to the sample/hold capacitor CI side at time t6, the signal voltage is input to the capacitor C1, and the changeover switch 14 is turned off at time t when the sample/hold pulse φ□ disappears (Fig. The signal voltage of the capacitor CI is held as the neutral position of the capacitor CI.

After the signal charge of the n-th horizontal line is amplified by the amplification MO3-FET4 and stored in the capacitor C1 of the CDS circuit 15 according to the operation timing described above, the signal charge of the n+1-th horizontal line is subsequently amplified by the same operation timing. It is amplified by MO3FET4 for amplification and stored in capacitor C1 of CDS circuit 15. As a result, the signals of two vertically adjacent pixels can be independently read out during the valid horizontal scanning period by controlling the switching of the horizontal gate switches 17-+ and 17-2 using the horizontal shift pulse φ8 issued from the horizontal scanning shift register 19. It will be possible. In addition, during the horizontal scanning valid period, reset noise) (R
G) to high level and reset drain (RD) to low level (approximately 1.5V).

During this readout, by sequentially reading out the hold outputs of the capacitors C, , C, a non-interlaced television signal can be obtained. Further, each hold output of the capacitors C+ and Cz may be read out at the same time. In this case, by appropriately processing the read signals with a signal processing system (not shown),
As in the case of sequential readout, a non-interlaced television signal can be obtained.

When the storage (ST) 1 overflows with signal charges, the signal charges are discarded from ST→O(1,-4FD→RD) due to horizontal overflow.In this way, the reset MO3-FE73 Drain electrode (RD)
By using this for horizontal line selection and also sharing it for the overflow train, the configuration of the horizontal line selection element and the overflow train can be simplified.

<Effects of the Invention> As explained above, according to the present invention, the horizontal line can be adjusted by applying a voltage to the gate electrode and the drain electrode of the reset MOS transistor that connects the gate input of the amplification MOS transistor of each light receiving section. In addition to making selections, the structure is configured to reduce noise by providing noise removal means for each vertical line for the amplified output of each light receiving section.
Lower noise allows for higher sensitivity and smaller pixel cells,
Furthermore, miniaturization of pixel cells has the effect of making the device more compact.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing only the essential parts of an embodiment of a solid-state imaging device according to the present invention, FIG. 2 is a cross-sectional structural diagram showing the structure of one unit cell, and FIG. 3 corresponds to FIG. 4 is a back view showing a part of the solid-state imaging device according to the present invention, and FIG. 5 is a time chart for explaining the circuit operation of FIG. 1. 1...Storage (ST). 2... Output gate (OG) 3... MO3-FET for reset 4... MO3-FET for amplification 5... FDA (floating diffusion)
Amplifier). 12...Clamp switch. 15...CDS (correlated double sample and hold) circuit. C,,C,...Sample/hold capacitor. Patent applicant Sony Corporation agent
Patent Attorney Kuninori Funabashi Figure 1 I Uni 7Fτ Tsum's tLB Figure 2 Both: 15F Tsum i Pregnancy H No. 31!1

Claims (1)

[Claims] For each pixel of a plurality of pixels arranged two-dimensionally in a matrix in the horizontal and vertical directions, a photoelectric conversion unit accumulates signal charges according to the amount of incident light, and a signal charge is transferred from the photoelectric conversion unit. a current collector that stores signal charges, and an amplification MO that amplifies and outputs the signal charges of this current collector.
A light receiving section having an S transistor and a reset MOS transistor that resets the gate potential of the amplification MOS transistor to a predetermined potential is provided, and a pixel in the vertical direction is set by applying a voltage to the gate electrode and drain electrode of the reset MOS transistor. What is claimed is: 1. A solid-state imaging device comprising: a noise removal circuit for removing noise contained in the amplified output of the amplification MOS transistor; and provided for each vertical line.