JPH04154190A - Mounting of chip component - Google Patents
Mounting of chip componentInfo
- Publication number
- JPH04154190A JPH04154190A JP27984290A JP27984290A JPH04154190A JP H04154190 A JPH04154190 A JP H04154190A JP 27984290 A JP27984290 A JP 27984290A JP 27984290 A JP27984290 A JP 27984290A JP H04154190 A JPH04154190 A JP H04154190A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chip component
- board
- resin
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 18
- 239000011347 resin Substances 0.000 abstract description 29
- 229920005989 resin Polymers 0.000 abstract description 29
- 230000000717 retained effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 18
- 238000010438 heat treatment Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ハイブリッド集積回路における実装方法、特にリード端
子の無いチップ部品を基板表面に実装する方法に関し、
塗布された導電性樹脂の所定領域外への流出を最小限に
抑制できるチップ部品の実装方法の提供を目的とし、
基板の表面にチップ部品を実装するに際して金属板から
なり貫通孔を具えたバッファチップを、基板上に形成さ
れた導体パターンとチップ部品の端子部との間に介在せ
しめるように構成する。[Detailed Description of the Invention] [Summary] Regarding the mounting method of a hybrid integrated circuit, especially the method of mounting chip components without lead terminals on the surface of a substrate, the leakage of the applied conductive resin to the outside of the predetermined area is minimized. With the aim of providing a method for mounting chip components that can reduce the amount of damage caused by the chip components, the present invention aims to provide a method for mounting chip components on the surface of a substrate. The structure is such that it is interposed between the
本発明はハイブリッド集積回路における実装方法に係り
、特にリード端子の無いチップ部品を基板表面に実装す
る方法に関する。The present invention relates to a method for mounting a hybrid integrated circuit, and more particularly to a method for mounting chip components without lead terminals on the surface of a substrate.
近年、電子機器の小型化、高密度実装化か進展するに伴
って、リード端子の無いディスクリート部品（チップ部
品と称する）を、基板表面に実装する技術（ｓｕｒｆａ
ｃｅ ｍｏｕｎｔｉｎｇ ｔｅｃｈｎｏｌｏｇｙ）が広
く取り入れられている。かかる表面実装技術では通常低
温はんだとフラックスからなるペーストを、チップ部品
と基板の間に介在せしめて加熱炉の中を通し、融けたは
んだによってチップ部品を基板にはんだ付けする。In recent years, as electronic devices have become smaller and have become more densely packaged, technology for mounting discrete components without lead terminals (referred to as chip components) on the surface of a substrate (surfa) has been developed.
ce mounting technology) has been widely adopted. In such surface mounting technology, a paste consisting of low-temperature solder and flux is usually interposed between the chip component and the board, passed through a heating furnace, and the chip component is soldered to the board with the molten solder.
表面実装技術の対象は当初トランジスタや抵抗、コンデ
ンサなどであったが、その範囲は更に拡大され今ではハ
イブリッド集積回路等もその対象になってきている。し
かし通常のハイブリッド集積回路はチップ部品の実装に
上記方法か用いられており、基板に実装するため再び加
熱炉の中を通すとはんだか融けてチップ部品か移動する
。Initially, the targets of surface mount technology were transistors, resistors, capacitors, etc., but its scope has further expanded to include hybrid integrated circuits, etc. However, in conventional hybrid integrated circuits, the above-mentioned method is used to mount chip components, and when the circuit is passed through a heating furnace again to be mounted on a substrate, the solder melts and the chip components move.
そこで基板に実装するため再び加熱炉の中を通してもチ
ップ部品か移動することのない、表面実装用のハイブリ
ッド集積回路に適した実装方法の開発か望まれている。Therefore, it is desired to develop a mounting method suitable for surface-mounted hybrid integrated circuits that does not cause chip components to move even when they are passed through the heating furnace again to be mounted on a board.
Ｃ従来の技術〕
第２図は従来のチップ部品の実装方法を示す断面斜視図
である。C. Prior Art FIG. 2 is a cross-sectional perspective view showing a conventional method for mounting chip components.
表面実装に適したハイブリッド集積回路を形成する手段
として、従来は図示の如く基板ｌにチップ部品２を実装
するに際して、基板１の表面に形成された導体パターン
３に導電性樹脂４を塗布し、チップ部品２の端子部５か
導体パターン３に重なるようにチップ部品２を基板１に
押し付け、加熱炉の中を通す等の方法によって導電性樹
脂４を硬化させている。Conventionally, as a means of forming a hybrid integrated circuit suitable for surface mounting, when mounting a chip component 2 on a substrate 1 as shown in the figure, a conductive resin 4 is applied to a conductive pattern 3 formed on the surface of the substrate 1. The chip component 2 is pressed against the substrate 1 so that the terminal portion 5 of the chip component 2 overlaps the conductor pattern 3, and the conductive resin 4 is hardened by passing it through a heating furnace or the like.
このようにして導電性樹脂４を硬化させたハイブリッド
集積回路は、加熱されても軟化点以下であれば導電性樹
脂４か軟化することなく、例えばハイブリッド集積回路
を通常の方法で表面実装するため加熱炉の中を通しても
、導体パターン３と端子部５の間の接続か阻害されるこ
とはない。The hybrid integrated circuit in which the conductive resin 4 is cured in this manner does not soften even when heated as long as the conductive resin 4 is below the softening point.For example, the hybrid integrated circuit can be surface-mounted by a normal method. The connection between the conductor pattern 3 and the terminal portion 5 is not disturbed even when the wire is passed through the heating furnace.
しかし従来の実装方法では基板とチップ部品の隙間か小
さく、基板の表面に形成された導体パターンに導電性樹
脂を塗布し、チップ部品の端子部が導体パターンに重な
るようにチップ部品を基板に押し付けたときに、導電性
樹脂が基板とチップ部品の隙間を伝わって不要な部分に
流れ出し、目的とする端子部と導体パターンの接続不良
か発生したり、或いは隣接する導体パターンとの間を短
絡させるという問題かあった。However, in the conventional mounting method, the gap between the board and the chip component is small, so conductive resin is applied to the conductive pattern formed on the surface of the board, and the chip component is pressed onto the board so that the terminal part of the chip component overlaps the conductive pattern. When the conductive resin passes through the gap between the board and the chip component and flows out into unnecessary areas, it may cause a poor connection between the intended terminal and the conductor pattern, or it may cause a short circuit between adjacent conductor patterns. There was a problem.
本発明の目的は塗布された導電性樹脂の所定領域外への
流出を、最小限に抑制できるチップ部品の実装方法を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for mounting chip components that can minimize the flow of the applied conductive resin out of a predetermined area.
第１図は本発明になるチップ部品の実装方法を示す断面
斜視図である。なお全図を通し同じ対象物は同一記号で
表している。FIG. 1 is a cross-sectional perspective view showing a method for mounting chip components according to the present invention. The same objects are represented by the same symbols throughout the figures.
上記課題は基板ｌの表面にチップ部品２を実装するに際
して、金属板からなり貫通孔７を具えたバッファチップ
６を、基板１上に形成された導体パターン３とチップ部
品２の端子部５との間に、介在せしめる本発明のチップ
部品の実装方法によって達成される。The above problem is that when mounting the chip component 2 on the surface of the substrate l, the buffer chip 6 made of a metal plate and provided with the through hole 7 is connected to the conductor pattern 3 formed on the substrate 1 and the terminal portion 5 of the chip component 2. This is achieved by the chip component mounting method of the present invention which is interposed between the steps.
第１図において金属板からなり貫通孔を具えたバッファ
チップを、基板上の導体パターンとチップ部品の端子部
との間に介在せしめることによって、導電性樹脂を塗布
したあとチップ部品を基板に押し付けたときに、導電性
樹脂か伝わらない程度に大きい隙間が基板とチップ部品
の間に形成され、しかも余分な導電性樹脂はバッファチ
ップの貫通孔と外部側面上に留保される。In Figure 1, a buffer chip made of a metal plate and provided with a through hole is interposed between the conductive pattern on the board and the terminal part of the chip component, and the chip component is pressed against the board after applying conductive resin. At this time, a gap large enough to prevent the conductive resin from being transmitted is formed between the substrate and the chip component, and excess conductive resin is retained in the through-holes and external side surfaces of the buffer chip.
即ち基板上に塗布された導電性樹脂の所定領域外への流
出を、最小限に抑制できるチップ部品の実装方法を実現
することができる。That is, it is possible to realize a chip component mounting method that can minimize the leakage of the conductive resin coated on the substrate to the outside of the predetermined area.
以下添付図により本発明の実施例について詳細に説明す
る。Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
表面実装に適したハイブリッド集積回路を形成する手段
として、本発明の実施例では第１図に示す如く基板１に
チップ部品２を実装するに際して、基板１の表面に形成
された導体パターン３に導電性樹脂４を塗布し、バッフ
ァチップ６を介してチップ部品２の端子部５か導体パタ
ーン３に重なるように、チップ部品２を基板１に押し付
は導電性樹脂４を硬化させている。なおバッファチップ
６は例えば銅板等導電性に優れた金属板で形成され、そ
の中央部に少なくとも１個の貫通孔７か設けられている
。As a means of forming a hybrid integrated circuit suitable for surface mounting, in the embodiment of the present invention, when mounting a chip component 2 on a substrate 1 as shown in FIG. The conductive resin 4 is applied and the chip component 2 is pressed against the substrate 1 so as to overlap the terminal portion 5 of the chip component 2 or the conductive pattern 3 via the buffer chip 6, and the conductive resin 4 is cured. The buffer chip 6 is made of a metal plate with excellent conductivity, such as a copper plate, and has at least one through hole 7 provided in its center.
このようにして導電性樹脂４を硬化させたノ１イブリッ
ド集積回路は、加熱されても軟化点以下であれば導電性
樹脂４か軟化することなく、例えばハイブリッド集積回
路を通常の方法で表面実装するため加熱炉の中を通して
も、導体パターン３と端子部５の間の接続が阻害される
ことはない。The hybrid integrated circuit in which the conductive resin 4 is cured in this way does not soften even when heated, as long as the conductive resin 4 is below its softening point. Therefore, the connection between the conductor pattern 3 and the terminal portion 5 is not hindered even if the wire is passed through the heating furnace.
また導電性樹脂を塗布したあとチップ部品を基板に押し
付けたときに、導電性樹脂が伝わらない程度に大きい隙
間か基板とチップ部品の間に形成され、しかも余分な導
電性樹脂はバッファチップの貫通孔と外部側面上に留保
される。即ち基板上に塗布された導電性樹脂の所定領域
外への流出を、最小限に抑制できるチップ部品の実装方
法を実現することができる。Furthermore, when a chip component is pressed onto a board after applying conductive resin, a gap is formed between the board and the chip component that is large enough to prevent the conductive resin from passing through, and the excess conductive resin penetrates the buffer chip. Retained on the pores and external sides. That is, it is possible to realize a chip component mounting method that can minimize the leakage of the conductive resin coated on the substrate to the outside of the predetermined area.
上述の如く本発明によれば塗布された導電性樹脂の所定
領域外への流出を、最小限に抑制できるチップ部品の実
装方法を提供することができる。As described above, according to the present invention, it is possible to provide a chip component mounting method that can minimize the flow of the applied conductive resin out of a predetermined area.
第１図は本発明になるチップ部品の実装方法を示す断面
斜視図、
第２図は従来のチップ部品の実装方法を示す断面斜視図
、
である。図において
１は基板、 ２はチップ部品、３は導体パタ
ーン、 ４は導電性樹脂、５は端子部、 ６は
バッファチップ、７は貫通孔、
をそれぞれ表す。FIG. 1 is a cross-sectional perspective view showing a chip component mounting method according to the present invention, and FIG. 2 is a cross-sectional perspective view showing a conventional chip component mounting method. In the figure, 1 is a substrate, 2 is a chip component, 3 is a conductor pattern, 4 is a conductive resin, 5 is a terminal portion, 6 is a buffer chip, and 7 is a through hole.
Claims (1)
して、金属板からなり貫通孔（７）を具えたバッファチ
ップ（６）を、該基板（１）上に形成された導体パター
ン（３）と該チップ部品（２）の端子部（５）との間に
、介在せしめることを特徴とするチップ部品の実装方法
。When mounting a chip component (2) on the surface of a substrate (1), a buffer chip (6) made of a metal plate and provided with a through hole (7) is mounted on a conductor pattern (3) formed on the substrate (1). ) and a terminal portion (5) of the chip component (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27984290A JPH04154190A (en) | 1990-10-18 | 1990-10-18 | Mounting of chip component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27984290A JPH04154190A (en) | 1990-10-18 | 1990-10-18 | Mounting of chip component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04154190A true JPH04154190A (en) | 1992-05-27 |
Family
ID=17616693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27984290A Pending JPH04154190A (en) | 1990-10-18 | 1990-10-18 | Mounting of chip component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04154190A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281703A (en) * | 2010-06-09 | 2011-12-14 | 富士通株式会社 | Laminated circuit board and board producing method |
| CN112437555A (en) * | 2020-11-25 | 2021-03-02 | 江苏汇成光电有限公司 | Mechanism capable of reducing jitter in Tape Bonding technological process |
-
1990
- 1990-10-18 JP JP27984290A patent/JPH04154190A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281703A (en) * | 2010-06-09 | 2011-12-14 | 富士通株式会社 | Laminated circuit board and board producing method |
| US8586876B2 (en) | 2010-06-09 | 2013-11-19 | Fujitsu Limited | Laminated circuit board and board producing method |
| CN112437555A (en) * | 2020-11-25 | 2021-03-02 | 江苏汇成光电有限公司 | Mechanism capable of reducing jitter in Tape Bonding technological process |
| CN112437555B (en) * | 2020-11-25 | 2021-11-09 | 江苏汇成光电有限公司 | Mechanism capable of reducing jitter in Tape Bonding technological process |
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