JPH04152714A - Cmos gate array - Google Patents

Abstract

PURPOSE:To accurately measure an output leakage current by adding a pull-up resistor, a pull-down resistance element controlling logic element and a test control terminal to each of buffer circuit sections of a bidirectional buffer circuit with the pull-up resistor and the pull-down resistor. CONSTITUTION:When a signal fed to a test terminal 21 is fixed to an H level in the practical operation, a current between a power supply 5 and ground is eliminated when a signal is outputted from an output buffer 10. When a signal fed to the test terminal 21 is fixed to an L level at the shipping test, a PMOS 6 keeps the off-state. Thus, no current flows from the power supply 5 to ground via the PMOS 6. Thus, a power supply leakage current test in the nonoperating state is conducted independently of the output state of the bidirectional buffer circuit with the pull-up resistor 3 and of the input state of an external H/L signal. Moreover, the output leakage current test in the output high impedance state of the output buffer 10 is conducted accurately.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a CMOS gate array with a built-in bidirectional buffer circuit with pull-up and pull-down resistors that enables accurate leakage current measurement or static special power supply leakage current measurement. It is something.

[Prior Art] Fig. 3 is a circuit diagram of a conventional bidirectional buffer circuit with a pull-up resistor, and Fig. 4 is a circuit diagram of a conventional bidirectional buffer circuit with a pull-down resistor. External signal terminal electrodes (hereinafter referred to as pads), (31 is a bidirectional buffer circuit with pull-up resistor, (4) is a bidirectional buffer circuit with pull-down resistor, (5) is a power supply, (6 is
) is a P-channel field-effect transistor (hereinafter referred to as PvO6) for the pull-up resistor, (7) is grounded, and (8) is an N-channel type MO8 field-effect transistor (hereinafter referred to as NMO8) for the pull-down resistor. 9
) (11) is a non-inverting buffer for input (hereinafter referred to as input buffer), (10) (12) is a 3-nutate output buffer for 6 outputs (hereinafter referred to as output buffer), (13)
) (16) connects the input buffer 6 data signal terminal to the pole (
(14) and (17) are output buffer 7 input data signal terminal electrodes (hereinafter referred to as input data terminals), (15) and (18) are output buffer 3 nutate control input signals. Terminal electric Fli (hereinafter referred to as control terminal)
It is.

Next, the operation will be explained. In Figure 3, control a11
When a ground level signal (referred to as a signal below c) is applied from the i11 terminal (15), the bidirectional buffer circuit with pull-up resistor (3) changes the output state and outputs the input data terminal (1
A power level signal (hereinafter referred to as R signal) or L signal applied from 4) is propagated to the pad (1) via the output buffer (10), and further via the input buffer (9) to the output data terminal. (13) When the H signal is applied from the control terminal (15), the output buffer (10) is in the output high impedance state, and the bidirectional buffer circuit with pull-up resistor ( 3) is in the input state, and the external H signal or L signal applied from pad (1)
The signal is passed through the input buffer (9) to the output data terminal (
13).

On the other hand, if no external input signal is applied from pad (1) at this time, the input/<
The input signal of the sofa (9) becomes H, and the input buffer (9)
) to the output data terminal (13).

Next, in FIG. 4, when the L signal is applied from the control terminal (18), the bidirectional Bazza circuit with pull-down (
4) is in a six-power state, and the H signal or L signal applied from the input data terminal (17) is sent to the output buffer (12).
is propagated to the pad (2) via the input buffer (11), and further propagated to the output data terminal (16) via the input buffer (11). Next, when an H signal is applied from the control terminal (18), the output buffer (12) becomes an output high impedance state, and the bidirectional buffer circuit section with pull-down resistor (4)
is in the input state, and the external B applied from pad (2)
The signal or L@ signal is propagated through the input buffer (11) to the output data terminal (16). On the other hand, if no external input signal is applied from the pad (2) at this time, the input buffer (1
The input signal of 1) becomes L, and the L signal is propagated to the output data terminal (13) via the input buffer C11).

[Problem to be solved by the invention j Since the conventional bidirectional buffer circuit with a pull-up resistor and the bidirectional buffer circuit with a pull-down resistor are configured as described above, PuO2 and NMO6 are always on, and therefore In the case of a bidirectional buffer circuit with a pull-up resistor: When the output buffer is in the L signal output state, current flows from the power supply to the ground via PuO2 and the output buffer, and the output buffer is in a high impedance state and the external input signal is L. When , current flows from the power supply through PuO2 to the ground of the external input signal driving element, and in the case of a bidirectional buffer circuit with a pull-down resistor, the output buffer becomes high.
In signal output state, output buffer and 11MO from power supply
When the output/< sofa is in a high impedance state and the external input signal is H, a current flows to the ground via NMO3 from the power supply of the external input signal drive element to the ground -N
This causes an increase in current consumption during actual use, as well as accurate static special power leak current testing for all test patterns for functional verification at the time of shipment, and accurate testing for both external input signals B and L in the output high-impedance DK. 8. There was a problem that leakage current measurement was not possible. This invention was made to solve the above problems. The C2200 has a built-in bidirectional buffer circuit with a pull-up resistor and a bidirectional buffer circuit with a pull-down resistor that enable accurate static II source leak current testing and output leak current testing regardless of the external input signal level or H.
The purpose is to obtain a MOS gate array.

Means for Solving Problems) The 7' bidirectional buffer circuit with pull-down resistor (sofa circuit and bi-directional buffer circuit with pull-down resistor according to the present invention) includes a pull-up resistor and a pull-down resistor for controlling the collection of pull-up resistors in each buffer circuit section. It has additional logic elements and test control terminals.

[Function] The ring element for controlling pull-up resistance and pull-down resistance and the control signal terminal in the present invention can control ON/OFF of the pull-up resistance and pull-down resistance element.

[Embodiment j] Hereinafter, an embodiment of the present invention will be explained with reference to the drawings.
FIG. 2 is a circuit diagram of a bidirectional buffer circuit with a pull-up resistor, which is an embodiment of the invention, and FIG. 2 is a circuit diagram of a bidirectional puff circuit with a pull-down resistor, which is another embodiment of the invention. In the figure, (ll+21 is a pad, (31Fi
Bidirectional/<tsu77 circuit section with pull-up resistor, (4) is bidirectional buffer circuit section with pull-down resistor, (5) #'i power supply, (6) is PMOS, (71 is ground).

(8) is N v OS, (9) (11) is input buffer 77, (10) (12) is output buffer, (13) (
16) is the output data terminal, (141 (17) is the input data terminal, r15) (18) is the control terminal, (21)
(22) is a test control terminal (hereinafter referred to as the test terminal)
, (19) is a two-man powered NAND gate (hereinafter referred to as 2NAND), and (20) is a two-man powered AND gate (hereinafter referred to as 2AND).
). Next, we will explain the operation. In FIG. 1, when the signal applied from the test terminal (21) is H, the control terminal (
15), when the L signal is applied from 2NAND (1
The output signal of 9) becomes H, and the PMO8f61 turns off. Also, the output buffer (10) becomes a signal output state, and the H signal or L signal applied from the input data terminal (14) is passed through the output buffer (10). The signal is propagated to the pad (1), and further propagated to the output data terminal (]3) via the input buffer (9), but in this case, since PMO3 (61) is in the off state, even when the output buffer (lO) outputs an L signal, There is no current flow between the power supply (5) and the ground (7). Next, when an H signal is applied from the control terminal (15), 2
The output of N A N D (19) becomes L and PuO2
(6) is in the on state, and the output buffer (lO) is in the output high-impedance state, and the external H or L signal applied from the pad (11) is in the input buffer (lO).
9) to the output data terminal (13).

On the other hand, if no external input signal is applied from the pad (1) at this time, the input signal to the input buffer (9) becomes R through the P-08 (6) which is in the ON state, and the input buffer (9) The H signal is propagated to the output data terminal (13) via. Next, when the signal applied from the test terminal (21) is L, the output signal of 2 N A N D (19) becomes 'H', regardless of the signal applied from the control terminal (15), and PuO2 (6 ) is in the off state.

Therefore, in this case, the HL of the output signal of the output buffer (lO) and the external input signal input from the pad (1)
No current bus is created between the power supply (5) and ground, regardless of the current. Therefore, during actual use, the signal applied to the test terminal (21) should be fixed at H.

a power supply (5) when the output buffer (10) is in a signal output state;
If the current between the ground and the ground can be eliminated, and if the signal applied to the test terminal (21) is fixed at L during the shipping test, PMO8+61 will maintain the OFF state by using PuO
2 (61), no current flows from the power supply (5) to the ground, and the bidirectional buffer circuit with pull-up resistor (3
) allows accurate static special power leak current testing regardless of the output status and external H/L color code input status, and the output buffer (10) output high impedance status! Accurate output leakage current testing at 1 is also possible.

Similarly, in Figure 2, the test terminal (22
) if the signal applied to the control terminal (1
When the signal applied to 8) is L, that is, when the output buffer (12) is in the signal output state, the output signal of 2AND (20) becomes L, and 8MO8 (8) is turned off, and the power supply,
No current flows between the ground (7) through the 8MO8 (81), and if the signal applied to the test terminal (22) is fixed at L during shipping tests, the signal applied from the control terminal (18) Regardless of Ill/LK, the output signal of 2AND becomes L and 8MO8 (8) maintains the off state, so it is connected from the power supply to ground (7) via N v o s (8).
No current flows to the output buffer (12), allowing accurate static special power leak current testing regardless of the output state of the bidirectional buffer circuit with pull-down (4) or the external El/L signal input state. ) It is also possible to accurately test the output leakage current in the output high impedance state.

〔Effect of the invention〕

As described above, according to the present invention, the pull-up resistor and pull-down resistor element control logic elements are installed in the same buffer circuit section, and the test terminal is provided, so that the pull-up resistor and pull-down resistor can be turned on and off from the outside at the time of shipping. PuO2, which can be controlled to turn off and is a pull-up resistor element
, the gate of N'dos which is a pull-down element, No.7
It is possible to minimize the potential difference between voltages and suppress the tail current effect, allowing accurate static special power leakage current testing for all test patterns for functional verification during load testing, and bidirectional buffer output high with pull-up resistor material or pull-down resistor. Accurate output leakage current test in impedance state is possible, and in actual use, when a bidirectional buffer signal with pull-up resistor or pull-down resistor is output, the through current between power supply and ground can be reduced, and current consumption can be suppressed. There is an effect that makes it possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a bidirectional buffer circuit with a pull-up resistor which is an embodiment of the present invention, FIG. 2 is a circuit diagram of a bi-directional 3777 circuit with a pull-down resistor which is another embodiment of the present invention, and FIG. The figure is a circuit diagram of a conventional bidirectional buffer circuit with a pull-up resistor, and FIG. 4 is a circuit diagram of a conventional bidirectional buffer circuit with a pull-down resistor. In the figure, (1) (21 is a pad, (3) is a bidirectional buffer with a pull-up resistor, (4) is a bidirectional buffer with a pull-down resistor, (5) is a power supply, and (6) is a PM
Os , (7) is grounded, (8) is N v OS , (
91 (11) is an input buffer, (10) (12) is an output buffer, (13) (16) is an output data terminal, (
14) (17+ is input data terminal, (15n (18)
is a control terminal, (19) is 2NAND, (20) is 2AN
D, (21) and (22) indicate tenuto terminals. In addition, in the figures, the same symbols indicate the same or equivalent parts. Deputy Masuo Oiwa 21st iml! gI Figure 3 Figure 4 Procedural Amendment C@issued] 861B 1998 Month/Day

Claims (1)

[Claims] A CMOS gate array bidirectional buffer circuit section with a pull-up resistor or a pull-down resistor, comprising a logic element for controlling the pull-up resistor or the pull-down resistor element and a control signal terminal.
OS gate array.