JPH04152502A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH04152502A JPH04152502A JP2276152A JP27615290A JPH04152502A JP H04152502 A JPH04152502 A JP H04152502A JP 2276152 A JP2276152 A JP 2276152A JP 27615290 A JP27615290 A JP 27615290A JP H04152502 A JPH04152502 A JP H04152502A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- thick film
- thick
- bonding
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000009966 trimming Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
混成集積回路、特に抵抗値が調整できる厚膜抵抗体を有
する混成集積回路に関し、
厚膜抵抗体を形成した後、容易にがっ安定性よくその抵
抗値を調整することを目的とし、基板１０上において、
厚膜抵抗体１が両端で厚膜導体２．３と接続しており、
１つの厚膜導体２に近い厚膜抵抗体１の領域にボンディ
ング用導体４゜５の群があり、この群はこの厚膜導体２
がらの距離が異なる複数のボンディング用導体４・５が
らなり、ボンディング用導体４，５の少なくとも１つが
この厚膜導体２上のボンディング用導体６と導電性ワイ
ヤ７で接続され、これによって厚膜抵抗体が所望の抵抗
値を有するように構成する。[Detailed Description of the Invention] [Summary] Regarding a hybrid integrated circuit, especially a hybrid integrated circuit having a thick film resistor whose resistance value can be adjusted, after the thick film resistor is formed, its resistance can be easily and stably adjusted. For the purpose of adjusting the value, on the substrate 10,
A thick film resistor 1 is connected to a thick film conductor 2.3 at both ends,
There is a group of bonding conductors 4°5 in the area of the thick film resistor 1 close to one thick film conductor 2, and this group is connected to this thick film conductor 2.
At least one of the bonding conductors 4 and 5 is connected to the bonding conductor 6 on the thick film conductor 2 by a conductive wire 7, thereby forming a thick film. The resistor is configured to have a desired resistance value.
本発明は、混成集積回路、特に抵抗値が調整できる厚膜
抵抗体を有する混成集積回路に関する。The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit having a thick film resistor whose resistance value can be adjusted.
従来、厚膜抵抗体の抵抗値を調整するには、厚膜抵抗体
１にレーザー光線を照射し、第２図に示すように、その
軌跡８に沿って厚膜を融解させてトリミングを行って抵
抗値を増加させることが行われていた。しかし厚膜抵抗
体１はトリミング軌跡８の近傍に熱ストレスが加わるの
で、微細なりラック９が発生する。特にトリミング軌跡
８の終点または屈折点の付近では発生が著しい。そのた
め、高電圧が印加される回路では、使用中にクラックが
ますます成長して抵抗値が増加するばかりでなく、つい
には厚膜抵抗体が切断してしまう欠点があった。Conventionally, in order to adjust the resistance value of a thick film resistor, the thick film resistor 1 is irradiated with a laser beam and the thick film is melted and trimmed along the trajectory 8 as shown in FIG. Efforts were made to increase the resistance value. However, since thermal stress is applied to the thick film resistor 1 in the vicinity of the trimming locus 8, a fine rack 9 is generated. The occurrence is particularly noticeable near the end point or refraction point of the trimming trajectory 8. Therefore, in a circuit to which a high voltage is applied, cracks not only grow more and more during use, increasing the resistance value, but also cause the thick film resistor to eventually break.
本発明は、微細なりラックを発生させることなく、抵抗
値の調整を行うことができる厚膜抵抗体を有する混成集
積回路を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit having a thick film resistor that allows adjustment of the resistance value without generating minute racks.
上記課題は、基板１０上において、厚膜抵抗体１が両端
で厚膜導体２．３と接続しており、１つの厚膜導体２に
近い厚膜抵抗体１の領域にボンディング用導体４．５群
があり、この群はこの厚膜導体２からの距離が異なる複
数のボンディング用導体４．５からなり、ボンディング
用導体４，５の少なくとも１つがこの厚膜導体２上のボ
ンディング用導体６と導電性ワイヤ７で接続され、これ
によって抵抗を所望の値とした厚膜抵抗体を有すること
を特徴とする混成集積回路によって解決することができ
る。The above problem is solved because the thick film resistor 1 is connected to the thick film conductor 2.3 at both ends on the substrate 10, and the bonding conductor 4. There are 5 groups, and this group consists of a plurality of bonding conductors 4.5 at different distances from the thick film conductor 2, and at least one of the bonding conductors 4 and 5 is connected to the bonding conductor 6 on the thick film conductor 2. This can be solved by a hybrid integrated circuit characterized in that it has a thick film resistor connected to the resistor by a conductive wire 7, thereby setting the resistance to the desired value.
第１図は本発明の原理説明図である。厚膜抵抗体１は両
端で厚膜導体２．３に接続している。ボンディング用導
体４は、一方において厚膜導体２上のボンディング用導
体６と接続しており、また図に示すように、他方におい
て、この厚膜導体２からの距離が遠い厚膜抵抗体１上の
他のボンディング用導体５と接続することもできる。１
つの厚膜導体２からこれらのボンディング用導体４・５
を結ぶ導電性ワイヤ７を経て、他端の厚膜導体３に至る
間の抵抗は、厚膜抵抗体１の当初の抵抗値より小さい。FIG. 1 is a diagram explaining the principle of the present invention. Thick film resistor 1 is connected at both ends to thick film conductors 2.3. The bonding conductor 4 is connected on one side to the bonding conductor 6 on the thick film conductor 2, and on the other hand, as shown in the figure, on the thick film resistor 1 which is far away from the thick film conductor 2. It can also be connected to other bonding conductors 5. 1
These bonding conductors 4 and 5 from the two thick film conductors 2
The resistance between the conductive wire 7 connecting the conductive wire 7 and the thick film conductor 3 at the other end is smaller than the initial resistance value of the thick film resistor 1.
第３図は、本発明の１つの実施態様を示す厚膜抵抗体の
平面図である。銀−パラジウム合金ペースト厚膜導体２
，３を両端で跨ぐように、１．０×１、５ ｍｍの酸化
ルテニウムペースト厚膜抵抗体ｌを設け、この上に９個
の金ペーストボンディング用導体をゴバンの目状に０．
３ ｍｍ間隔で設け、厚膜導体２上にも同じく金ペース
トの３個のボンディング用導体６を設け、さらに図示し
ない他の素子も設けてセラミック基板を焼成した。この
厚膜抵抗体１の厚膜導体２，３間の抵抗値は１．ＯＫΩ
であった。図に示すように、各群のボンディング用導体
４を、厚膜導体２上のボンディング用導体６に金ワイヤ
７で接続し、さらに１つの群のボンディング用導体４を
、この群の他のボンディング用導体５にも接続した。そ
の結果抵抗値は９７０Ωに減少した。FIG. 3 is a plan view of a thick film resistor showing one embodiment of the present invention. Silver-palladium alloy paste thick film conductor 2
A ruthenium oxide paste thick film resistor l of 1.0 x 1.5 mm was provided so as to straddle both ends of the ruthenium oxide paste resistor l, and nine gold paste bonding conductors were placed on top of this in a goblin pattern.
Three bonding conductors 6 made of gold paste were also provided on the thick film conductor 2 at intervals of 3 mm, and other elements (not shown) were also provided, and the ceramic substrate was fired. The resistance value between the thick film conductors 2 and 3 of this thick film resistor 1 is 1. OKΩ
Met. As shown in the figure, the bonding conductors 4 in each group are connected to the bonding conductors 6 on the thick film conductor 2 with gold wires 7, and the bonding conductors 4 in one group are connected to the bonding conductors 6 on the thick film conductor 2. It was also connected to conductor 5. As a result, the resistance value was reduced to 970Ω.
なお、厚膜導体の材料は、金導体または銅導体などを使
用することができ、ワイヤは、アルミニウムまたは銅な
どを使用できる。またボンディング用導体は、ワイヤの
種類によって、適当な接続強度の得られる他の導体を使
用することができる。Note that the material for the thick film conductor can be a gold conductor, a copper conductor, or the like, and the wire can be made of aluminum, copper, or the like. Further, as the bonding conductor, other conductors that provide suitable connection strength can be used depending on the type of wire.
本発明によればレーザートリミングが不要となり、レー
ザー切断部分が必要でなくなるので、抵抗体膜の面積を
小さくすることができる。また抵抗値の調整は、レーザ
ーによる微細なりラックの発生による抵抗値のドリフト
がなくなるばかりでなく、高電圧が印加される電子回路
において抵抗値の安定な調整が可能となる。さらに従来
はレーザートリミングによって抵抗体が部分的に分割さ
れるので、抵抗体の熱分布が変わってしまうが、本発明
では抵抗体の形状は設計時のままであり膜の有効面積が
従来に比べて大きく、かつ熱分布の均一化をはかること
ができる。According to the present invention, laser trimming is not necessary, and a laser cutting portion is not required, so that the area of the resistor film can be reduced. Further, the adjustment of the resistance value not only eliminates resistance value drift due to the generation of fine cracks caused by the laser, but also enables stable adjustment of the resistance value in electronic circuits to which high voltage is applied. Furthermore, in the past, the resistor was partially divided by laser trimming, which changed the heat distribution of the resistor, but in the present invention, the shape of the resistor remains as it was designed, and the effective area of the film is larger than before. It is possible to achieve a uniform heat distribution.
第１図は、本発明の原理を示す厚膜抵抗体の断面図であ
り、
第２図は、従来技術の厚膜抵抗体の平面図であり、
第３図は、本発明の実施態様の厚膜抵抗体の平面図であ
る。
１・・・厚膜抵抗体、 ２．３・・・厚膜導体、４
．５．６・・・ボンディング用導体、７・・・導電性ワ
イヤ、 ８・・・トリミング軌跡、９・・・微細な
りランク、 １０・・・セラミック基板。
本発明の詳細な説明する厚膜抵抗体の断面図第１図
従来技術の厚膜抵抗体の平面図
第２図
８・・・トリミング軌跡
９・・・微細なりランク
１０・・・セラミフク基板FIG. 1 is a cross-sectional view of a thick film resistor showing the principle of the present invention, FIG. 2 is a plan view of a conventional thick film resistor, and FIG. 3 is a cross-sectional view of a thick film resistor according to an embodiment of the present invention. FIG. 2 is a plan view of a thick film resistor. 1...Thick film resistor, 2.3...Thick film conductor, 4
．． 5.6... Conductor for bonding, 7... Conductive wire, 8... Trimming locus, 9... Fine rank, 10... Ceramic substrate. FIG. 1 is a cross-sectional view of a thick film resistor explaining the present invention in detail. FIG. 2 is a plan view of a thick film resistor according to the prior art.
Claims (2)
体２、３と接続しており、１つの厚膜導体２に近い厚膜
抵抗体１の領域にボンディング用導体４、５の群があり
、この群はこの厚膜導体２からの距離が異なる複数のボ
ンディング用導体４、５からなり、ボンディング用導体
４、５の少なくとも１つがこの厚膜導体２上のボンディ
ング用導体６と導電性ワイヤ７で接続され、これによっ
て抵抗を所望の値とした厚膜抵抗体を有することを特徴
とする混成集積回路。1. On the substrate 10, a thick film resistor 1 is connected to thick film conductors 2 and 3 at both ends, and a group of bonding conductors 4 and 5 is arranged in a region of the thick film resistor 1 near one thick film conductor 2. This group consists of a plurality of bonding conductors 4 and 5 having different distances from the thick film conductor 2, and at least one of the bonding conductors 4 and 5 has conductivity with the bonding conductor 6 on the thick film conductor 2. A hybrid integrated circuit characterized in that it has thick film resistors connected by wires 7, thereby setting the resistance to a desired value.
厚膜抵抗体１上のボンディング用導体４が、さらにこの
厚膜導体２から遠い位置にある他のボンディング用導体
５と、導電性ワイヤ７で接続されている、請求項１記載
の混成集積回路。2. The bonding conductor 4 on the thick film resistor 1 connected to the bonding conductor 6 on the thick film conductor 2 is connected to another bonding conductor 5 located further away from the thick film conductor 2 and the conductive wire 7 2. The hybrid integrated circuit according to claim 1, wherein the hybrid integrated circuit is connected by a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2276152A JPH04152502A (en) | 1990-10-17 | 1990-10-17 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2276152A JPH04152502A (en) | 1990-10-17 | 1990-10-17 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04152502A true JPH04152502A (en) | 1992-05-26 |
Family
ID=17565485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2276152A Pending JPH04152502A (en) | 1990-10-17 | 1990-10-17 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04152502A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016121203A1 (en) * | 2015-01-26 | 2016-08-04 | Koa株式会社 | Chip resistor |
-
1990
- 1990-10-17 JP JP2276152A patent/JPH04152502A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016121203A1 (en) * | 2015-01-26 | 2016-08-04 | Koa株式会社 | Chip resistor |
| CN107210103A (en) * | 2015-01-26 | 2017-09-26 | 兴亚株式会社 | Patch resistor |
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