JPH04149653A - Read/comparison system for duplex memory - Google Patents

Abstract

PURPOSE:To reduce the capacity of a buffer by controlling a selector with the output of a preceding data deciding part to store the preceding data in a data buffer and to store the subsequent data in a comparison data register respectively and comparing both data with each other by a comparator. CONSTITUTION:The 1st and 2nd selectors 31 and 32 with the output of a preceding data deciding part 30. Then the preceding data are stored in a data buffer 33 and the subsequent data are stored in a comparison data register 34 respectively. Then the data comparison timing is secured for a comparator 35. In such a constitution, the data buffers that cause the increase of hardware can be decreased down to just a single unit. Then the capacity of the buffer storing the data read out of a duplex memory can also be reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a duplex memory read comparison system in a system in which a processing device and two external memories (duplex memories) are connected, the capacity of a buffer for storing data read from the duplex memory is calculated. For the purpose of reducing the number of data, there are memories forming the duplex memory, a preceding data determination unit that receives the outputs of these memories and determines which memory has the data leading, and the output of each of the duplex memories. a first selector that receives and selects one of the outputs; a second selector that also receives the respective outputs of the duplex memory and selects one of the outputs; and a data buffer that stores the output of the first selector. , a comparison data register that receives the output of the second selector, and a comparison circuit that compares the outputs of these data buffers and the comparison data register;
and controls the second selector to change the preceding data to data -
The buffer is configured to store subsequent data in comparison data registers, and to take timing when data is compared by a comparison circuit.

[Industrial Application Field] The present invention is a processing device and two external memories (duplex memory).
The present invention relates to a read comparison system for duplex memories in a system in which these are connected.

A data processing computer system has a configuration in which two memories (duplex memories) are connected to one processing device in order to maintain high reliability.

In this type of system, the same data is written in two memories, and when reading it, the same 7 traces of data are read out, and only when the data in both nodes are matched, is that data used as data for data processing. A system has been adopted as follows. In the case of 2, the two systems may be connected to each other due to reasons such as the fact that the redundant memory is a storage device that can operate independently, has its own clock, or has different retrieval timing. The time it takes for the data to reach the processing device is delayed. In order to absorb this deviation, it is desirable to provide a notch for each memory, or to make the capacity of this notch as small as possible.

[Prior Art] FIG. 5 is a block diagram showing an example of the configuration of a conventional system. The data read from the duplex memories 1 and 2 enters the transfer control unit 10. Transfer control unit] (-) has data notches 11,1:2.1-these data buffers 11.1. ．． A comparing section 1' for comparing the output data of the two is included. The data read from each duplex memory 1.2 is transferred to each data buffer 11.1.
2 are sequentially stored. Then, the data stored at the same address are simultaneously read out and compared by the comparator 13.

As a result of the comparison by the comparison unit 1', if both data match, it is determined that the data is normal, and the processing unit 'fj
t2 (Written to main storage unit (MSU) 21 in 1. Processing unit! [CPtJ22 in 20 is 2.9 MSU
Based on the data read from 21, predetermined arithmetic processing, etc.
HC) 23 and outputs it to the input/output device (1/"0).

In a system configured as described above, in a conventional duplex system, data is simultaneously read from two duplex memories 1.2 and stored in data buffers 11.12 in order to confirm the identity of both systems. The reason why the data buffers 11 and 12 are provided here is because this type of duplex memory C is a storage device that can operate independently. This is based on the fact that the timings at which the data arrives are different for both systems due to reasons such as differences in the timings of the two systems.In other words, in order to absorb the timing difference between the two systems,
Data buffers 11 and 12 are provided corresponding to each duplex memory, and a comparison is made when the data of both systems of the same address are complete.

Then, as a result of the comparison in the comparison unit 13, the data of both systems matched ('O), and it was determined that the 11 normality of the data T was secured, and it was written to the NI S L,i 21. ing. As a result of the comparison by the comparison unit 1-3, if the pigs of both systems do not match (-2), the transfer control unit 10 performs a predetermined discrepancy process.

FIG. 6 is a general diagram of the conventional comparison method. Arrows - indicate the storage addresses of data from each memory. This shows the case where data is stored sequentially in memory 1.When the data in the shaded area arrives from memory 1, the data is stored sequentially.
Therefore, the data is compared with the data in the shaded area of the rough 712. In this case, it is allowed to advance by the capacity of one data buffer.

[Problems to be solved by Je Ming] As mentioned above, the Congregation system has two data buffers 11 and 12 in order to absorb the time difference between the data of the two systems. In this case, the permissible range of the time difference in the arrival of the read deck is up to the capacity of one data sofa. If the time difference increases beyond that, it is necessary to temporarily stop reading the preceding memory. This can be a cause of low system performance, and it is one of the problems that the hardware (especially the dekubenotsa) is not efficient enough.

The present invention has been made in view of the above-mentioned problems, and has as its object the provision of a read comparison system for duplexed memory 11 that can reduce the capacity of a buffer for storing data read from duplexed memory. There is.

[F stage that does not solve the problem] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 5 are designated by the same reference numerals. Reference numerals 1 and 2 refer to memories constituting the duplexed memories, 3 ( ) receives the outputs of these memories 1 and 2 and determines which memory the data comes from in advance, and 31 refers to the duplexed memory. A first selector receives each output of the memory 12 and selects one of them; 32 is a second selector that receives each output of the duplex memory ++x and 2 and selects one of the two; 33 is a second selector that selects one of the two 1st
a data buffer 34 for storing the output of the selector 31;
is a comparison data register that receives the output of the second selector 32, and the registers 34 and 35 are comparison circuits that compare the outputs of the decoder 7733 and the comparison data register 34.

Ef') Control the 1st and 20th cycle p31.32 by the output of the preceding data determination unit 3)) Compare data
The data are stored in five blocks 34, respectively, and the comparison circuit 35 is configured to take the timing when comparing the data.

With this configuration, the e-ware increase IJ
Data that causes outdated data \ Only one sofa is required, and data read from the duplex memory is stored...! It is possible to reduce the file size.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Figure 1 and [ti- are indicated by the same reference numerals as E1 (.In the figure, 1 and 2 are duplex memories (hereinafter, duplex memory 1 will be abbreviated as memory 0 and duplex memory 2 will be abbreviated as memory 1). ).41 is a data port () that temporarily holds data read from memory 0.
42 is a data port 1 (hereinafter abbreviated as data port 1) which temporarily holds data read from the memory. Reference numeral 43 denotes a buffer that holds the baritbiso[* read out from memory 0;

130 is ＼B+1 held in Notsa 43.44
! A preceding data determining unit 31 determines which of the data read out from memory 0 by Tobinodo was read out first.
A first selector (above, PF) receives memory read data from the data boat 1 and selects preceding data on the memory side in response to a control signal from the preceding data determination unit 30.
Selector 0 (abbreviated as 0) is on the instep, and 32 is the data port 0. After receiving the memo + 1 read data from data port 1 or C1, the control signal from the preceding data determination unit-30 causes the data to be read later.
, memo! This is a second selector/lid (hereinafter simply referred to as selector 1) that selects data on the side.

33 is a data register 77 which sequentially stores the output from selector 0, and 34 is a comparison data register which holds the output from selector 1. 45 is a fetch data register for fetching data read from the data register 733;
A comparison circuit 35 compares the output from the fetch register 45 (read data from the data buffer 33) with the data read from the comparison data register 34.

The output of the fetch data register 45 and the output of the comparison circuit 35 are sent to the request source (for example, the processing device 20 in FIG. 5).

46 is a transfer control unit that performs transfer control when transferring data from memory [1, 1 to a request source; 47 is a data address control unit that controls the address of the data buffer 33; and 48 is a data port []i address. The register 49 that holds λ is updated across the value of λ 48 +
1 circuit, 50 is a register that holds the address of data port 1, 51 is a register that updates the value of the register 50 +
It is one circuit. Update control of these addresses is performed by the data buffer address control section 47 described above.

Reference numeral 52 designates one of the outputs of the register 48.5CF as a data buffer address according to a control signal from the data buffer address control unit 47, and the data buffer 33
This is a selector that can be used to Reference numeral 53 denotes an error determination unit which receives the duplex memory 0 error and duplex memory 1 error signals, performs error determination, and sends the results to the request source. The memory error here refers to an error that is output from each memory 1.2 when a read error occurs due to an FCC check or the like when reading data in the memories 1.2. The operation of the circuit configured in this way will be explained as follows.

First, the concept of the present invention is illustrated in FIG. 3. Like the conventional method shown in Figure 6, this is an example in which memory 0 takes the lead, and when data arrives from memory 1, the data to be compared indicates data buffer address 1, so its contents are The contents of the comparison data file/meta 34 are compared.

Below, FIG. 2 will be explained. Processing device (request source)
When a data transfer request is received from memory 0.1, data transfer from memory 0.1 is started, and each data port (),
The data read to 1 is retained and the buffer 743.44
The valid bits of each memory are maintained. Here, it is assumed that there is a response before the data of data port () or the data of data port 1. data port 1], and notifies the data buffer address control unit 47 of this fact.Furthermore, a select signal is given to the selector 31 to output the data of data port 0. It is applied to the data buffer 33.

Upon receiving the signal from the preceding data determining section 30, the data buffer address control section 47 outputs a select signal to the selector 52, selects the address of data port O of the register 48, and stores 'j' in the data buffer 33. As a result, the data given from the selector 31 is written into the data buffer 33 at the address given from the selector 52. Simultaneously with the second data write, the data buffer address control section 47 operates four +1 adders to increment the data port address of the data buffer 33 by one.

Next, the data read from the memory 1 and the no \lit bit are sent to the data port 1.1 and the buffer 44 with a delay. The preceding data determining unit 30 receives the valid bits from the respective buffers 43 and 44, determines that delayed data has arrived at the data port 1, and notifies the data buffer address control unit 47 of this fact. Further, a select signal is sent to the selector 1, and the data of the data port 1 is output and applied to the comparison data register 34.

At this time, the address of the data to be compared with the contents of the comparison data register 34 is the data port address 1 of the second star 50.
given from. Therefore, the data buffer address control section 47 supplies a select signal to the selector 52 to output the data port 1 address, which is the content of the register 5(-), and supplies it to the data buffer 33.

Next, the transfer control unit 46 sets the data read from the data buffer 33 into the 7-enochi data register 45.

The comparison circuit 35 compares the preceding data held in the fetch data register 45 and the succeeding data held in the comparison data register '34. The result of the comparison is 7
It is sent to the request source together with the contents of the Esochi data register 45. In other words, if both data match as a result of the comparison by the comparison circuit 35, the contents of the fetch data register 45 will be d.
Two things happen: the data is stored in the requesting MSU (not shown) as data read from memory.

On the other hand, when the data transfer is completed and the transfer control unit 46 notifies the error determination unit 5'3 of the end, the error determination unit 53 notifies the request source of this if a read error occurs during the data transfer. .

Hereinafter, the case where the data from memory 0 precedes is explained as an example, or the data from memory 1 may precede. In that case, the output of the selector 1 is given to the data buffer 33, and the output of the selector (-) is set to the comparison data register 34.The data writing address of the sofa 33 to the data at this time is data port 1. The address is given from the register 50 that holds the address.Then, the data read from the data 11 buffer 33 and the contents of the comparison data register 34 are compared by the comparison circuit 35.

FIG. 4 is a time chart showing the operation of the present invention. In the figure, W is a data buffer write state, R is a data buffer read state, and C is a comparison state. First, data enters data port 0 first (■). This data is written to the data 11 buffer 73' and sent to the fetch data register 45 at the same time.

Next, data comes into data port 1 (■). This data is sent to the comparison data register 34 (■
). In this state, the data read from the data buffer '33 (output of the fetch data register 45) and the output of the comparison data register 34 are compared by the comparison circuit 35 (■). The same applies hereafter.

[Effects of the Invention] As described above in detail, according to the present invention, the data read from the duplex memory can be sequentially timed by setting the leading I data in the data buffer and the trailing data as comparison data and setting it in the sister. It can be compared well, and the capacity of one software for storing data read from the duplex memory can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a configuration block diagram showing an embodiment of the present invention, Fig. 3 is a conceptual diagram of a comparison method according to the present invention, and Fig. 4 shows the operation of the present invention. 5 is a diagram showing a configuration example of a conventional system, and FIG. 6 is a conceptual diagram of a conventional comparison method. In FIG. 1, 1.2 is a duplex memory, 30 is a preceding data determination section, 31 and 32 are selectors, 33 is a data buffer, 34 is a comparison data register, and 35 is a comparison circuit.

Claims (1)

[Claims] Memories (1) and (2) that constitute the duplex memory, and a preceding device that receives the outputs of these memories (1) and (2) and determines which memory has the preceding data. a data determination section (30); and a first selector (31) that receives the respective outputs of the duplex memories (1) and (2) and selects one of them.
), a second selector (32) that similarly receives the respective outputs of the duplex memories (1) and (2) and selects one of them, and data that stores the output of the first selector (31). a buffer (33); a comparison data register (34) that receives the output of the second selector (32); and a comparison circuit (35) that compares the outputs of the data buffer (33) and the comparison data register (34). The first and second
The selectors (31) and (32) are controlled to store the preceding data in the data buffer (33) and the succeeding data in the comparison data register (34), respectively, and then the comparison circuit (35)
What is claimed is: 1. A read comparison system for dual memory, characterized in that the system is configured to take timing when comparing data.