JPH04148538A - Tab semiconductor device - Google Patents

Tab semiconductor device

Info

Publication number
JPH04148538A
JPH04148538A JP2272409A JP27240990A JPH04148538A JP H04148538 A JPH04148538 A JP H04148538A JP 2272409 A JP2272409 A JP 2272409A JP 27240990 A JP27240990 A JP 27240990A JP H04148538 A JPH04148538 A JP H04148538A
Authority
JP
Japan
Prior art keywords
substrate
hole
tie bar
lead
molding material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2272409A
Other languages
Japanese (ja)
Other versions
JP2833189B2 (en
Inventor
Harumi Miyao
宮尾 晴美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2272409A priority Critical patent/JP2833189B2/en
Publication of JPH04148538A publication Critical patent/JPH04148538A/en
Application granted granted Critical
Publication of JP2833189B2 publication Critical patent/JP2833189B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance productivity and yield by a method wherein one or two or more tie bars are installed at the outside of a tie bar so as to be separated by an outer lead hole in order to eliminate a danger that a substrate is contaminated and that a through hole is blocked up. CONSTITUTION:A second tie bar 8a is formed at the outside of a tie bar 8 so as to be separated by outer lead holes 4. When such a semiconductor device is mounted on a substrate and its outer circumference is coated with a molding material, the molding material 9 flows over the tie bar 8 when its amount is much. However, the molding material 9 is stopped by the second tie bar 8a and does not reach the substrate 11. Consequently, there is no danger that the substrate 11 is contaminated and that a through hole is blocked up. Since the two tie bars 8, 8a are installed at a lead 3, a stress exerted on the lead 3 is relaxed after it has been bonded to a conductive pattern 12.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、可撓性フィルムに半導体素子を実装してなる
TAB式半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a TAB type semiconductor device in which a semiconductor element is mounted on a flexible film.

[従来の技術] ポリイミドフィルムの如き可撓性のフィルムに半導体装
置を搭載し、その電極にフィルムに設けたリードを接続
してなるTAB式半導体装置は、多量生産に適する、小
形化できる、ファインパターン化が可能であるなど種々
特徴を有するため、現在では広く使用されている。
[Prior Art] A TAB type semiconductor device, in which a semiconductor device is mounted on a flexible film such as a polyimide film, and leads provided on the film are connected to the electrodes, is suitable for mass production, can be miniaturized, and is a fine-grained semiconductor device. It is currently widely used because it has various features such as being able to be patterned.

第7図はTAB式半導体装置の製造過程の一例を示す平
面図で、(1)は長尺のフィルム、(2)はフィルム(
1)の長さ方向に一定の間隔で設けられたデバイスホー
ル、(3)はフィルム(1)上に設けられた銅箔の如き
導電率の高い材料からなるリードで、その先端部はデバ
イスホール(2)内に突出してインナーリード(3a)
を形成している。(4)はデバイスホール(2)の外側
にこれと平行に形成され、リード(3)の外端部、即ち
アウターリード(3b)を露出させるためのアウターリ
ードホール、(5)はフィルム(1)を搬送するための
スプロケット穴である。(6)はデバイスホール(2)
内に配設され、その電極がインナーリード(3a)に接
続された半導体素子である。
FIG. 7 is a plan view showing an example of the manufacturing process of a TAB type semiconductor device, in which (1) is a long film, (2) is a film (
1) device holes provided at regular intervals in the length direction; (3) is a lead made of a highly conductive material such as copper foil provided on the film (1), the tip of which is connected to the device hole. (2) Inner lead protruding inward (3a)
is formed. (4) is an outer lead hole formed outside and parallel to the device hole (2) to expose the outer end of the lead (3), that is, the outer lead (3b); (5) is an outer lead hole formed in parallel with the device hole (2); ) is a sprocket hole for conveying. (6) is device hole (2)
It is a semiconductor element disposed inside the inner lead (3a), and its electrode is connected to the inner lead (3a).

このようにして半導体素子(6)が接続されたフィルム
(1)はプレス等により切断線(7)で切断8れ、第8
図に示すように個々の半導体装置となる。
The film (1) to which the semiconductor element (6) is connected in this way is cut 8 along the cutting line (7) using a press or the like.
As shown in the figure, these become individual semiconductor devices.

なお、(8)は切断の際残置されたフィルムで、般にタ
イバーと呼ばれている。
Note that (8) is a film left behind during cutting and is generally called a tie bar.

第9図は上記のような半導体装置を基板等に実装した状
態を示す模式図で、(11)は基板、(12)は基板(
11)上に形成された導電パターンである。半導体装置
はその能動面を下にして基板(11)上に載置され、ボ
ンディングツールによりアウターリード(3b)を導電
パターン(12)に接続する。そして、湿気等の侵入を
防止するため、半導体素子(6)の外周と基板(11)
との間に、半液体状樹脂のモールド材(9)を塗布する
FIG. 9 is a schematic diagram showing the state in which the above-described semiconductor device is mounted on a substrate etc. (11) is the substrate, (12) is the substrate (
11) A conductive pattern formed thereon. The semiconductor device is placed on the substrate (11) with its active side facing down, and the outer leads (3b) are connected to the conductive patterns (12) by a bonding tool. In order to prevent moisture from entering, the outer periphery of the semiconductor element (6) and the substrate (11) are
A semi-liquid resin molding material (9) is applied between the two.

[発明が解決しようとする課題] 上記のようなモールド材(9)は、半導体素子(6)と
タイバー(8)との間を充填するように塗布しているが
、モールド材(9)の量が多いと、タイバー(8)を乗
り越えて基板(11)上に流れ出すことが屡々ある。ま
た、モールド材(9)の乾燥工程においても、熱によっ
て流動したモールド材(9)が、タイバー(8)を越え
て流出することがある。
[Problems to be Solved by the Invention] The molding material (9) as described above is applied so as to fill the space between the semiconductor element (6) and the tie bar (8). If the amount is large, it often flows over the tie bars (8) and onto the substrate (11). Furthermore, during the drying process of the molding material (9), the molding material (9) fluidized by heat may flow out over the tie bars (8).

このため、基板(11〉が汚れるのでその清掃や除去が
きわめて面倒で生産性の向上を阻害するばかりでなく、
ときとして、基板(11)に設けたスルーホールが閉塞
されてしまうこともある。
As a result, the substrate (11) gets dirty, making cleaning and removal extremely troublesome, which not only impedes productivity improvement, but also
Sometimes, the through holes provided in the substrate (11) may become blocked.

本発明は、上記の課題を解決すべくなされたもので、半
導体素子の外周に塗布するモールド材が基板上に流出す
るおそれのないTAB式半導体装置を得ることを目的と
したものである。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a TAB type semiconductor device in which there is no possibility that molding material applied to the outer periphery of a semiconductor element will flow out onto a substrate.

[課題を解決するための手段] 本発明にかかるTAB式半導体装置は、可撓性フィルム
に設けたデバイスホールの少なくとも対向する2辺の外
側に多数のリードを保持するタイバーを有し、前記デバ
イスホール内に配設された半導体素子の電極に前記リー
ドをそれぞれ接続してなるTAB式半導体装置において
、前記タイバーの外側にアウターリードホールを隔てて
1本又は2本以上のタイバーを設けたものである。
[Means for Solving the Problems] A TAB type semiconductor device according to the present invention has a tie bar for holding a large number of leads on the outside of at least two opposing sides of a device hole provided in a flexible film, and the device A TAB type semiconductor device in which the leads are respectively connected to the electrodes of a semiconductor element arranged in the hole, and one or more tie bars are provided outside the tie bar with an outer lead hole in between. be.

[作 用] 半導体装置を基板等に実装してその外周と基板等との間
にモールド材を塗布する際、モールド材の量が多かった
り乾燥時に流動したりすると、モールド材は、タイバー
を乗越えて流れ出すことがあるが、その流れは第2のタ
イバーによって阻止され、基板等を汚したりスルーホー
ルを閉塞したりすることはない。
[Function] When a semiconductor device is mounted on a substrate, etc. and a molding material is applied between the outer periphery and the substrate, etc., if the amount of molding material is large or flows during drying, the molding material may cross over the tie bars. However, this flow is blocked by the second tie bar and will not stain the substrate or block the through holes.

[実施例] 第1図は本発明実施例を模式的に示した平面図である。[Example] FIG. 1 is a plan view schematically showing an embodiment of the present invention.

なお、第7図で説明した従来例と同じ部分には同じ符号
を付し、説明を省略する。(4a)はアウターリードホ
ール(4)の外側にこれと所定の距離を隔てて、かつ平
行に設けられた第2のアウターリードホールである。
Note that the same parts as in the conventional example explained in FIG. 7 are denoted by the same reference numerals, and the explanation will be omitted. (4a) is a second outer lead hole provided outside the outer lead hole (4) at a predetermined distance from the outer lead hole (4) and in parallel therewith.

12図は上記のようなフィルム(1)を切断線(7)で
切断した状態を示すもので、タイバー(8)の外側には
アウターリードポール(4)を隔てて、第2のタイバー
(8a)が形成されている。
Figure 12 shows the film (1) as described above cut along the cutting line (7).A second tie bar (8a) is placed outside the tie bar (8) with the outer lead pole (4) in between. ) is formed.

上記のような半導体装置を基板に実装してその外周にモ
ールド材を塗布すると、第3図に示すように、モールド
材(9)の量が多いとタイバー(8)を乗越えて流れ出
すことがあるが、このモールド材(9)は第2のタイバ
ー(8a)によって阻止され、基板(11)上まで達す
ることはなく、シたがって基板(11)を汚したりスル
ーホールを閉塞するおそれもない。
When a semiconductor device as described above is mounted on a board and molding material is applied to its outer periphery, as shown in Figure 3, if there is a large amount of molding material (9), it may flow over the tie bars (8). However, this molding material (9) is blocked by the second tie bar (8a) and does not reach above the substrate (11), so there is no risk of contaminating the substrate (11) or blocking the through hole.

また、リード(3)には2本のタイバー(8) 、 (
8a)が設けられているので、導電パターン(12)と
のボンディング後にリード(3)に加わるストレスを緩
和することができる。
Also, the lead (3) has two tie bars (8), (
8a), the stress applied to the lead (3) after bonding with the conductive pattern (12) can be alleviated.

なお、第1図の実施例では、アウターリードホール(4
)の外周にそれぞれ第2のアウターリードホール(4a
)を設けた場合を示したが、リード(3)が設けられて
いる側にのみ第2のアウターリードホール(4a)を設
け、リード(3)が設けられていない側の第2のアウタ
ーリードホール(4a)は省略してもよい。
In addition, in the embodiment shown in FIG. 1, the outer lead hole (4
) are provided with second outer lead holes (4a
), but the second outer lead hole (4a) is provided only on the side where the lead (3) is provided, and the second outer lead hole (4a) is provided on the side where the lead (3) is not provided. The hole (4a) may be omitted.

第4図は本発明の他の実施例の模式的平面図である。第
1図の実施例においては、タイバー(8)の外周に所定
の距離を隔てて第2のタイバー(8a)を設けた側を示
したが、本実施例にいおいては、リード(3)が設けら
れた側にのみ第2のタイバー(8a)を設けたもので、
モールド材(9)の基板(11)上への流出を防止しう
ろことは、第1図の実施例の場合と同様である。
FIG. 4 is a schematic plan view of another embodiment of the present invention. In the embodiment shown in FIG. 1, the second tie bar (8a) is provided on the outer periphery of the tie bar (8) at a predetermined distance, but in this embodiment, the lead (3 ) is provided with a second tie bar (8a) only on the side where it is provided,
The scales for preventing the molding material (9) from flowing onto the substrate (11) are the same as in the embodiment shown in FIG.

第5図は本発明のさらに他の実施例の模式的平面図であ
る。本実施例は半導体素子(8)の四辺に設けられた電
極に、デバイスホール(2)の四辺に設けたリード(8
)をそれぞれ接続した半導体装置に本発明を実施したも
ので、デバイスホール(2)の四辺に沿って設けられた
アウターリードホール(4)の外側に、所定の距離を隔
てて第2のアウターリードホール(4a)を設け、この
第2のアウターリードホール(4a)に沿ってフィルム
(1)を切断したものである。このように構成すること
により、第6図に示すような半導体装置を得ることがで
きる。
FIG. 5 is a schematic plan view of still another embodiment of the present invention. In this embodiment, the electrodes provided on the four sides of the semiconductor element (8) are connected to the leads (8) provided on the four sides of the device hole (2).
), in which a second outer lead is installed at a predetermined distance outside the outer lead hole (4) provided along the four sides of the device hole (2). A hole (4a) is provided and the film (1) is cut along this second outer lead hole (4a). With this configuration, a semiconductor device as shown in FIG. 6 can be obtained.

上記の説明では、タイバーの外側に第2のタイバーを設
けた場合を示したが、タイバーの外側に2本以上のタイ
バーを設けてもよい。
In the above description, a case is shown in which the second tie bar is provided on the outside of the tie bar, but two or more tie bars may be provided on the outside of the tie bar.

また、基板等に実装した半導体装置の周辺と基板との間
にモールド材を塗布する場合の例を示したが、本発明は
これに限定するものではなく、例えば基板等に実装した
半導体素子及びインナーリードをポツティングにより封
止する場合、あるいは基板等に実装する前に、半導体素
子及びインナーリード部分を金型を用いて合成樹脂等で
パッケージする場合などにも本発明を実施することがで
きる。
Further, although an example is shown in which a molding material is applied between the periphery of a semiconductor device mounted on a substrate etc. and the substrate, the present invention is not limited to this. The present invention can also be practiced when the inner leads are sealed by potting, or when the semiconductor element and the inner leads are packaged with synthetic resin or the like using a mold before being mounted on a substrate or the like.

[発明の効果] 以上詳記したように、本発明はTAB式半導体装置のタ
イバーの外側にアウターリードホールを隔てて1本又は
2本以上のタイバーを設けたので、半導体素子の外周と
基板等との間に塗布したり、ボッティングや金型で半導
体素子等を封止したモール材がタイバーを乗越えて流れ
出しても、外側のタイバーによって阻止されて基板等や
フィルム上に流れ出すことがない。このため基板等やフ
ィルムを汚したリスルホールを閉塞したりするおそれが
なく、生産性及び歩留りを向上することができる。
[Effects of the Invention] As described in detail above, the present invention provides one or more tie bars on the outside of the tie bar of a TAB type semiconductor device with an outer lead hole in between, so that the outer periphery of the semiconductor element, the substrate, etc. Even if the molding material coated between the molding material and the semiconductor elements sealed by botting or molding flows over the tie bars, it is blocked by the outer tie bars and does not flow onto the substrate or the film. Therefore, there is no risk of clogging the squirrel holes that have contaminated the substrate or the like, and productivity and yield can be improved.

また、リードは複数本のタイバーで保持されているので
、リードの曲りや捩れを防止することができ、さらに、
半導体素子の電極への接続後にリードに加わるストレス
が緩和され、接続の歩留り及び信頼性を向上することが
できる。
In addition, since the lead is held by multiple tie bars, it is possible to prevent the lead from bending or twisting.
The stress applied to the lead after connection to the electrode of the semiconductor element is alleviated, and the yield and reliability of the connection can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明実施例を模式的に示した平面図、第2図
(a)は第1図の切断線で切断した状態を示す平面図、
(b)はそのA−A断面図、第3図は作用説明図、第4
図は本発明の他の実施例の模式的平面図、第5図は本発
明のさらに他の実施例側の模式的平面図、第6図は第5
図の切断線で切断した状態を示す斜視図、第7図は従来
のTAB式半導体装置の一例を模式的に示した平面図、
第8図(a)は第7図の切断線で切断した状態を示す平
面図、(b)はそのB−B断面図、第9図は第8図の半
導体装置を基板に実装した状態を示す断面図である。 (1):フィルム、(2):デバイスホール、(3):
リード、(3b): アウターリード、(4):アウタ
ーリードホール、(4a):第2のアウターリードホー
ル、(5):スプロケット穴、(8):半導体素子、(
7):切断線、 (8):タイバー (8a): 第2のタイバー (9):モールド材、 (11): 基板等、 (12): 導電パタ ーン。
FIG. 1 is a plan view schematically showing an embodiment of the present invention, FIG. 2(a) is a plan view showing a state cut along the cutting line of FIG. 1,
(b) is its A-A sectional view, Fig. 3 is an action explanatory diagram, and Fig. 4
The figure is a schematic plan view of another embodiment of the present invention, FIG. 5 is a schematic plan view of still another embodiment of the present invention, and FIG.
FIG. 7 is a perspective view showing a state cut along the cutting line in the figure; FIG. 7 is a plan view schematically showing an example of a conventional TAB type semiconductor device;
8(a) is a plan view taken along the cutting line in FIG. 7, FIG. 8(b) is a sectional view taken along line B-B, and FIG. 9 is a plan view showing the semiconductor device in FIG. 8 mounted on a board. FIG. (1): Film, (2): Device hole, (3):
Lead, (3b): Outer lead, (4): Outer lead hole, (4a): Second outer lead hole, (5): Sprocket hole, (8): Semiconductor element, (
7): cutting line, (8): tie bar (8a): second tie bar (9): molding material, (11): substrate etc., (12): conductive pattern.

Claims (1)

【特許請求の範囲】[Claims] 可撓性フィルムに設けたデバイスホールの少なくとも対
向する2辺の外側に多数のリードを保持するタイバーを
有し、前記デバイスホール内に配設された半導体素子の
電極に前記リードをそれぞれ接続してなるTAB式半導
体装置において、前記タイバーの外側にアウターリード
ホールを隔てて1本または2本以上のタイバーを設けた
ことを特徴とするTAB式半導体装置。
A device hole provided in the flexible film has a tie bar for holding a large number of leads on the outside of at least two opposing sides, and each of the leads is connected to an electrode of a semiconductor element arranged in the device hole. A TAB type semiconductor device characterized in that one or more tie bars are provided on the outside of the tie bar with an outer lead hole in between.
JP2272409A 1990-10-12 1990-10-12 TAB type semiconductor device Expired - Fee Related JP2833189B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2272409A JP2833189B2 (en) 1990-10-12 1990-10-12 TAB type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2272409A JP2833189B2 (en) 1990-10-12 1990-10-12 TAB type semiconductor device

Publications (2)

Publication Number Publication Date
JPH04148538A true JPH04148538A (en) 1992-05-21
JP2833189B2 JP2833189B2 (en) 1998-12-09

Family

ID=17513503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2272409A Expired - Fee Related JP2833189B2 (en) 1990-10-12 1990-10-12 TAB type semiconductor device

Country Status (1)

Country Link
JP (1) JP2833189B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1032221A (en) * 1996-07-12 1998-02-03 Nec Corp Printed wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1032221A (en) * 1996-07-12 1998-02-03 Nec Corp Printed wiring board
US5925445A (en) * 1996-07-12 1999-07-20 Nec Corporation Printed wiring board

Also Published As

Publication number Publication date
JP2833189B2 (en) 1998-12-09

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