JPH04148274A - Testing system for information processor - Google Patents

Abstract

PURPOSE:To make the capacity of an external storage device small by testing a vector arithmetic device by comparing an executed result compressed by an executed result compressing mechanism with the expected value of a compressed arithmetic result. CONSTITUTION:A testing program 11 initializes the vector arithmetic device by a preprocessing part 16 when started, and loaded a test instruction 12, test data 13 and a compressed expected value 14 from the external storage device in a main storage device. Next, the vector arithmetic device is started, and by adding the executed result in an executed result compressing part 15 at a word unit, the executed result is compressed to one word finally. And by adding preliminarily at the word unit similarly, the expected value 14 compressed to the one word and the executed result compressed to the one word are compared in a comparing part 17, and discriminating a normal/defective condition, the test of the vector arithmetic is executed. Thus, it is possible to make the capacity of the external storage device small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test method for an information processing device, and particularly to a test method for a vector arithmetic unit.

[Conventional technology]

Conventionally, this type of testing method has an expected value in an uncompressed form and performs the test by comparing the execution result with the expected value.

[Problem to be solved by the invention]

As mentioned above, conventional test methods have expected values in an uncompressed form, so especially when a large amount of test data and expected values are required, such as when testing vector arithmetic units, test data Another disadvantage is that the capacity of an external storage device for storing expected values becomes large.

In addition, in terms of test time, there is a drawback that it takes time to load test data and expected values, which takes up a large portion of the test time.

[Means to solve the problem]

A test method for an information processing device according to the present invention performs test control on a scalar arithmetic unit in an information processing device including a vector arithmetic unit and a scalar arithmetic unit, and uses one or more test commands for the vector arithmetic unit and this test command. In a test method for a vector arithmetic unit that has test data to be used and an expected value of the operation result, there is an execution result compression mechanism that compresses the execution result and an expectation that the expected value of the operation result is compressed in advance using the same algorithm as the execution result compression mechanism. The vector computing unit is tested by comparing the execution result compressed by the execution result compression mechanism with the expected value of the compressed operation result.

In addition, when a defect is detected, it has a simulation mechanism that simulates the test instruction with instructions on the scalar arithmetic unit, and calculates the correct value using the simulation mechanism.
A detailed analysis of the defect is performed by comparing this correct value with the execution result of the vector arithmetic unit.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a test program according to an embodiment of the present invention.
FIG. 2 is a block diagram of an embodiment of an information processing apparatus to which the test program shown in FIG. 1 is applied, and FIG. 3 is a flowchart outlining the operation of the test program shown in FIG. 1.

As shown in FIG. 1, the test program 11 of this embodiment includes test commands 12, test data 13, compressed expected values 1
4, an execution result compression section 15, a preprocessing section 16, and a comparison section 17.

Further, as shown in FIG. 2, the information processing device 21 to which the main test program 11 is applied includes a scalar arithmetic unit 22,
Vector calculator 23, system control device 24, main storage device 25, input/output control device 26, external storage device! It consists of 27.

Here, the operation of the test program 11 will be explained with reference to the drawings.

In FIG. 3, when the test program 11 is started, the preprocessing unit 16 initializes the vector arithmetic unit 23 (step 32), and stores the test command 12, test data 13, and compressed expected value 14 in the external storage device 27. from there to the main storage device 25 (step 33). Next, the vector calculator 23
is started (step 34), and the execution result is added word by word in the execution result compression section 15, thereby finally compressing the execution result into one word (step 35). Then, the comparison unit 17 compares the expected value 14, which has been compressed into one word by adding each word in advance, and the execution result, which has been compressed into one word, and tests the vector calculation 23 by determining whether it is good or bad. (Step 36).

FIG. 4 is a configuration diagram of a test program according to a second embodiment of the present invention, and FIG. 5 is a flowchart showing an outline of the operation of the test program of FIG.

As shown in FIG. 4, test program 4 of the second embodiment
1 includes a test command 42, test data 43, compressed expected value 44, execution result compression section 45, preprocessing section 46, comparison section 4
7. It is composed of a simulation section 48.

Here, the operation of the test program 41 will be explained with reference to the drawings.

In FIG. 5, when the test program 41 is started, the preprocessor 46 initializes the vector calculator 23 (step 52), and stores the test command 42, test data 43, and compressed expected value 44 in the external storage device 27. 0 to the main storage device 25 (step 53). Next, the vector arithmetic unit 23
is started (step 54), and the execution result is added word by word in the execution result compression section 45, thereby finally compressing the execution result into one word (step 55). Then, the comparison unit 47 compares the expected value 44, which has been compressed into one word by adding each word in advance, with the execution result, which has been compressed into one word, to determine whether it is good or bad (step 56).

In this way, the operations up to the comparison section 47 are similar to those of the test program 11.

When the comparator 47 detects a defect, the simulation unit 48, which is designed to simulate the operation of the vector arithmetic unit 23 with the instructions of the scalar arithmetic unit 22, uses the test instruction 42.
A correct value is obtained using the test data 43 and the correct value is compared and outputted with the execution results of the two vector computing units (step 57).

Further, the test program 11.41 can have a plurality of test commands, test data, and expected values, and can be repeatedly executed from loading to pass/fail determination.

〔Effect of the invention〕

As explained above, according to the present invention, the capacity of the external storage device can be reduced by compressing and retaining the expected value.

This is particularly effective in tests that require a large amount of test data and expected values, such as tests on vector arithmetic units.

Also, much of the test time is spent on test data from external devices,
This is necessary for loading expected values, and has the effect of shortening test time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a test program according to an embodiment of the present invention.
FIG. 2 is a block diagram of an embodiment of an information processing device to which the test program shown in FIG. 1 is applied; FIGS. This figure is a flowchart showing an outline of the operation of the test program of FIG. 4. 11.41...Test program, 12.42...Test command, 13.43...Test data, 14°44...
- Compressed expected value, 15.45... Execution result compression section, 16.46... Preprocessing section, 17.47... Comparison section, 21... Information processing device, 22... Scalar Arithmetic unit, 23... Vector computing unit, 24... System control device, 25... Main storage device, 26... Input/output control device, 27... External storage device, 48... Simulation section .

Claims (1)

[Claims] 1. Performing test control on the scalar arithmetic unit in an information processing device including a vector arithmetic unit and a scalar arithmetic unit,
In the test method for the vector computing unit, the vector computing unit has one or more test instructions for the vector computing unit, test data used in the test instructions, and an expected value of the computed result, comprising: an execution result compression mechanism that compresses the execution result; and the computing unit. The expected value of the result has an expected value compressed in advance using the same algorithm as the execution result compression mechanism, and the execution result compressed by the execution result compression mechanism is compared with the expected value of the compressed operation result. A test method for an information processing device, characterized in that the vector arithmetic unit is tested by: 2. The testing method for an information processing device according to claim 1, further comprising a simulation mechanism for simulating the test instruction with an instruction on a scalar arithmetic unit when a defect is detected, and calculating a correct value by the simulation mechanism; A testing method for an information processing device, characterized in that a detailed analysis of a defect is performed by comparing the correct value with an execution result of the vector arithmetic unit.