JPH04147648A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04147648A JPH04147648A JP27275590A JP27275590A JPH04147648A JP H04147648 A JPH04147648 A JP H04147648A JP 27275590 A JP27275590 A JP 27275590A JP 27275590 A JP27275590 A JP 27275590A JP H04147648 A JPH04147648 A JP H04147648A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon layer
- fuse
- semiconductor device
- fused
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 25
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 2
- 238000007664 blowing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に多結晶シリコン層から
な、るヒユーズを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a fuse made of a polycrystalline silicon layer.
従来、半導体装置に多結晶シリコン層からなるヒユーズ
を形成する場合は、単一の工程で平坦に形成された絶縁
酸化膜上に多結晶シリコン層を成長させ、この多結晶シ
リコン層をパターニングしてヒユーズとして用いていた
。このような多結晶シリコンをヒユーズとして形成した
半導体装置の例を第２図（ａ）、（ｂ）に示す。Conventionally, when forming a fuse made of a polycrystalline silicon layer in a semiconductor device, a polycrystalline silicon layer is grown on a flat insulating oxide film in a single process, and this polycrystalline silicon layer is patterned. It was used as a fuse. An example of a semiconductor device in which such polycrystalline silicon is used as a fuse is shown in FIGS. 2(a) and 2(b).
すなわち半導体基板１上に熱酸化によって形成された絶
縁酸化膜２上に多結晶シリコン層５Ａを形成したのちパ
ターニングしてヒユーズを形成し、さらにその上に眉間
絶縁膜３と耐酸化膜４を形成し、ヒユーズの溶断される
部分６Ａの層間絶縁膜３と耐酸化膜４を除去する。ヒユ
ーズの溶断される部分６Ａの多結晶シリコン層５Ａの層
抵抗の値をａ、幅をｂ、厚さをＣ１長さをｄとすると、
溶断される部分６Ａの抵抗値Ｒは（１）式で表わされる
。That is, a polycrystalline silicon layer 5A is formed on an insulating oxide film 2 formed by thermal oxidation on a semiconductor substrate 1, and then patterned to form a fuse, and then a glabella insulating film 3 and an oxidation-resistant film 4 are formed thereon. Then, the interlayer insulating film 3 and the oxidation-resistant film 4 in the portion 6A of the fuse to be blown are removed. Assuming that the value of the layer resistance of the polycrystalline silicon layer 5A in the portion 6A where the fuse is blown is a, the width is b, the thickness is C1, and the length is d.
The resistance value R of the portion 6A to be fused is expressed by equation (1).
ここで層抵抗ａ及び幅す及び長さｄが一定の値とすると
抵抗値Ｒは厚さＣに反比例する。Here, assuming that the layer resistance a, width and length d are constant values, the resistance value R is inversely proportional to the thickness C.
又、ヒユーズは電流によって切断されるため、オームの
法則から電流を■、電圧をＶ、抵抗をＲとすると（２）
式となる。Also, since fuses are cut by current, from Ohm's law, if current is ■, voltage is V, and resistance is R, then (2)
The formula becomes
■
Ｉ ＝ −−−（２）
ここで（１）式を（２）式に代入すると（３）式となし
たがってヒユーズは電流を多く流すことにより溶断され
るが、この構造では溶断される部分６Ａの多結晶シリコ
ン層５Ａの幅すにも限界があるため、溶断するには高い
電圧を必要とし、ヒユーズを確実に溶断するための障害
となっていた。■ I = ---(2) Here, substituting equation (1) into equation (2) yields equation (3). Therefore, the fuse is blown by flowing a large amount of current, but in this structure, the part that is blown is Since there is a limit to the width of the 6A polycrystalline silicon layer 5A, a high voltage is required to blow the fuse, which has been an obstacle to blowing the fuse reliably.
上述した従来の多結晶シリコン層からなるヒユーズ構造
では、ヒユーズの溶断される部分の抵抗値Ｒが低いので
、溶断する際、切れずにショートしていたり、又逆に高
い電圧を必要とする欠点がある。In the above-mentioned conventional fuse structure made of a polycrystalline silicon layer, the resistance value R of the part of the fuse that is blown is low, so when the fuse is blown, it does not break and short-circuits, or conversely, it requires a high voltage. There is.
本発明の目的は、ヒユーズとしての多結晶シリコン層に
電流を流して溶断する際、低い電圧で確実に溶断てきる
ヒユーズを得ることにある。An object of the present invention is to obtain a fuse that can be reliably blown at a low voltage when a current is passed through a polycrystalline silicon layer as a fuse to blow it.
本発明の半導体装置は、半導体基板上に設けられた多結
晶シリコン層からなるヒユーズを有する半導体装置にお
いて、前記ヒユーズの溶断される部分の多結晶シリコン
層の厚さが他の部分の多結晶シリコン層の厚さより薄く
形成されているものである。The semiconductor device of the present invention is a semiconductor device having a fuse made of a polycrystalline silicon layer provided on a semiconductor substrate, in which the thickness of the polycrystalline silicon layer in the part where the fuse is blown is the same as that of the polycrystalline silicon layer in other parts. It is formed thinner than the thickness of the layer.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.
第１図において、半導体基板１上には酸化膜２を介して
多結晶シリコン層５からなるヒユーズが形成されている
。そしてヒユーズの溶断される部分６を除いた部分に眉
間絶縁膜３および耐酸化膜４が形成されている。そして
特に、溶断される部分６の多結晶シリコン層は、他の部
分の多結晶シリコン層５よりも薄い構造になっている。In FIG. 1, a fuse made of a polycrystalline silicon layer 5 is formed on a semiconductor substrate 1 with an oxide film 2 interposed therebetween. A glabellar insulating film 3 and an oxidation-resistant film 4 are formed in the area other than the part 6 where the fuse is blown. In particular, the polycrystalline silicon layer in the portion 6 to be blown out has a thinner structure than the polycrystalline silicon layer 5 in other portions.
このように構成された本実施例によれば、従来例と同様
に溶断される部分６の多結晶シリコン層５の層抵抗をａ
、幅をｂ、長さをｄとし、厚さのみを前記従来の多結晶
シリコン６Ａの厚さＣとの差をｅとし、その抵抗値Ｒ５
を求めた場合（４）式又、従来と同様にヒユーズに流れ
る電流は（５）式又、電圧で表わすと（６）式となる。According to this embodiment configured in this way, the layer resistance of the polycrystalline silicon layer 5 in the portion 6 to be fused is set to a, similar to the conventional example.
, the width is b, the length is d, only the thickness is the difference from the thickness C of the conventional polycrystalline silicon 6A, e is the resistance value R5.
When the equation (4) is obtained, the current flowing through the fuse is expressed as the equation (5) as in the conventional case, and when expressed in terms of voltage, the equation (6) is obtained.
ここで従来と同じ電圧でヒユーズを切ろうとした場合、
式（６）より厚さ（ｃ−ｅ）の反比例分電流が多く流れ
るため、溶断される部分６の多結晶シリコン層５をより
確実に溶断することができ、本発明の目的を達成するこ
とができる。If you try to cut the fuse at the same voltage as before,
According to equation (6), since a large amount of current flows in inverse proportion to the thickness (c-e), the polycrystalline silicon layer 5 in the portion 6 to be fused can be fused more reliably, thereby achieving the object of the present invention. I can do it.
以上説明したように本発明は、多結晶シリコン層からな
るヒユーズの溶断される部分の多結晶シリコン層の厚さ
を他の多結晶シリコン層の厚さより薄くすることにより
、ヒユーズをより確実に溶断てきるという効果がある。As explained above, the present invention allows the fuse to be blown more reliably by making the thickness of the polycrystalline silicon layer at the part where the fuse made of the polycrystalline silicon layer is thinner than the thickness of the other polycrystalline silicon layers. It has the effect of making you feel better.
第１図は本発明の一実施例の断面図、第２図（ａ）、（
ｂ）は従来の半導体装置の平面図及び断面図である。
１・・・半導体基板、２・・・酸化膜、３・・・層間絶
縁膜、４・・・耐酸化膜、５，５Ａ・・・多結晶シリコ
ン層、６．６Ａ・・・溶断される部分。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2(a), (
b) is a plan view and a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 3... Interlayer insulating film, 4... Oxidation resistant film, 5,5A... Polycrystalline silicon layer, 6.6A... Fused out part.
Claims (1)
ヒューズを有する半導体装置において、前記ヒューズの
溶断される部分の多結晶シリコン層の厚さが他の部分の
多結晶シリコン層の厚さより薄く形成されていることを
特徴とする半導体装置。In a semiconductor device having a fuse made of a polycrystalline silicon layer provided on a semiconductor substrate, the thickness of the polycrystalline silicon layer in a portion of the fuse to be blown is formed to be thinner than the thickness of the polycrystalline silicon layer in other portions. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27275590A JPH04147648A (en) | 1990-10-11 | 1990-10-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27275590A JPH04147648A (en) | 1990-10-11 | 1990-10-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04147648A true JPH04147648A (en) | 1992-05-21 |
Family
ID=17518302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27275590A Pending JPH04147648A (en) | 1990-10-11 | 1990-10-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04147648A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007294961A (en) * | 2006-04-26 | 2007-11-08 | Samsung Electronics Co Ltd | Integrated fuse for low power application which is electrically programmable, and method for forming same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5954240A (en) * | 1982-09-21 | 1984-03-29 | Mitsubishi Electric Corp | Integrated circuit |
-
1990
- 1990-10-11 JP JP27275590A patent/JPH04147648A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5954240A (en) * | 1982-09-21 | 1984-03-29 | Mitsubishi Electric Corp | Integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007294961A (en) * | 2006-04-26 | 2007-11-08 | Samsung Electronics Co Ltd | Integrated fuse for low power application which is electrically programmable, and method for forming same |
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