JPH04146632A - Method of mounting semiconductor device - Google Patents
Method of mounting semiconductor deviceInfo
- Publication number
- JPH04146632A JPH04146632A JP2271265A JP27126590A JPH04146632A JP H04146632 A JPH04146632 A JP H04146632A JP 2271265 A JP2271265 A JP 2271265A JP 27126590 A JP27126590 A JP 27126590A JP H04146632 A JPH04146632 A JP H04146632A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrodes
- electrode
- interval
- circuit substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000002245 particle Substances 0.000 claims abstract description 20
- 239000003302 ferromagnetic material Substances 0.000 claims abstract description 8
- 239000000853 adhesive Substances 0.000 claims abstract description 7
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 230000005415 magnetization Effects 0.000 claims description 4
- 230000005291 magnetic effect Effects 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 2
- 238000007772 electroless plating Methods 0.000 abstract description 2
- 230000004907 flux Effects 0.000 abstract description 2
- 229910018104 Ni-P Inorganic materials 0.000 abstract 1
- 229910018536 Ni—P Inorganic materials 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052789 astatine Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- SIBIBHIFKSKVRR-UHFFFAOYSA-N phosphanylidynecobalt Chemical compound [Co]#P SIBIBHIFKSKVRR-UHFFFAOYSA-N 0.000 description 2
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000003984 copper intrauterine device Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置と回路基板とを電気的に接続する実
装方法に関し、磁気の吸引力を用いた実装方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mounting method for electrically connecting a semiconductor device and a circuit board, and more particularly to a mounting method using magnetic attractive force.
従来、半導体装置と回路基板とを接続する方法には、金
（Ａｕ）や銅（Ｃｔ＞やアルミニウム（Ａｔ）の細線で
アルミニウムのパッドとリードフレームを接続するワイ
ヤーボンディング法や、アルミニウムのパッド上へ金や
はんだを厚くめっきし、すず（Ｓｎ）めっきしたリード
テープに熱圧着スルテープオートメイテッドボンディン
グ（ＴＡＢ）法がある。Conventionally, methods for connecting semiconductor devices and circuit boards include wire bonding, which connects aluminum pads and lead frames with thin gold (Au), copper (Ct), or aluminum (At) wires, and wire bonding, which connects aluminum pads to lead frames. There is a through-tape automated bonding (TAB) method in which lead tape is thickly plated with metal or solder and then thermocompressed to a lead tape plated with tin (Sn).
しかしながら従来のワイヤーボンディングやＴＡＢは、
ＡｔとＡｕ、ＡｔとＯｕ、ＡｔとＡｔやＡｕとＳｎ、は
んだと３ｎなどの組み合せを外部加熱により熱拡散や融
解で接続するため、接続部分が変形し、狭い電極間隔の
半導体装置は電気特性上短絡しゃすい°とい５課題を有
した。However, conventional wire bonding and TAB
Because combinations such as At and Au, At and Ou, At and At, Au and Sn, and solder and 3N are connected by thermal diffusion and melting by external heating, the connected parts are deformed and the electrical characteristics of semiconductor devices with narrow electrode spacing deteriorate. There were five tasks, including short circuits.
本発明は以上の課題を解決するものでその目的は、熱拡
散や融解のメカニズムによらない方法で狭い電極間隔の
半導体装置を外部回路に接続する方法を提供するもので
ある。The present invention has been made to solve the above problems, and its purpose is to provide a method for connecting a semiconductor device with narrow electrode spacing to an external circuit by a method that does not rely on thermal diffusion or melting mechanisms.
本発明の半導体装置の実装方法は、半導体装置の電極と
回路基板の電極とを導電粒子の分散した膜又は接着剤に
より接続する実装方法において、半導体装置の電極又は
回路基板の電極又は導電粒子のいずれか二つ以上が強磁
性体で、且つ、半導体装置の電極又は回路基板の電極の
いずれか一つ以上着磁処理したものを用いて接続するこ
とを特徴とする。The semiconductor device mounting method of the present invention is a mounting method in which an electrode of a semiconductor device and an electrode of a circuit board are connected by a film or an adhesive in which conductive particles are dispersed. It is characterized in that at least two of them are made of ferromagnetic material, and that at least one of the electrodes of the semiconductor device or the electrodes of the circuit board is magnetized.
本発明の半導体装置の実装方法は、熱を加えずに磁気力
の吸引作用と導電粒子により電気的な接続を実現する方
法である。そのため実装する電極や導電粒子は、吸引す
るため２つ以上強磁性体で且つ、電極のどちらか１つ以
上が着磁させなければならない。もし強磁性体が１つで
あると、磁気作用が期待できない。さらに着磁していな
げれば、強磁性体同志が吸引することもない。また、導
電粒子が着磁していると、接続前に粒子間で吸引して結
合し、接続後電気的短絡が発生する。The semiconductor device mounting method of the present invention is a method of realizing electrical connection by the attraction effect of magnetic force and conductive particles without applying heat. Therefore, two or more of the electrodes and conductive particles to be mounted must be made of ferromagnetic material in order to attract them, and one or more of the electrodes must be magnetized. If there is only one ferromagnetic material, no magnetic effect can be expected. Furthermore, if it is not magnetized, ferromagnetic materials will not be attracted to each other. Furthermore, if the conductive particles are magnetized, the particles will be attracted to each other and bond together before connection, resulting in an electrical short circuit after connection.
以上の理由から、上蓮した磁性材料と着磁処理が必要な
のである。For the above reasons, a highly refined magnetic material and magnetization treatment are necessary.
また導電粒子は、基板や電極自身の厚みばらつきによる
電気的接続不良を防ぐため用いた。The conductive particles were also used to prevent electrical connection failures due to variations in the thickness of the substrate and electrodes themselves.
本発明の効果について、以下の実施例に基づいて説明す
る。The effects of the present invention will be explained based on the following examples.
（実施例１） 第１図は本実施例の実装の断面図である。(Example 1) FIG. 1 is a sectional view of the implementation of this embodiment.
第１図のようにルタイプけい素基板１に酸化けい素ＩＱ
を形成し、５０ｔｔｍＸ５Ｄｐｍ角、５０μｍ間隔に窒
化けい素３で分離したアルミニウム（Ａｔ）合金２と無
電解めっき法で選択的にニッケルーリン（Ｎｔ−ｐ）層
４と保磁力５００エルステツド、残留磁束密度１０００
０ガウスのコバルト・リン（ｃｏ−Ｐ）層５を合計約５
μｍ形成した半導体装置の電極と、銅６で配線した絶縁
基板７に選択的に２０μｍ間隔で約５μｍ前述のＣＯ・
２層５を形成した回路基板とを、樹脂粒子へ前述のＣｏ
−Ｐ層を形成した平均粒径約５μｍの導電粒子８を分散
させた紫外線硬化接着剤９を用い、第１表のような組み
合せで５０００エルステツドの磁場を使い着磁した。As shown in Fig. 1, silicon oxide IQ is applied to the silicon substrate
Aluminum (At) alloy 2 separated by silicon nitride 3 at 50ttm x 5Dpm square and 50μm intervals and nickel-phosphorus (Nt-p) layer 4 selectively formed by electroless plating with a coercive force of 500 oersted and residual magnetic flux density. 1000
A total of about 5 cobalt-phosphorus (co-P) layers of 0 Gauss
The electrodes of the semiconductor device formed in .mu.m and the insulating substrate 7 wired with copper 6 are selectively coated with about 5 .mu.m at intervals of 20 .mu.m.
The above-mentioned Co
-Using an ultraviolet curing adhesive 9 in which conductive particles 8 having an average particle diameter of about 5 μm and forming a P layer were dispersed, magnetization was performed using a magnetic field of 5000 oersted in combinations as shown in Table 1.
第 １ 表 但し、 試料２のみ電極同志が吸引するよ う着磁 した。Table 1 however, Only sample 2 will be suctioned by the electrodes. Magnetization did.
そして次に回路基板上へ半導体装置をのせ、フリップチ
ップボンディングした後、接着剤を硬化させ実装を完成
させた。Next, the semiconductor device was placed on the circuit board, flip-chip bonding was performed, and the adhesive was cured to complete the mounting.
実施例１０半導体装置の電極を非磁性のＮ１・Ｐ層まで
とした以外、実施例１と同様の回路基板と導電粒子を用
い、回路基板の電極のみ着磁したそしてフリップチップ
ボンディシグし、試料４とした。Example 10 The same circuit board and conductive particles as in Example 1 were used except that the electrodes of the semiconductor device were changed to the non-magnetic N1 and P layers. Only the electrodes of the circuit board were magnetized, and flip-chip bonding was performed to prepare the sample. It was set as 4.
（実施例６）
実施例１０回路基板の電極を非磁性金属とした以外、実
施例１と同様の半導体装置の電極と導電粒子を用い、半
導体装置の電極のみ着磁した。そしてフリップチップボ
ンディングし、試料５とした。(Example 6) Example 10 The same electrodes and conductive particles of a semiconductor device as in Example 1 were used except that the electrodes of the circuit board were made of non-magnetic metal, and only the electrodes of the semiconductor device were magnetized. Then, flip-chip bonding was performed to obtain sample 5.
（実施例４）
実施例１の導電粒子を非磁性の金属で被覆した以外、実
施例１と同様の半導体装置の電極と回路基板の電極を用
い第２表のような組み合せで着磁し、フリップチップボ
ンディング実装した。(Example 4) The conductive particles of Example 1 were coated with a non-magnetic metal, but the same semiconductor device electrodes and circuit board electrodes as in Example 1 were used to magnetize them in the combinations shown in Table 2. Implemented flip chip bonding.
但し試料７のみ電極同志が吸ジ１するよう着磁した。However, only sample 7 was magnetized so that the electrodes were attracted to each other.
第
表
（比較例１）
実施例１の各電極と導電粒子を着磁せず、フリップチッ
プ実装した。Table 1 (Comparative Example 1) The electrodes and conductive particles of Example 1 were not magnetized and were flip-chip mounted.
（比較例２）
実施例１の導電粒子を着磁させ、フリップチップ実装し
た。(Comparative Example 2) The conductive particles of Example 1 were magnetized and flip-chip mounted.
（比較例５）
実施例１の回路基板の電極と導電粒子を非磁性のＮ１−
Ｐめっきに変更した以外、半導体装置の電極を着磁して
実施例１と同様の方法によりフリップチップ実装した。(Comparative Example 5) The electrodes and conductive particles of the circuit board of Example 1 were replaced with non-magnetic N1-
The electrodes of the semiconductor device were magnetized and flip-chip mounted in the same manner as in Example 1, except that the plating was changed to P plating.
以上実施例１から４の試料１から８と比較例１から３の
実装品の電気特性を調べ実装状態を評価した。その結果
、試料１から８は良好な接続であったが、比較例１と５
は電気的に接続されていない部分が現われ、比較例２は
電極間が短絡するという問題を発生させた。The electrical characteristics of the mounted products of Samples 1 to 8 of Examples 1 to 4 and Comparative Examples 1 to 3 were examined and the mounting state was evaluated. As a result, samples 1 to 8 had good connections, but comparative examples 1 and 5
In Comparative Example 2, there appeared a portion that was not electrically connected, and a problem occurred in which the electrodes were short-circuited.
尚、本実施例以外にも半導体装置の電極や回路基板の電
極や導電粒子の構成が、表面に強磁性体をこれらの電極
等の二つ以上に形成していれば、膜厚や組成が変わって
も効果に変わりがなかつたまたフリップチップボンディ
ングを、導電粒子を分散させた膜や紫外線硬化材料以外
の接着剤に分散させたものを使用しても、効果に変わり
がなかった。In addition to this example, if the structure of the electrodes of a semiconductor device, the electrodes of a circuit board, or the conductive particles has a ferromagnetic material formed on the surface of two or more of these electrodes, the film thickness and composition may vary. There was no change in effectiveness even when flip-chip bonding was used with a film in which conductive particles were dispersed or in an adhesive other than an ultraviolet curing material.
以上述べたように、本発明は強磁性体の形成とその着磁
により、狭い電極間隔でも半導体装置を電気的に実装で
き、しかも磁力により半導体装置と回路基板の電極が若
干ずれても、接続できるという効果を有する。As described above, by forming a ferromagnetic material and magnetizing it, the present invention enables semiconductor devices to be electrically mounted even with narrow electrode spacing, and even if the electrodes of the semiconductor device and the circuit board are slightly misaligned due to magnetic force, the connection can be maintained. It has the effect of being able to.
第１図は本発明の実施例に示した実装の断面図である。
１・・・・・・・・・ｎタイプけい素基板２・・・・・
・・・・アルミニウム合金６・・・・・・・・・窒化け
い素
４・・・・・・・・・ニッケル・リン層５・・・・・・
・・・コバルト・リン層６・・・・・・・・・銅
７・・・・・・・・・絶縁基板
８・−・・・・・・・導電粒子
９・・・・・・・・・紫外線硬化接着剤１０・・・・・
・・・・酸化けい素
以上
出願人 セイコーエプソン株式会社FIG. 1 is a sectional view of a mounting shown in an embodiment of the present invention. 1...N-type silicon substrate 2...
...Aluminum alloy 6...Silicon nitride 4...Nickel phosphorous layer 5...
Cobalt/phosphorus layer 6 Copper 7 Insulating substrate 8 Conductive particles 9・・UV curing adhesive 10・・・・
...Silicon oxide and above Applicant Seiko Epson Corporation
Claims (1)
散した膜又は接着剤により接続する実装方法において、
半導体装置の電極又は回路基板の電極又は導電粒子のい
ずれか二つ以上の表面が強磁性体に覆われ、且つ、半導
体装置の電極又は回路基板の電極のいずれか一つ以上着
磁処理したものを用いて接続することを特徴とする半導
体装置の実装方法。In a mounting method that connects an electrode of a semiconductor device and an electrode of a circuit board using a film or adhesive in which conductive particles are dispersed,
The surfaces of two or more of the electrodes of the semiconductor device, the electrodes of the circuit board, or conductive particles are covered with a ferromagnetic material, and one or more of the electrodes of the semiconductor device or the electrodes of the circuit board are subjected to magnetization treatment. 1. A method for mounting a semiconductor device, characterized in that connection is made using a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2271265A JPH04146632A (en) | 1990-10-09 | 1990-10-09 | Method of mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2271265A JPH04146632A (en) | 1990-10-09 | 1990-10-09 | Method of mounting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04146632A true JPH04146632A (en) | 1992-05-20 |
Family
ID=17497673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2271265A Pending JPH04146632A (en) | 1990-10-09 | 1990-10-09 | Method of mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04146632A (en) |
-
1990
- 1990-10-09 JP JP2271265A patent/JPH04146632A/en active Pending
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