JPH04145656A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To simplify steps, to improve yield and to prevent disconnection of an aluminum electrode by burying metal in an opening formed at one end of a high resistance film by a selective CVD method, and forming a power source wiring part of a resistance element. CONSTITUTION:An element isolating oxide film 2, etc., are sequentially formed on a silicon substrate 1, covered with an interlayer film 10, and then an opening 11 is opened on one end of a high resistance film 9 by photoetching. In this case, the part of the film 9 is run under a part to become a power source wiring part, and the opening 11 becomes like a groove along the part. A tungsten electrode 12 is buried in thickness substantially equal to that of the film 10 in the opening 11 by a selective tungsten CVD method. Then, an interlayer film 13, an aluminum electrode 14 are formed. Thus, a photoetching step is eliminated, and steps are simplified, and hence yield is improved, and the wiring part is buried in the groove. Therefore, its flatness is improved, and disconnection of the electrode 14 due to the step can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to the structure and manufacturing method of an SRAM memory cell.

[Conventional technology]

Integrated circuits formed on semiconductor substrates, especially silicon substrates, are becoming increasingly dense and large in capacity.In particular, the density of integrated circuits such as semiconductor memory devices is increasing to 4M, 16M bits, or more. ing. In large-scale integrated circuits, it is necessary to form many elements on one chip, but from the viewpoint of yield and cost, it is necessary to make the area of one chip as small as possible. To meet the demands of these three parties, 1.
The most effective method is to reduce the area per element.

In a static RAM (SRAM), a memory cell has two drive MO3 transistors 17a and 17b and two transfer MOS transistors 1 as shown in FIG.
A system consisting of 8a, 18b and two resistive elements 19a, 19b is suitable for such a large capacity and is the mainstream. For example, the area of 1 cell is 20
The length of the resistance element must be approximately 2 μm. As the resistance element becomes microscopic in this way, the structure and formation method of the power supply wiring section becomes a problem.

Generally, high-resistance polysilicon has been used for resistance elements in SRAMs. One end of this high-resistance polysilicon is connected to the gate electrode of the driving MOS transistor, and impurities are diffused into the polysilicon from the gate electrode, and the other end is used as a power supply wiring part where impurities of 1019 to 10210 are connected.
It is doped with a concentration of 2O'. When a voltage is applied, a depletion layer extends into the high-resistance polysilicon from both ends, but as the length of the high-resistance polysilicon becomes shorter, these depletion layers begin to overlap each other, causing an excessive current to flow and the so-called punch-through phenomenon. I end up.

Furthermore, when impurities are introduced into the power supply wiring portion by ion implantation, there is a problem that if the impurity is implanted at a high dose, the dielectric breakdown voltage of the gate oxide film becomes defective due to charge-up.

Furthermore, in order to keep the standby current of SRAM low, a material with higher resistance than polysilicon, such as S I PO3 (Semi In
If a high-resistance material such as sulating poly 5 ilicon is used, the resistance of the power supply wiring portion may not be reduced sufficiently by doping with impurities. If the resistance becomes close to that of the resistive element, the power supply voltage of the cell section will drop due to the potential drop in the power supply wiring section, and the high-level potential of the node will also become low, making the operation of the cell unstable.

Fig. 4 shows a conventional method for solving these problems. Fig. 4 (A) is a cross-sectional view showing an SRAM memory cell according to the conventional technology, and Fig. 4 (B) shows its resistance element and power supply wiring section. This is a plan layout diagram, and FIG. 4(A) is the same as FIG. 4(B).
It corresponds to a cross section along nn' of . The structure will be explained in correspondence with the circuit diagram of FIG.

In FIG. 4(A), a driving MO5t-
A gate electrode 5 corresponding to the gate of the Lat-ran jitter (or 17b) is also provided on the surface of the silicon substrate 1 for transfer.
A diffusion layer 6 corresponding to the diffusion layer of the OS transistor 18b (or 18a) is formed, and a high-resistance film 9 corresponding to the resistance element 19b (or 19a) is formed thereon with a glabella film 7 interposed therebetween. The diffusion layer 6 and the gate electrode 5 are connected through the connection hole 4, and the gate electrode 5 and the high resistance film 9 are connected through the connection hole 8, forming a node 20b (or 20a). The high resistance film 9 is covered with an interlayer film 10, and an opening 11 is opened above one end of the high resistance film 9. A silicide electrode 16 runs on it, and is connected to the high resistance film 9 through the opening 11, and resistive elements 19a, 1 as shown in FIG. 4(B).
9b (corresponds to the power supply 21 in FIG. 5). Furthermore, an aluminum electrode 14 is formed thereon with an interlayer film 13 interposed therebetween.

Next, a method of manufacturing the SRAM memory cell as described above will be explained. Although an N-channel type memory will be described here, a P-channel type memory cell can also be formed in exactly the same way, and the impurity types may be replaced by P for N and N for P. This also applies to later embodiments.

First, a device isolation oxide film 2 with a thickness of 300 to 10,000 m is formed on the surface of a P-type silicon substrate l using the well-known LOCO8 process.
A gate oxide film 3 with a thickness of 5 to 1100 nm was formed, and a contact hole 4 was opened by photoetching. After that, tungsten polycide is deposited to a thickness of 200 to 500 nm, and arsenic atoms are deposited to a thickness of 1015 to 1016 cm to form an N-type diffusion layer 6 that will become the source and train of the 8th order MOS transistor. After ion implantation at a dose of 2 and annealing in a nitrogen atmosphere,
As the glabellar membrane 7, 50 to 5000 m of SiO2 film is deposited by the well-known LPGVD method. Furthermore, a contact hole 8 is opened by photoetching, and a high resistance film 9 such as polysilicon or S I POS is formed by LPCVD.
After depositing 00 nm and patterning by photoetching, an Si 02 film having a thickness of 50 to 500 nm is deposited thereon as an interlayer film 10 by LPCVD.

Next, an opening 11 is formed on one end of the high-resistance film 9 by photoetching, and tungsten silicide is deposited thereon to a thickness of 100 to 500 nm by sputtering, and a silicide electrode 16 is formed by patterning by photoetching. And 4mo 1 by CVD method
A glabellar membrane 13 such as a PSG membrane containing 10% of phosphorus is coated with a thickness of 100%.
.about.11,000 nm is deposited, aluminum containing St is deposited, and the aluminum electrode 14 is formed by patterning by photoetching to form the structure shown in FIG. 4(A).

According to the structure and manufacturing method described above, since the power supply wiring section is not doped with impurities, the punch-through phenomenon is suppressed, charge-up does not occur, and even if the resistance value of the resistor element becomes high, the power supply wiring section is not doped with impurities. resistance can be lowered.

[Problem to be solved by the invention]

The conventional power supply wiring structure and formation method of the resistor element described above requires a photoetching process of the silicide electrode.
The increase in the number of steps causes a decrease in yield, and since the flatness after forming the power supply wiring section is also poor, there is also the problem that it becomes a source of disconnection, etc. when forming the aluminum wiring.

[Means to solve the problem]

In the SRAM memory cell of the present invention, an insulating film covering a resistance element whose one end is connected to the gate of a driving MOS transistor has an opening above the other end of the resistance element, and the opening is filled with metal by selective CVD. It has a structure in which it serves as a power supply wiring part for the resistance element, and also includes a step of forming an opening on one end of the resistance element in an insulating film covering the resistance element, and a selective CVD method for forming the opening. and embedding metal to form a power supply wiring portion of the resistance element.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(A) is a cross-sectional view of an SRAM memory cell according to the first embodiment of the present invention, FIG. 1(B) is a plan layout diagram of a resistive element and a power supply wiring section, and FIG. Figure 1 (B
) shows a cross section along I-1'. First, Figure 1 (
The structure of this SRAM memory cell will be explained using A) and (B).

The structure is basically the same as that shown in the conventional technology. However, in the conventional technique, a silicide electrode is formed by photoetching to cover the opening 11, whereas in this embodiment, the opening 11 is filled with a tungsten electrode formed by selective CVD. No, and because of selective CVD, a part of the high-resistance film 9 runs under the portion that will become the power supply wiring section, as shown in FIG. 1(B).

Next, the manufacturing method of the first embodiment of the present invention will be explained with reference to FIG. First, layers up to the interlayer film 10 are deposited in the same manner as in the conventional technique [FIG. 2(A)]. Next, an opening 11 is formed on one end of the high resistance film 9 by photoetching. At this time, as shown in FIG. 1(B), a part of the high-resistance film 9 runs under the part that will become the power wiring part, and the opening 11 is shaped like a groove along that part. Figure (B)]. Then, a well-known selective tungsten CVD method is applied to the opening 11.
Interlayer Ji! Tungsten T& to the same thickness as 10
12 is embedded [FIG. 2(C):] After that, a glabellar membrane 13 and an aluminum electrode 14 are formed in the same manner as in the conventional technique, thereby partially completing the structure shown in FIG. 1(A).

In this embodiment, since the power supply wiring portion can be formed only by a selective CVD process, a photoetching process as in the conventional technique is not required. Furthermore, as can be seen by comparing FIG. 1(A) and FIG. 4(A), this embodiment has superior flatness than the conventional one. Since the height is 100 to 500 nm, a step is created by this amount, whereas in this embodiment, the step in the power supply wiring portion is almost 0, and the disconnection of the aluminum wiring in this portion can be almost zero.

Next, a second embodiment of the present invention will be described. This embodiment is characterized in that the interlayer film on the high resistance film 9 is flattened. The structure is almost the same as the first embodiment, but the interlayer film 1
0, an interlayer film 15 consisting of two layers, an SiO2 film that prevents impurities from the PSG film from diffusing into the high resistance film 9, and a PSG film is used, and the glabellar film 15 is flattened. .

The manufacturing method of this example will be explained with reference to FIG. First, in the same manner as in the first embodiment, up to the high resistance film 9 is formed, and then a 5i0 film with a thickness of 50 to 2000 m is formed by LPCVD.
2 film and thickness 1 containing 4m01% phosphorus by CVD method.
An interlayer film 15 consisting of two layers with a PSG film of 00 to 11000 nm is deposited [FIG. 3(A)]. After that, 900～
A known glue flow is performed at 1000° C., and the glabellar membrane 15 is flattened by a combination of etching back and the like [FIG. 3(B)]. Then, in the same manner as in the first embodiment, the opening 11
3(C)], tungsten electrode 12 is buried by selective CVD (FIG. 3(D)), and interlayer film 13 is deposited to form aluminum electrode 14.

In this embodiment, the number of steps is slightly increased due to planarization, but since it is added to selective CVD filling, which originally has good flatness, the flatness is very excellent.

〔Effect of the invention〕

As described above, according to the present invention, selective CVD is used to form the power supply wiring portion of the resistance element, so the photoetching process is not required, the process can be simplified, and the yield can be improved. Furthermore, since the power supply wiring portion is embedded in the groove, it has good flatness and has the effect of preventing disconnection of the aluminum electrode due to differences in level.

[Brief explanation of drawings]

FIG. 1(A) is a cross-sectional view showing a first embodiment of the present invention, FIG. 1(B) is a plan layout diagram of a resistor element and power supply wiring section of the first embodiment of the present invention, and FIG. (A), (B), (
C) is a cross-sectional view showing the manufacturing method of the first embodiment of the present invention, and FIGS.
FIG. 4(A) is a cross-sectional view of a conventional semiconductor memory device, and FIG. 4(B) is a planar layout diagram of a resistive element and a power supply wiring portion of a conventional semiconductor memory device. , FIG. 5 is an S diagram for explaining the present invention and the prior art.
FIG. 2 is a circuit diagram of a RAM memory cell. 1... Silicon substrate, 2... Element isolation oxide film, 3.
...Gate oxide film, 4, 8... Connection hole, 5... Gate electrode 6... Diffusion layer, 7, 10, 13.15... Interlayer film, 9... High resistance film, 11 ...Opening, 12...
・Tungsten electrode, 16... Silicide electrode, 17
a, 17b...drive MOS) transistor, 18a,
18b...Transfer MOS transistor, 19a, 19
b...resistance element, 20 a. 0b...Node, 1...Power supply.

Claims (1)

[Claims] 1. Two driving MOS transistors formed on a semiconductor substrate and two transfer MOS transistors connected to their drains.
In a semiconductor memory device consisting of a static memory cell having an OS transistor and two resistance elements, an insulating film covering a resistance element connected to a gate of a driving MOS transistor has an opening above one end of the resistance element. . A semiconductor memory device, wherein the opening is filled with a metal electrode formed by a selective CVD method, and the metal electrode forms a power supply wiring portion of a resistive element. 2. Forming an opening on one end of the resistance element in an insulating film covering the resistance element, and filling the opening with metal by selective CVD to form the electrode wiring part. 2. The method of manufacturing a semiconductor memory device according to claim 1.