JPH04144432A - Interface circuit - Google Patents

Abstract

PURPOSE:To maintain the safe operation of the whole system by selecting one of plural inputted measured results based upon majority, and when all the measured results are mutually different, selecting a previously determined value and setting up the selected value on a specific position of a transmission frame to inform the value to a counter station. CONSTITUTION:An error in a receiving frame transmitted by a demapping circuit 12 is measured, at least three measured results obtained by the circuit 12 are inputted by a demapping circuit 13 with an interval shorter than the one-frame period of a transmission frame, one of the inputted measured results is selected based upon majority, and when all the inputted measured results are mutually different, the previously determined value is selected, the selected value is set up on a specific position of a frame to be transmitted to inform the value to the counter station. Even in the case of an asynchronous: operation, mistransfer for a far end bit error(FEBE) is not generated and the safe operation of the whole system can be maintained.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to an interface circuit in a terminal device used in a new synchronous network (hereinafter referred to as 5ONET).

(Prior Art) A 5ONET interface circuit which uses a hierarchical signal of an existing digital system 3 (hereinafter referred to as DS3) as a tributary is configured as shown in FIG.

In FIG. 3, 11 is a DS3 analog input interface circuit, which includes AGC, equalization, ternary discrimination, and B3ZS decoder. 12 is a demapping (hereinafter referred to as DMAP) circuit, and 13 is a pine pink (hereinafter referred to as MAP) circuit.
Circuit 14 is a Ds3 analog output interface circuit, which includes a B3ZS coder and a coaxial driver. still,
FIG. 4 shows the 5TS-1 frame structure of 5ONET handled here.

A DS3 signal (IN) input from an external DS3 device is input to N by the DS3 analog input interface 11.
It is converted into an RZ signal, and is converted into 5TS- by the MAP circuit 13.
It is placed in one frame and sent to the multiplexer (OU
T).

On the other hand, the 5TS-1 received signal (
IN) is a DMAP circuit] DS3 information is separated on the circuit 2 and sent to a coaxial cable by a DS3 analog output interface 14 (OUT). At this time, the DMA
The P circuit 12 receives the received 5TS-1 frame B I P (
Bit Interleaved Parity) - 8, detects and counts errors between it and the 83 bytes in the next frame, and encodes it in binary, F E B E
(Par End Bit Error) Outputs a frame every 4 bits.

The MAPN path 13 inputs the FEBE processed and output by the DMAP circuit 12, and receives the 4 bits from the first to fourth bits from the G] byte in the path overhead of the transmission frame.
Bits are used to notify the other station of the status of the sending path.

Here, the receiving and passing portion of FEBH between the MAP circuit 13 and the DMAP circuit 12 in the conventional 5ONET interface circuit will be explained using FIG.

121 is a FEBE processing unit in the DMAP circuit 12;
] 31 is the FEBE input section in the MAP circuit 13;
32 is a FEBE frame insertion section within the MAP circuit 13.

DMAP circuit 12 outputs a 4-bit FEBE signal. Since the data rate of FEBE is equal to 5 ONET frames, it is every 125 μs. FEB in MAP circuit 13
The E input section 131 is composed of four D type flops, stores the input FEBE data at the beginning of the transmission frame, and inserts the data prepared by the FEBE input section 131 into the FEBE insertion section at the timing of the 01 byte of the STS frame. 132, it is inserted (overridden) into the frame.

6 shows the timing of the operation of the circuit shown in FIG. 3. FIG. 6(a) shows the FEBE output of the DMAP circuit 12, FIG. 6(b) shows the frame pulse of the MAP circuit 13, and FIG. (C) shows the FEBE data taken into the MAP circuit]3.

As shown in Figure 6, when FEBE is delivered,
There is no particular problem if the entire transmission system in which this circuit is used is operated in network synchronization.

That is, in FIG. 3, the phase difference between the FEBE change point of the output of the DMAP circuit 12 and the beginning of the transmission frame (rising edge of FPS) maintains a constant value.

However, in the case of a station that is unable to perform network synchronization due to problems with its synchronization device, etc., the station must use a clock independent of its own synchronization network to overcome the emergency in order to minimize the impact on transmission equipment. However, in this case, the clock on the transmitting side and the clock on the receiving side are asynchronous.

For example, assume that the clock frequency of the transmitter f, j is 1 ol earlier than the frequency of the receiver (+j). The series of FEBE timing relationships shown in Figure 6 are not constant, but
It changes from time to time. That is, as shown in FIGS. 7(a) to 7(C), the frame head position (rising edge of FSP) of the MAP circuit 13 is brought forward. FIG. 8 shows the timing when this timing is located near the FEBE change point. This also shows the unevenness (skew) in the manual timing of FEBE.

At the timing shown in FIG. 8, if the DMAP circuit 12 originally alternated between FEBE values of 7 (0111 in binary) and 8 (1000 in binary) for each frame, the MAP circuit 13 sets them to 0 (0000 in binary)
or 1 (0001 in binary). Furthermore, the FEEE of the output of the DMAP circuit 12
The length of the uneven part of the 4-bit change (skew) is 10
If it is 0 ns, the FEBE value cannot be accurately transmitted due to the 10 ppm speed difference between the asynchronous clocks, which will impede the safe operation of the entire system.

(Problems to be Solved by the Invention) As described above, in the case of asynchronous operation, in the conventional interface circuit, the FEBE value is inaccurately passed, which may impede the safe operation of the entire system. Ta.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an interface circuit that can receive and receive FEBE without mistakes even in asynchronous operation, and can maintain safe operation of the entire system.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention provides a bidirectional interface circuit for inputting and outputting tributary signals built in a digital multiplex transmission device, in which the tributary input signal a mapping circuit for placing a tributary signal on a transmission frame of the digital multiplex transmission device, and a demapping circuit for unloading a tributary signal from a transmission frame from the game, and the demapping circuit measures and outputs an error in a transmitted received frame. Equipped with
The mapping circuit includes a means for capturing the measurement results of the demapping circuit at least three times at intervals shorter than one frame period of the transmission frame, and a means for selecting one of the measurement results captured by this means by majority vote; The present invention is characterized by comprising means for selecting one predetermined value when all the results are different, and notifying the opponent by placing it at a specific position in the frame to be transmitted.

(Function) In the interface circuit having the above configuration, the demapping circuit measures errors in the received frame transmitted, and the mapping circuit measures the measurement results obtained by the demapping circuit at least three times at intervals shorter than one frame period of the transmission frame. One of the imported measurement results is selected by majority vote, and if all the imported measurement results are different, one predetermined value is selected and placed at a specific position in the frame to be transmitted. I'm trying to let the game know.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the FEBE manual section in the MAP circuit used in the interface circuit according to the present invention.
lb and IC are 4-bit memories, 2 is a memory timing generator, and 3 is a majority selection section.

The memory timing generator 2 generates a write control signal to sequentially write FEBE into the memories 1a to 1c three times per frame in synchronization with the transmission frame.

The timing of these three times is at equal intervals, for example, 5ONE
This is the start timing of the A1°Hl and D7 bytes of the section overhead of T.

In other words, the FEBE value is stored in the first memory 1 at timing A1.
a, it is stored in the second memory 1b at H1 timing and in the third memory IC at D7 timing. In this way the first
When the FEBE value is stored in each of the third memories 1a to 1c, a read control signal is output from the memory timing generator 2, and the stored contents are read from each of the memories 18 to 1c.

The majority selection unit 3 compares the contents of the memories 1a to 1c and, if all three are equal, sets the value as the transmission FEEB value.

Among the contents of the memories 1a to 1c, if two memory contents are equal and one is different, the two equal memory contents are taken as the transmission FEBE value.

If the contents of the memories 1a to 1c are all different, the contents of the first memory 1a are set as the transmission FEBE value.

The operation of the above configuration will be described below with reference to FIG.

Now, suppose that the FEBE value is read at the timing shown in FIG. 2(a). Frame t, i+1°i+2. i+3.
... are A, B, C, D, respectively, and the periods j, j+1 . . . shown in FIG. j+2゜j+3. ... three times each at equal intervals (memory la.

The write order of lb and lc is a, b, and c), write and read control is performed, and input to the majority selection section 3.

In the majority selection unit 3, a writing error occurs at timing C of period j since it corresponds to a frame switching period, but at timing b and C, value A of frame i is normally written. Therefore, as shown in FIG. 2(C), A is selected and output by majority vote.

At timing C in period j+1, it corresponds to frame l, and b
, C timing corresponds to frame i+l, so the value B of frame i+1 is selectively output as shown in FIG. 2(C).

At timing C of period i+2, the value B of frame i+1 is set, and at timing b, the error value is set because it is in an unstable state.
Since the value C of frame i+2 is taken in at the C timing, the value B at the first C timing is selectively output.

At timing C in period j+3, the value C of frame i→-2
At timing b, the error value is taken in because it is in an unstable state, and at timing C, the value of frame i+2 is taken in, so the value C at the first timing C is selected and output. Thereafter, output values are selected by taking majority vote in the same manner.

That is, normally, the contents of at least two or more memories match, and if all three are different, this means that the data has been read incorrectly. In such a case, by selecting the readout output of the memory 1a, it is possible to avoid reading erroneous data.

Therefore, the interface circuit with the above configuration is
Even in asynchronous operation, receiving the FEBE signal can eliminate transmission errors.

In the above embodiment, the extraction of the FEBE signal is performed in frame 3.
However, the present invention is not limited to this, and it goes without saying that more extraction circuits may be set to take majority decision.

[Effects of the invention] As described above, according to this invention, even in asynchronous operation, FEB
The E receiver can provide an interface circuit that is error-free and maintains safe operation of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the configuration of the FEBE manual section in the MAP circuit as an embodiment of the interface circuit according to the present invention, FIG. 2 is a timing diagram for explaining the operation of the embodiment, and FIG. The figure is a block circuit diagram showing the configuration of a conventional 5ONET interface circuit, FIG. 4 is a block diagram showing the configuration of the 5TS-1 frame of the 5ONET, and FIG. 5 is a block diagram showing the configuration of the 5ONET 5TS-1 frame. FIG. 3 is a timing diagram for explaining the operation. la, lb, lc...4-bit memory, 2...memory timing generator, 3...majority selection section, 11...
・DS3 analog input interface circuit, 12...
・DMAP circuit, 13...MAP circuit, 14...D
S3 analog output interface circuit. Applicant's agent Patent attorney Suzue Takehiko r→ θ ← θ tsu trouble −

Claims (1)

[Scope of Claim] A bidirectional interface circuit for inputting and outputting tributary signals built into a digital multiplex transmission device, comprising: a mapping circuit for placing the tributary input signal on a transmission frame of the digital multiplex transmission device; a demapping circuit that lowers a tributary signal from a frame, the demapping circuit includes means for measuring and outputting an error in a transmitted received frame, and the mapping circuit applies the measurement result of the demapping circuit to a transmitted frame. 1
A means of capturing at least three times at intervals shorter than the frame period, and selecting one of the measurement results captured by this means by majority vote, and selecting one predetermined value if the captured measurement results are all different. and a means for notifying a game player of the information by placing it on a specific position of a frame to be transmitted.