JPH04144263A - Lead frame and manufacture thereof - Google Patents
Lead frame and manufacture thereofInfo
- Publication number
- JPH04144263A JPH04144263A JP26806190A JP26806190A JPH04144263A JP H04144263 A JPH04144263 A JP H04144263A JP 26806190 A JP26806190 A JP 26806190A JP 26806190 A JP26806190 A JP 26806190A JP H04144263 A JPH04144263 A JP H04144263A
- Authority
- JP
- Japan
- Prior art keywords
- parts
- solder
- lead frame
- groove
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 14
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路を実装するリードフレーム、特
に、ビン数の多いリードフレームの構造と製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for mounting a semiconductor integrated circuit, and particularly to a structure and manufacturing method of a lead frame with a large number of bins.
［従来の技術］
従来のリードフレームは、４２合金（Ｎ ｉ ４２重量
％、Ｆｅ残）に代表される鉄系合金やリン青銅に代表さ
れる銅系合金などの金属板７をプレス法、すなわち、所
望のパターンを有する金型でプレス加工するか、あるい
は、エツチング法、すなわち、上記金属板７上にフォト
レジスト８をコーティングし、所望のパターンを有する
マスクを用いて、露光、現像を行い、フォトレジスト膜
８をパターン化した後、塩化第二鉄液等のエツチング液
にて、腐食させることにより製造していた。[Prior Art] A conventional lead frame is manufactured by pressing a metal plate 7 made of an iron-based alloy such as 42 alloy (N i 42% by weight, Fe balance) or a copper-based alloy such as phosphor bronze. , by press working with a mold having a desired pattern, or by etching, that is, by coating the photoresist 8 on the metal plate 7, exposing and developing using a mask having a desired pattern, After patterning the photoresist film 8, it was manufactured by etching it with an etching solution such as ferric chloride solution.
半導体集積回路、特に特定用途向は半導体集積回路のよ
うな多機能を有する半導体集積回路の分野では、端子数
が増加する傾向にある。これに対し、半導体集積回路の
チップでは、高集積化が望まれ、サイズ面での制約を受
けている。このため、端子のピッチを狭くせざるをえな
い方向にある。2. Description of the Related Art In the field of semiconductor integrated circuits, especially semiconductor integrated circuits having multiple functions such as semiconductor integrated circuits for specific applications, the number of terminals tends to increase. On the other hand, semiconductor integrated circuit chips are desired to be highly integrated and are subject to size constraints. For this reason, the pitch of the terminals has to be narrowed.
このように、半導体集積回路の多端子化、ならびに、そ
の端子間の狭ピッチ化が進むにつれて、それに対応する
リードフレームの多ビン化、インナーリード部３および
アウターリード部２の狭ピッチ化の要求が高まっている
。As described above, as the number of terminals of semiconductor integrated circuits and the pitch between the terminals become narrower, there is a corresponding demand for a lead frame with a larger number of bins and a narrower pitch between the inner lead part 3 and the outer lead part 2. is increasing.
一方、多ピンリードフレームを用いた半導体集積回路の
実装はプリント回路基板５上に設けた端子６表面にはん
だ付けする、いわゆる、表面実装法が一般的である。は
んだ付は法としては、はんだペーストを塗布し、加熱溶
融させる方式が採用されている。しかし、アウターリー
ド２のピッチが狭くなるにつれて、それに対応するプリ
ント回路基板５上の端子６のピッチも狭くなり、加熱溶
融時における、はんだの端子外への流出による短絡が避
けられなくなるという問題点が生しる。On the other hand, when mounting a semiconductor integrated circuit using a multi-pin lead frame, a so-called surface mounting method is generally used, in which the terminals 6 are soldered onto the surface of the terminals 6 provided on the printed circuit board 5. The method used for soldering is to apply solder paste and melt it by heating. However, as the pitch of the outer leads 2 becomes narrower, the pitch of the corresponding terminals 6 on the printed circuit board 5 also becomes narrower, resulting in the problem that short circuits due to solder flowing out of the terminals during heating and melting cannot be avoided. is born.
上記の問題点を解決するために、本発明では、あらかじ
め、アウターリード２のプリント回路基板５上の端子部
６と接する面に、溝部１０を形成し、その溝部１０には
んだ部工を形成する。In order to solve the above problems, in the present invention, a groove 10 is formed in advance on the surface of the outer lead 2 that contacts the terminal portion 6 on the printed circuit board 5, and a solder part is formed in the groove 10. .
〔発明の詳述］
樹脂封止した半導体集積回路をプリント回路基板５上に
はんだ付けするには、プリント回路基板５上の端子６の
上に、あらかじめ、はんだペーストを塗布し、リードフ
レームのアウターリード２の接合部を加熱接合する。[Detailed Description of the Invention] In order to solder the resin-sealed semiconductor integrated circuit onto the printed circuit board 5, solder paste is applied on the terminals 6 on the printed circuit board 5 in advance, and solder paste is applied to the outer surface of the lead frame. The joint portion of lead 2 is heated and joined.
アウターリード２の狭ピッチ化にともない、それに対応
するプリント回路基板５上の端子部６の狭ピッチ化が必
要となってくる。このため、加熱熔融の際、流出したは
んだが隣の端子６上のはんだと接触し、短絡を招くとい
う上述の問題点が発生する。As the pitch of the outer leads 2 becomes narrower, it becomes necessary to correspondingly narrow the pitch of the terminal portions 6 on the printed circuit board 5. Therefore, during heating and melting, the solder that flows out comes into contact with the solder on the adjacent terminal 6, causing the above-mentioned problem of causing a short circuit.
この問題点を解決するために、あらかじめ、リードフレ
ーム製造時に、アウターリード２のプリント回路基板５
上の端子部６と接する面に、溝部１０を形成し、その溝
部１０にはんだペーストを埋め込んでおくと、加熱時の
はんだの流出は溝部１０周辺に抑えられ、端子６外への
流失は起こらなくなる。また、はんだとリードフレーム
の接する面積は溝６の分だけ大きくなるため、接着強度
は高くなる。In order to solve this problem, when manufacturing the lead frame, the printed circuit board 5 of the outer lead 2 is
By forming a groove 10 on the surface in contact with the upper terminal 6 and filling the groove 10 with solder paste, the solder flowing out during heating is suppressed around the groove 10 and does not flow outside the terminal 6. It disappears. Furthermore, since the contact area between the solder and the lead frame is increased by the groove 6, the adhesive strength is increased.
このようなリードフレームを製造する方法としては、エ
ツチング法で通常のリードフレームを製造する方法、す
なわち、金属板７の両面にフォトレジスト８で所望のパ
ターンを形成し、両面からエツチング液で腐食を行って
製造する方法をそのまま用いることが可能で、溝部１０
に相当する部分にフォトレジストの開口部９を設けるよ
うに設計しておけばよい。フォトレジスト１１１Ｂのパ
ターンを形成後、両面からエツチング液で腐食すると、
溝部１０では片面のみ腐食されるため、金属板７厚の半
分相当の深さの溝が形成される。溝部１０の開口形状は
規定するものではなく、はんだ付は後に外部へはんだが
流出せず、適度な接着強度が得られるように設計すれば
よい、形成された溝部１０にはんだを埋め込む方法も規
定するものではないが、印刷方式がより簡便である。A method for manufacturing such a lead frame is to use an etching method to manufacture a normal lead frame. In other words, a desired pattern is formed on both sides of a metal plate 7 using photoresist 8, and corrosion is removed from both sides using an etching solution. It is possible to use the method of manufacturing the groove part 10 as it is.
It is only necessary to design the photoresist so that the opening 9 is provided in a portion corresponding to . After forming the pattern of photoresist 111B, if etching is applied from both sides,
Since only one side of the groove portion 10 is corroded, a groove having a depth equivalent to half the thickness of the metal plate 7 is formed. The shape of the opening of the groove 10 is not specified, and the design should be such that the solder does not leak out later and a suitable adhesive strength is obtained.The method of filling the formed groove 10 with solder is also specified. However, the printing method is simpler.
金属板として、４２合金（４２重量％Ｎｉ、Ｆｅ残）を
用い、その両面に東京応化工業■製のネガ型フォトレジ
ストＰＭＥＲ（商品名）を浸漬塗布しく第４図（ａ）参
照）、所望のパターンを有するマスクを用いて、露光、
現像を行い、フォトレジスト膜のパターン化を行った（
第４図（ｂ）参照）。42 alloy (42% by weight Ni, remaining Fe) was used as the metal plate, and a negative photoresist PMER (trade name) manufactured by Tokyo Ohka Kogyo ■ was dip coated on both sides (see Fig. 4(a)), as desired. Exposure using a mask with a pattern of
Development was performed and the photoresist film was patterned (
(See Figure 4(b)).
この際、溝部となるべき部分のフォトレジストが除去さ
れるように、あらかしめ、マスクのパターンを設計して
おく。At this time, the mask pattern is designed in advance so that the photoresist in the portions that should become the grooves is removed.
その後、塩化第二鉄液を用い、両面からエツチングを行
い、リードフレームを形成した（第４図（ｃ）参照）。Thereafter, etching was performed from both sides using a ferric chloride solution to form a lead frame (see FIG. 4(c)).
このとき、金属板厚の半分相当の深さの溝が形成された
。At this time, a groove with a depth equivalent to half the thickness of the metal plate was formed.
フォトレジストを剥離後、はんだペーストを印刷するこ
とにより、はんだ部を形成゛し、目的としたリードフレ
ームを製造した（第４図（ｄ）参照）。After peeling off the photoresist, a solder portion was formed by printing a solder paste, and the intended lead frame was manufactured (see FIG. 4(d)).
本発明によるリードフレームを用いた半導体集積回路を
プリント配線基板に実装する際、はんだの端子部外への
流出が抑えられ、多ピンの半導体集積回路の実装が可能
となった。また、本リードフレームは通常のエツチング
法による製造方法を用いることが可能であり、はんだ層
形成も印刷方式が可能であるため、簡便な方法で製造で
きるという利点を有する。When a semiconductor integrated circuit using the lead frame according to the present invention is mounted on a printed wiring board, solder is prevented from flowing out of the terminal portion, making it possible to mount a multi-pin semiconductor integrated circuit. Further, this lead frame can be manufactured using a normal etching method, and the solder layer can also be formed by a printing method, so it has the advantage that it can be manufactured by a simple method.
第１図は、本発明のリードフレームの一実施例を示す平
面図である。第２図は、本発明のり一ド７レームを用い
て、半導体集積回路のチンブを樹脂封止し、アウターリ
ード先端部を曲げ加工により成形し、プリント回路基板
上に実装可能にした状態を示す概略説明図である。第３
図は、プリント回路基板上の端子にはんだ付けした状態
を示す断面説明図であり、第３図（ａ）は本発明のリー
ドフレームを用いた半導体集積回路素子をプリント回路
基板上にはんだ付けした状態を示す断面説明図であり、
第３図（ｂ）は従来法で製造したリードフレームを用い
た半導体集積回路素子をプリント回路基板上にはんだ付
けした状態を示す断面説明図である。第４図（ａ）〜（
ｄ）は本発明のリードフレームの製造方法の一例を工程
順に示す断面説明図である。
１・・・はんだ部
３・・・インナーリード
５・・・プリント回路基板
７・・・金属板
９・・・溝部に相当するフォ
１０・・・溝部
２・・・アウターリード
４・・・封止樹脂
６・・・端子部
８・・・フォトレジスト
トレジストの開口部FIG. 1 is a plan view showing an embodiment of the lead frame of the present invention. Fig. 2 shows a state in which the chip of a semiconductor integrated circuit is sealed with resin using the adhesive 7 frame of the present invention, and the tip of the outer lead is formed by bending so that it can be mounted on a printed circuit board. It is a schematic explanatory diagram. Third
The figure is an explanatory cross-sectional view showing a state in which the semiconductor integrated circuit element using the lead frame of the present invention is soldered onto the printed circuit board. It is a cross-sectional explanatory diagram showing the state,
FIG. 3(b) is an explanatory cross-sectional view showing a state in which a semiconductor integrated circuit element using a lead frame manufactured by a conventional method is soldered onto a printed circuit board. Figure 4(a)-(
d) is a cross-sectional explanatory view showing an example of the lead frame manufacturing method of the present invention in the order of steps; 1...Solder part 3...Inner lead 5...Printed circuit board 7...Metal plate 9...Front 10 corresponding to the groove part...Groove part 2...Outer lead 4...Sealing Stopper resin 6...Terminal part 8...Opening part of photoresist resist
Claims (1)
ーリード２部分に、溝部１０が形成され、前記溝部１０
にはんだ部１が設けられてなることを特徴とするリード
フレーム。（２）金属板７両面にフォトレジスト８で所
望のパターンを形成し、エッチングによってリードフレ
ームを製造する際、溝部１０を片面エッチングにより形
成し、その後、溝部１０にはんだ部１を形成することを
特徴とする請求項（１）に記載するリードフレームの製
造方法。(1) A groove portion 10 is formed in a portion of the outer lead 2 corresponding to the terminal portion 6 on the printed circuit board, and the groove portion 10
A lead frame characterized by being provided with a solder portion 1. (2) When manufacturing a lead frame by forming a desired pattern on both sides of the metal plate 7 with photoresist 8 and etching it, it is recommended to form the groove part 10 by etching one side of the metal plate and then form the solder part 1 in the groove part 10. A method for manufacturing a lead frame according to claim (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26806190A JPH04144263A (en) | 1990-10-05 | 1990-10-05 | Lead frame and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26806190A JPH04144263A (en) | 1990-10-05 | 1990-10-05 | Lead frame and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04144263A true JPH04144263A (en) | 1992-05-18 |
Family
ID=17453347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26806190A Pending JPH04144263A (en) | 1990-10-05 | 1990-10-05 | Lead frame and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04144263A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011237207A (en) * | 2010-05-07 | 2011-11-24 | Japan Electronic Materials Corp | Probe |
| JP2014154756A (en) * | 2013-02-12 | 2014-08-25 | Calsonic Kansei Corp | Conductive member and temporary joining method of sheet |
| CN110972399A (en) * | 2019-12-19 | 2020-04-07 | 黄石星河电路有限公司 | Production process of printed circuit board with groove in middle of IC bonding pad |
-
1990
- 1990-10-05 JP JP26806190A patent/JPH04144263A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011237207A (en) * | 2010-05-07 | 2011-11-24 | Japan Electronic Materials Corp | Probe |
| JP2014154756A (en) * | 2013-02-12 | 2014-08-25 | Calsonic Kansei Corp | Conductive member and temporary joining method of sheet |
| CN110972399A (en) * | 2019-12-19 | 2020-04-07 | 黄石星河电路有限公司 | Production process of printed circuit board with groove in middle of IC bonding pad |
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