JPH04142643A - Input/output controller - Google Patents

Abstract

PURPOSE:To prevent data transfer stop by providing an input/output controller with the function that when data transfer is requested from a plurality of channels, if effective prefetch data items are present in a prefetch data buffer for the channels that issued a request for data transfer, data transfer to relevant channel is taken preferentially. CONSTITUTION:Prefetch data transfer address buffer 20 holds prefetch data transfer address for each channel, and prefetch data buffer 40 stores prefetch data for each channel. Further, output data transfer control circuit 30 manages and controls the prefetch data buffer 40 for controlling the execution of prefetching and also returns a prefetch data not-stored signal to the prefetch data buffer 40 for a channel where prefetch data is not yet stored therein. Furthermore, channel request control circuit 50 receives a data transfer request from a plurality of channels, selects one channel in accordance with prefetch not-stored signals for each channel and an inherent priority sequence of each channel, and accepts a data transfer request from selected channels. With this, stopping of data transfer can be protected.

Description

TECHNICAL FIELD The present invention relates to an input/output control device, and more particularly to an input/output control device that transfers data from a prefetch buffer in response to data transfer requests from a plurality of channels.

Conventional technology Conventionally, in this type of input/output device, when data transfer requests from multiple channels conflict, a channel request control circuit selects one channel only based on channel-specific priorities during output transfer. and was accepting data transfer requests for the selected channel. Then, the data according to the request was transferred. Furthermore, the priority order for each channel was managed using a table of channel numbers and priority orders.

In other words, in the conventional input/output control device described above, in output transfer, the channel request control unit selects a data transfer request for one channel from among data transfer requests from multiple channels based only on the priority of each channel,
If the data to be transferred to that channel is not stored in the prefetch data buffer because data was being output, data transfer to the channel will be stopped until the data in that channel becomes valid. There was a drawback that it could be stored away. In other words, if there is no data in the preemption rebuffer that should be transferred to a channel with a higher priority, the transfer will be forced to wait even if there is data in the preemption buffer that should be transferred to a channel with a lower priority. was there.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide an input/output control device in which data transfer does not stop.

Structure of the Invention An input/output control device according to the present invention includes a prefetch rebuffer that holds prefetched data in main memory, responds to data transfer requests from a plurality of channels with predetermined priorities, and responds to data transfer requests from a plurality of channels with predetermined priorities. an input/output control device that transfers data in the prefetch rebuffer according to the method, the device includes means for determining whether or not there is data to be requested in the prefetch rebuffer in response to reception of the request; , means for processing a request of the next priority when it is indicated that there is no data to be requested.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an input/output control device according to the present invention.

In the figure, an input/output control device 1 according to an embodiment of the present invention
0 is connected to a plurality of channels (not shown), and in output transfer, there is a prefetch data transfer address buffer 20 that holds a prefetch address for data transfer for each channel, and a prefetch data transfer address buffer 20 that stores prefetch data for each channel. Output data transfer that manages and controls the prefetch data buffer 40 and the prefetch data buffer, controls the execution of prefetch, and returns a prefetch non-signal for channels for which prefetch data is not stored in the prefetch pig buffer. The control circuit 30 receives and receives data transfer requests from a plurality of channels, selects one channel based on the pre-empted signal for each channel and the priority unique to each channel, and accepts and accepts data transfer requests from the selected channel. The channel request control circuit 50 is configured to include a channel request control circuit 50.

In the input/output control device 10 having such a configuration, when output transfer to a certain channel is started in output transfer of data in a main memory (not shown), the address storage section of the prefetch data transfer address buffer 20 corresponding to the channel is The prefetch address is set to . Then, before an output transfer request is made from that channel at the set prefetch address i, a pig transfer request a is sent to the main memory (not shown), and the operation of reading the transfer data from the main memory (prefetch )I do.

The read transfer data f from the main memory device is stored in the data storage section of the channel-corresponding prefetch data buffer 40 for that channel.

In this state, in the prefetch data transfer address buffer 20, the next prefetch address b, which is counted up by the number of bytes of transfer data from the main memory, is set in the channel storage section described above.

The prefetch data buffer 40 is managed and controlled by the control signal e from the output data transfer control circuit 30, and when a data transfer request is made from a channel, the prefetch data buffer 40 receives a prefetch data transfer for that channel from the channel request control circuit 50. Request d is output. Then, the prefetch data buffer 40 controlled by the output data transfer control circuit 30 that receives the prefetch data for that channel is outputted as transfer data g to the channel.

Data is transferred to the channel and prefetch data buffer 4
When 0 no longer has valid prefetch data for that channel,
Preemptive action again.

Here, when there are multiple data transfer requests from the channel at the same time, that is, when requests conflict, the data transfer request a to the main storage device is processed by the preemptive read address in the preemptive data transfer address buffer 20.
is output. Then, the transfer data f from the main storage device
It is determined whether valid data to be transferred to each channel is stored in the prefetch data buffer 40.

For channels that are not stored, the output data transfer control circuit 30 sends a prefetched unread signal C of each channel.
is output. In the channel request control circuit 50, there is a data transfer request from a channel, and one channel is selected from among the channels excluding channels that are not preemptive based on the priority order specific to each channel. In other words, if the highest priority among competing requests has not been preempted, the next priority is selected.

In this way, the preemptive data transfer request d for the selected channel is output from the channel request control circuit 50,
The prefetch data corresponding to that channel in the prefetch data buffer 40 is transferred to that channel.

Therefore, requests that have not been preempted are postponed, so data transfer does not stop.

Note that if three requests conflict, the first
If the second priority is not prefetched, it goes without saying that the third priority will be transferred.

As described in detail, the present invention provides, in output transfer in an input/output control device, in response to data transfer requests from multiple channels, valid prefetch data (to be sent to the channel with the data transfer request) is stored in the prefetch redata buffer. By giving priority to the prefetch data buffer if it exists in the prefetch data buffer, the effect is that data transfer from the prefetch data buffer to the channel can be executed without stopping.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an input/output control device according to an embodiment of the present invention. Explanation of symbols of main parts

Claims (1)

[Claims] (1) includes a prefetch buffer that holds prefetched data in main memory, responds to data transfer requests from a plurality of channels with predetermined priorities, and transfers data in the prefetch buffer according to the priority order; an input/output control device for determining whether or not there is data to be requested in the prefetch buffer in response to reception of the request; An input/output control device comprising means for processing a request of the next priority when indicated.