JPH04141777A - Logic simulation system - Google Patents

Abstract

PURPOSE:To shorten processing time by performing simulation to the only part attached by the correction in a logic circuit. CONSTITUTION:The system is composed of a model preparation part 1 and a simulation part 2. In the model preparation part 1, circuit information 3 and correction information 4 is inputted, and a simulation model 5 is prepared. In the simulation part 2, the simulation model 5 and an input pattern 6 are inputted, and an output pattern 7 is outputted. In this case, the simulation is performed to the only circuit of the part affected by the correction while utilizing the simulation model 5. Thus, excessive processing time is unnecessitated at the time of performing simulation again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulation method, and particularly to a logic simulation method for large-scale logic circuits.

[Conventional technology]

In the conventional logic simulation method, when performing the simulation again after modifying the logic circuit model, the entire circuit is simulated.

[Problem to be solved by the invention]

The above-described conventional logic simulation method has a drawback in that it requires a large amount of processing time when performing simulation again.

[Means to solve the problem]

The logic simulation method of the present invention includes means for creating a simulation model using circuit information before modification and circuit modification information when a modification is made in a logic circuit;
and means for simulating only the portion of the circuit affected by the modification using the simulation model.

〔Example〕

FIG. 1 is a flowchart showing the configuration of an embodiment of the present invention.

This embodiment is composed of a model creation section 1 and a simulation section 2. In the model creation section 1, circuit information 3 and modification information 4 are input, and a simulation model 5 is created. In the simulator a section 2, a simulation model 5 and an input button 6 are input, and an output button 7 is output.

FIG. 2 is a block diagram showing a logic circuit model before modification, and FIG. 3 is an example of a block diagram showing a logic circuit model after modification. In the model creation section 1, the circuit information 3 shown in FIG. 2 and the correction information 4 shown in FIG. 13 and output pins 21 and 22), and create a simulation model 5. In the simulation section 2, the circuit range (
Regarding input pins 11 to 13 and output pins 2l to 22), input button 6 is input, simulation is performed, and output button 7 is obtained. No simulation is performed for the circuit range (input pins 14 and 15, output pin 23) that is not affected by the modification information 4.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing processing time because simulation is performed only on the portions affected by modification in the logic circuit.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a logic circuit model before modification of this embodiment, and FIG. 3 is a block diagram showing a logic circuit model after modification of this embodiment. The block diagram shown in FIG. 1...Model creation section, 2...Simulation section,
3... Circuit information, 4... Correction information, 5... Simulation model, 6... Input button, 7... Output button, 11-15... Input pin, 21-23...
Output pin.

Claims (1)

[Claims] Means for creating a simulation model using circuit information before correction and circuit modification information when a modification is made in a logic circuit; and means for simulating only a portion of the circuit affected by the modification using the simulation model. A logical simulation method characterized by comprising the following.