JPH04138747A - Storage controller for reception data - Google Patents

Abstract

PURPOSE:To surely write plural data in the unit of transmission sent continuously at a high speed to a storage device by generating an address in response to the end of transmission unit such as a packet. CONSTITUTION:When a flat check timing generating circuit 21 detects a flag just after an initial packet, the circuit 21 outputs a packet end signal. When both a CRC error and an address error are not in existence, a validity discrimination circuit 26 outputs a valid packet end signal to increment the content of a bank counter 42 by one thereby designating an address of a succeeding bank of a storage device 100. When the CRC error or the address error is in existence, no valid packet end signal is generated and the count of the bank counter 42 is not incremented. The operation as above is repeated and a packet without any error is stored in a series of banks of the storage device 100 sequentially.

Description

[Detailed description of the invention] [Industrial application field]

This invention can be applied, for example, to a high-level data link control procedure (
The present invention relates to a storage control device for received data that controls writing of data that is divided into predetermined transmission units and transmitted into a storage device, such as the HDLC (hereinafter abbreviated as HDLC) system.

[Summary of the invention]

The present invention provides a device for controlling the writing of data divided into predetermined transmission units and transmitted into a storage device, which detects the end of the transmission unit, and based on the detection signal, starts the next transmission unit. By providing an address generation circuit that generates the address of the storage device for the data, CPU processing is not required and the received data can be reliably written to the storage device even when a plurality of transmission units are successively received. It has been made possible.

[Conventional technology]

As shown in FIG. 4, in the HDLC data format, data to be transmitted is divided into predetermined transmission units called packets. Flags are placed before and after the packet. The flag has a pattern of "01111110" including six consecutive "1"s. For data other than flags, “1” is 5.
If m consecutively, "01" is forcibly inserted, so the flag can be distinguished from other data.
It is configured to include, in this order, an address specifying the next station (station receiving data or control), data, and a CRC code for error detection. Data transfer of such HDLC format data from a receiving circuit to a storage device has conventionally been carried out using a general-purpose DMA.
Although this is done using a controller, address setting for storing received packets is done by a central processing unit f (hereinafter abbreviated as CPU).

[Problem to be solved by the invention]

As mentioned above, conventionally, the CPU sets the address for storing received packets, so when multiple packets are transmitted in succession, the first packet cannot be stored. However, there were cases where the next packet could not be memorized. In other words, when the data rate is 125 Kbps, the time from detecting the end of one transmission unit of data by receiving a flag to receiving the next data is 64 μSee.
It is. The faster the data rate becomes, the shorter this time will be. With current CPU performance, several tens of μSee
It is difficult to set the address within the following time. The present invention provides a storage control device for received data that can write received data into a storage device even when a plurality of transmission units (for example, packets) are continuously transmitted at a high data rate, and that does not require processing by a CPU. The purpose is to provide

[Means to solve the problem]

In order to achieve the above object, the present invention provides a transmission unit end detection circuit (for example, a transmission unit end detection circuit) which detects the end of a transmission unit such as a packet and outputs a transmission unit end signal when made to correspond to the embodiment shown in FIG. 2), an address generation circuit (4) that generates an address for the storage device (100) in response to a transmission unit end signal, and a controller (6) that controls the supply of received data and address to the storage device (100). ).

[Effect]

In the received data storage control device of the present invention, when data transmitted divided into predetermined transmission units such as packets is received, a transmission unit end signal indicating the end of the transmission unit is generated, and the transmission unit ends. An address of the storage device (100) is generated in response to the signal. Therefore, the CPU
(200) no longer needs to set the address of the storage device (100), and even if multiple transmission units of data are sent consecutively at high speed, these transmission units (especially the second and subsequent transmission units) Data can be stored reliably.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a received data storage control device according to the present invention. This example is based on the fourth
It is configured to be adaptable to the HDLC format shown in the figure, and controls writing of data divided into packets and transmitted to the storage device 100. The main components of this embodiment are an end of valid packet detection circuit 2 which detects the end of a valid packet (i.e. without CRC error and address error) and generates an end of valid packet signal, and a circuit 2 which receives the end of valid packet signal. an address generation circuit 4 that generates an address for the storage device 100, and a DMA controller 6 that controls the supply of data to the storage device 100 and the supply of the address. The valid packet end detection circuit 2 includes a flag detection timing generation circuit 21, a CRC check circuit 22, an address check circuit 23, delay circuits 24 and 25, and a validity/invalidity determination circuit 26. The flag detection timing generation circuit 21 detects a flag from the HDLC format received data and generates a packet end signal, and also generates a start signal to start the CRC check circuit 22 and address check circuit 23. It can be configured as shown in Figure 3. In FIG. 3, the flag pattern detection circuit 211 outputs "1" when it detects "01111110" corresponding to the flag in the received data. The output of this flag pattern detection circuit 211 is connected to the clock inputs of two D flip-flops 212 and 213 connected in series. 1'' is always applied to the data output of the flip-flop 212, the output Q of the flip-flop 212 is connected to the data input D2 of the flip-flop 213, and the outputs of the two flip-flops 212 and 213 are connected to the AND output. It is connected to the human power of the gate 214. The terminal of the output Q1 of the flip-flop 212 is a terminal for generating a start signal, and the output terminal of the AND gate 214 is a terminal for outputting a packet end signal. When the first flag is detected (this corresponds to detecting the beginning of a packet), the flag pattern detection circuit 211 outputs "1" to the clock input of the flip-flop 212, and the flip-flop circuit 212 outputs "1" to the clock signal of the flip-flop circuit 212. The start signal is set to 1” and the CRC check circuit 22 and address check circuit 23
Output to. When the flag pattern detection circuit 211 detects the next flag (this corresponds to detecting the end of the packet), the flag pattern detection circuit 2]1 outputs "1" to the clock inputs of the flip-flops 212 and 213. As a result,
Outputs Q and Q2 of flip-flops 212 and 213
Both become “1”, and the output of the AND gate 214 becomes “1”.
1", and a packet end signal is generated. When the CRC check circuit 22 receives the start signal from the flag detection timing generation circuit 21, it divides the received data by the generation polynomial, and if it is not divisible, a CRC error signal is generated. via the delay circuit 24 to the validity/invalidity determination circuit 26
Output to. When the address check circuit 22 receives the start signal from the flag detection timing generation circuit 21, it checks the address part of the received data and determines whether the next data is for the station in question, and if it is not for the station in question. The address error signal is outputted to the validity/invalidity determination circuit 26 via the delay circuit 25. The delay circuits 24 and 25 are provided to adjust the time so that the packet end signal, CRC error signal, and address error signal are simultaneously supplied to the validity/invalidity determination circuit 26, and are, for example, a shift register having an appropriate number of stages. Consisted of. The validity/invalidity determination circuit 26 outputs a valid packet end signal to the address generation circuit 4 when it receives a packet end signal but does not receive a CRC error signal or an address error signal. Also, when receiving the packet end signal, C
When receiving the RC error signal or the address error signal or both, the validity/invalidity determination circuit 26 outputs an invalidation signal to the address generation circuit 4. The address generation circuit 4 is configured in accordance with the fact that the storage device 100 is configured to have a plurality of banks each corresponding to one packet as shown in FIG. It consists of a bank counter 42, a data counter 43, and an OR circuit 44. Upper address circuit 41 generates bits common to all of storage device 100. The puncture counter 42 receives the effective packet end signal as an increment signal, and increases its value by one each time it receives this increment signal. This counter 42
The output of is an intermediate address that specifies one bank of the storage device 100. The data counter 43 receives, as an increment signal, a 1-byte data reception signal generated each time the data receiving circuit 30 receives 1 byte of data, and increases the value by 1 each time it receives this increment signal. The output of this counter 43 is a lower address indicating a particular byte in one bank of storage device 100. The data counter 43 is reset by receiving a valid packet end signal or an invalid signal from the valid packet end detection circuit 2 via the OR circuit 44. The upper address circuit 41, bank counter 42, and data counter 43 generate upper, middle, and lower addresses, respectively, when receiving a data transfer command from the DMA controller 6. When the DMA controller 6 receives the 1-byte data reception signal from the data reception circuit 30, it outputs a bus occupancy request BUSREQ requesting the CPU 200 to occupy the data bus 50 and the address bus 60 via the control bus 70, and CPU20
When receiving bus occupancy permission BUSACK indicating permission for occupancy of the data bus 50 and address bus 60 from 0 through the control bus 70, it outputs a data transfer command. The DMA controller 6 also provides a write command WR or a read command RE to the storage device 100 via the control bus 70. The storage device 100 performs write or read operations in response to commands WR and RE. Note that, upon receiving a data transfer command from the DMA controller 6, the data receiving circuit 30 transfers 1 byte of data to the storage device 100 via the local data bus 32 and the data bus 50.
Transfer to. In the embodiments of FIGS. 1, 2, and 3 configured as described above, not a single packet is currently being received, and the values of the puncture counter 42 and data counter 43 are 0.
Therefore, it is assumed that the address of the 0th byte of the 0th (first) bank of the storage device 100 is specified. When the first data byte of the first packet is received, the data receiving circuit 30 outputs a 1-byte data receiving signal to the DMA controller 6. In response, the DMA controller 6 provides a bus occupancy request BUSREQ to the CPU 200 via the control bus 70. controller 6
When receiving bus occupancy permission BUSACK from the CPU 200, it outputs a data transfer command to the upper address circuit 41, the puncture counter 42, the data counter 43, and the data receiving circuit 30. Further, the DMA controller 6 gives a write command WR to the storage device 100. As a result, the first data byte of the first packet is the address for the first byte of the 0th (first) bank of the storage device 100 (because the value of the data counter 43 is increased by 1 due to the 1-byte data reception signal).
will be written to. Similarly, the second and third packets of the first packet
. . data bytes are written to the addresses for the second, third, . . . bytes of the 0th bank of the storage device 100. On the other hand, the flag detection timing generation circuit 21 of the valid packet end detection circuit 2 detects the flag immediately before the first packet and generates a start signal, and in response to this, the CRC check circuit 22 and address check circuit 23 respectively Checks for errors and sends the result to delay circuit 2
4 and 25 to the validity/invalidity determination circuit 26. When the flag detection timing generation circuit 21 detects the flag immediately after the first packet, it outputs a packet end signal. If there is neither a CRC error nor an address error, the validity/invalidity determination circuit 26 outputs a valid packet end signal, increments the value of the puncture counter 42 by one, and causes the next bank of the storage device 100 to be addressed. The validity/invalidity determination circuit 26 does not generate a valid packet end signal and does not increase the value of the puncture counter 42 when there is a CRC error or an address error. Therefore, when the next packet is received, it will be written to the bank to which the previous packet was written. Since the previous packet has an error, there is no problem even if it is erased by writing the next packet. The operations described above are repeated to sequentially store error-free packets in successive banks of storage device 100. Note that in the above embodiment, writing is performed from a storage area with a small address to a storage area with a large address, so the values of the puncture counter and data counter are sequentially increased. However, it is not necessary to do this. Alternatively, writing may be performed from a large address area to a small address area sequentially. In this case, the values of the bank and data counters may be sequentially decreased. Further, it is not necessarily necessary to specify the address using a counter; any means may be used as long as it can change the address value generated in response to the packet end signal.

【Effect of the invention】

As is clear from the above explanation, according to the present invention, an address can be generated according to the end of a transmission unit such as a packet, so there is no need for processing by the CPU, and the address can be transmitted continuously at high speed. Multiple transmission units of data can be reliably written to the storage device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a storage control device for received data according to the present invention, FIG. 2 is an explanatory diagram showing an example of the configuration of the storage device 100 of FIG. 1, and FIG. FIG. 4 is a block diagram showing an example of the configuration of the flag detection timing generation circuit shown in FIG. 1, and FIG. 4 is an explanatory diagram showing an HDLC data format. 2; Valid packet end detection circuit 4; Address generation circuit 6; DMA controller 21; Flag detection timing generation circuit 42; Bank counter 43; Data counter 100; Storage device 200, CPU Agent Patent attorney Masami Sato Procedural Amendment Heisei April 158, 1990 1. Display of the case 1990 Patent Application No. 261985 2. Name of the invention Storage control device for received data 3. Person making the amendment Relationship to the case Patent applicant address Tokyo Parts Co., Ltd. Kitashinyo 6-7-35 Name (2
18) Sony Corporation Representative Norio Ohga 4 Agent 1130 Address Sun Palace Shinjuku 1207, 8-12-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Detailed description of the invention in the specification, brief description of the drawings Columns and drawings. 8. Contents of amendment (1) In the specification, from page 7, line 6 to page 8, line 16, "In FIG. 3, an end signal is generated." is corrected as follows. "In FIG. 3, the flag pattern detection circuit 211
“01111110” corresponding to the flag in the received data
When detected, the flag detection output FLGD (
Figure 5A) is output. This flag detection output FLGD is supplied to the pulse generation circuit 214. This pulse generating circuit 214 outputs a pulse PS (FIG. 5B) synchronized with, for example, a data pit clock. This pulse PS
is supplied to AND circuits 215 and 216. Flag detection output F from flag pattern detection circuit 211
LGD is also supplied to the clock pulse input terminals of two D flip-flop circuits 212 and 213 connected in series. “1” is always applied to the data input terminal of the flip-flop circuit 212, and the output Q1 of the flip-flop circuit 212 is supplied to the data input terminal D2 of the flip-flop circuit 213. Then, the output Q of the flip-flop circuit 212 or the AND circuit 21
Furthermore, the output Q2 of the flip-flop circuit 213 is supplied to the AND circuit 216. In the above configuration, when the flag pattern detection circuit 211 detects the first flag (this corresponds to detection of the starting edge of a packet), the flag pattern detection circuit 211 detects the first flag.
The flag detection output FLGD which rises to "1" is output to the flip-flop circuit 212. Therefore, the output Q1 of the flip-flop circuit 212 or the flag detection output FLGD which rises to "1" is output to the flip-flop circuit 212.
1', the AND circuit 215 gates the output pulse PS of the pulse generation circuit 214, outputs it as a start signal ST (E in FIG. 5), and supplies it to the CRC check circuit 22 and address check circuit 23. do. When the flag pattern detection circuit 211 detects the next flag (this corresponds to detecting the end of the packet), since the output Q+ of the flip-flop circuit 212 is "1", the output Q of the flip-flop circuit 213, But the fifth
It rises to “1” as shown in the figure. Therefore, the AND circuit 216 outputs the output pulse PS of the pulse generation circuit 214.
is gated, and this is used as the packet end signal END (fifth
Output as Figure F). Note that the flip-flop circuits 212 and 213 are reset at system startup. j(2) Same, page 9, line 2,
"Check circuit 22" is corrected to "check circuit 23." (3) Same, page 16, line 5, "This is an explanatory diagram." is corrected to "The explanatory diagram, FIG. 5, is a time chart for explaining FIG. 3." (4) In the drawings, Figure 3 is corrected as shown in the attached sheet. (5) Add Figure 5 in the attached sheet. that's all

Claims (1)

[Claims] Data that is divided into predetermined transmission units and transmitted,
A storage control device for received data that controls writing to a storage device, the device comprising: a transmission unit end detection circuit that detects the end of the transmission unit and outputs a transmission unit end signal; A storage control device for received data, comprising: an address generation circuit that generates an address for the storage device; and a controller that controls supply of the data to the storage device and supply of the address.