JPH0413855Y2 - - Google Patents

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Publication number
JPH0413855Y2
JPH0413855Y2 JP1983003118U JP311883U JPH0413855Y2 JP H0413855 Y2 JPH0413855 Y2 JP H0413855Y2 JP 1983003118 U JP1983003118 U JP 1983003118U JP 311883 U JP311883 U JP 311883U JP H0413855 Y2 JPH0413855 Y2 JP H0413855Y2
Authority
JP
Japan
Prior art keywords
output
matching
driver
signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983003118U
Other languages
Japanese (ja)
Other versions
JPS59108346U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP311883U priority Critical patent/JPS59108346U/en
Publication of JPS59108346U publication Critical patent/JPS59108346U/en
Application granted granted Critical
Publication of JPH0413855Y2 publication Critical patent/JPH0413855Y2/ja
Granted legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transmitters (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は無線送信機とアンテナとの整合回路
で、詳しくは出力同調器の自動調整回路に関す
る。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a matching circuit between a radio transmitter and an antenna, and more particularly to an automatic adjustment circuit for an output tuner.

〔従来の技術〕[Conventional technology]

送信機の出力同調器は、終段増幅素子とアンテ
ナ回路の整合をとつて、アンテナに最大の高周波
電力を供給することを目的としている。また広帯
域出力部とアンテナとの中間に挿入して回路の整
合を改善し、電波のスプリアスを低減する用途に
も用いられる。回路としては高調波低減効果の大
きいπ形整合回路が用いられることが多いが、こ
れは直列素子のコイルLと、入力側と出力側の並
列素子コンデンサとからなり、バンド切換はコイ
ルLの巻数を可減し、バンド内の微調整は入力側
バリコンVC1と出力側バリコンVC2とを調整して
行うのが普通である。ところで、これ等2個のバ
リコンの動作は互いに関連して影響し合うので、
双方を少しづつ動かして最良状態に合わせるのは
熟練を要する上に時間が掛る。そのため、従来か
らサーボコントロールによる自動同調制御が行わ
れているが、それには次のような問題点があつ
た。従来方式では最適点の検出に送信機出力部の
SWR(定在波比)が1.0に近くなるようにしてい
るが、送信状態でのSWR検出は送信機出力(進
行波電力)とアンテナ側からの反射波電力とより
計算で求めることは比較的容易である。しかし、
SWR値をサーボコントロールの規準とするため
にはSWR値は自動計測されなければならず、こ
れは特に周波数範囲が広く、出力も変化する用途
には困難が多く、反射波電力を検出するための方
向性結合器の特性の問題もあつて、この方式の実
施には多大の労力と費用を必要とする。
The purpose of the output tuner of the transmitter is to match the final stage amplification element and the antenna circuit to supply maximum high-frequency power to the antenna. It is also used to improve circuit matching and reduce spurious radio waves by inserting it between the broadband output section and the antenna. A π-type matching circuit, which has a large harmonic reduction effect, is often used as a circuit, but this consists of a series element coil L and parallel element capacitors on the input and output sides, and band switching is determined by the number of turns of coil L. Normally, fine adjustment within the band is performed by adjusting the input-side variable capacitor VC 1 and the output-side variable capacitor VC 2 . By the way, the operations of these two variable capacitors are related to each other and influence each other, so
Adjusting both parts little by little to achieve the best condition requires skill and time. For this reason, automatic tuning control using servo control has conventionally been performed, but this has the following problems. In the conventional method, the transmitter output section is used to detect the optimal point.
Although we try to keep the SWR (standing wave ratio) close to 1.0, SWR detection in the transmitting state is relatively difficult to calculate by calculating the transmitter output (traveling wave power) and the reflected wave power from the antenna side. It's easy. but,
In order to use the SWR value as a standard for servo control, the SWR value must be automatically measured, which is particularly difficult in applications where the frequency range is wide and the output changes. Due to problems with the characteristics of the directional coupler, implementing this method requires a great deal of effort and expense.

〔考案が解決しようとする課題〕[The problem that the idea aims to solve]

従来は送信機の同調を変えることにより、アン
テナ回路の定在波のモードが変化するから、送信
機出力部の高周波電圧と有効出力とは比例すると
は限らず、従つて出力電圧を出力電力の規準とす
ることができないとの観念からSWR値を規準と
していたものである。しかしながら、アンテナと
フイーダが一定であり、送信周波数も一定である
ならば、アンテナ回路における定在波の形は決定
してしまい、電圧値や電流値に支配される要素を
含まないから、いかなるSWRの状態でも送信機
出力部における電力と電圧の比例関係は保たれる
ので、単に出力電力の最大点を求めるだけならば
電圧検出で十分なものである。
Conventionally, changing the tuning of the transmitter changes the standing wave mode of the antenna circuit, so the high frequency voltage at the transmitter output section and the effective output are not necessarily proportional to each other, and therefore the output voltage is proportional to the output power. The SWR value was used as a standard based on the idea that it could not be used as a standard. However, if the antenna and feeder are constant and the transmission frequency is also constant, the shape of the standing wave in the antenna circuit is determined and does not include elements controlled by voltage or current values, so any SWR Since the proportional relationship between power and voltage at the transmitter output section is maintained even in this state, voltage detection is sufficient if simply finding the maximum point of output power.

〔課題を解決しようとする手段〕[Means to try to solve the problem]

無線送信機の出力側からSWR検出回路、コイ
ル、2つの可変コンデンサVC1,VC2からなるπ
形整合回路、出力検出回路およびアンテナを直列
接続し、前記SWR検出回路の出力はコンパレー
タで基準電圧と比較した出力をCPUに供給し、
前記出力検出回路の出力はA/D変換器を介して
前記CPUに供給し、該CPUの出力側には前記π
形整合器の2つの可変コンデンサVC1,VC2を交
互に変化させて整合させるよう連結した夫々の駆
動器M1,M2に接続する構成である。
π consisting of an SWR detection circuit, a coil, and two variable capacitors VC 1 and VC 2 from the output side of the wireless transmitter.
A shape matching circuit, an output detection circuit, and an antenna are connected in series, and the output of the SWR detection circuit is compared with a reference voltage by a comparator, and the output is supplied to the CPU.
The output of the output detection circuit is supplied to the CPU via an A/D converter, and the π
The configuration is such that the two variable capacitors VC 1 and VC 2 of the shape matching device are connected to respective drivers M 1 and M 2 connected to each other so as to alternately change and match them.

〔実施例〕〔Example〕

第3図は本考案の送信機の自動調整回路を示す
一実施例であり、第3図により説明する。図中
は送信機出力部であり、のπ形整合回路は送信
機出力部とアンテナとの間に配設し、アンテナと
π形整合回路の間に設けた送信出力検出回路
を設け、その出力側ははA/D変換器4に接続し
A/D変換器4の出力側とCPU5の入力ポート
と結線する。送信器出力部とπ形整合器の間
にSWR検出回路10を設け、その出力側とコン
パレータ9の他の入力端子には基準電圧を加え
て、出力側はCPU5の入力ポートに接続する。
CPU5からπ形整合回路の可変コンデンサ
VC1を連結した駆動器M16にCPU5の出力51
を接続し、π形整合回路の可変コンデンサVC2
を連結して駆動する駆動器M27に出力信号52
を入力する構成である。
FIG. 3 shows an embodiment of an automatic adjustment circuit for a transmitter according to the present invention, which will be explained with reference to FIG. 1 in the diagram
is the transmitter output section, the π-type matching circuit 2 is installed between the transmitter output section and the antenna, and the transmission output detection circuit 3 is installed between the antenna and the π-type matching circuit 2.
is provided, and its output side is connected to the A/D converter 4, and the output side of the A/D converter 4 is connected to the input port of the CPU 5. An SWR detection circuit 10 is provided between the transmitter output section 1 and the π-type matching box 2 , a reference voltage is applied to its output side and the other input terminal of the comparator 9, and the output side is connected to the input port of the CPU 5. .
Variable capacitor from CPU5 to π-type matching circuit 2
Output 51 of CPU 5 to driver M 1 6 connected to VC 1
and connect the variable capacitor VC 2 of the π-type matching circuit 2 .
The output signal 52 is sent to the driver M 2 7 which connects and drives the
It is configured to input.

第1図に送信出力回路の詳細が例示されてい
るように送信出力電圧21をコンデンサC1,C2
により分電圧出力して、D1,D2のダイオードで
整流して出力を得ている。この送信出力検出電圧
31はA/D変換器4に入力される。このA/D
変換器4の実用的回路例が第2図である。A/D
変換器4の出力デジタル値41はCPU5に入力
する。
As shown in the details of the transmission output circuit 3 in FIG. 1, the transmission output voltage 21 is connected to capacitors C 1 and C 2
The divided voltage is output by the diodes D 1 and D 2 and rectified to obtain the output. This transmission output detection voltage 31 is input to the A/D converter 4. This A/D
An example of a practical circuit of the converter 4 is shown in FIG. A/D
The output digital value 41 of the converter 4 is input to the CPU 5.

CPU5はπ形整合回路の可変コンデンサ
VC1の駆動器6と可変コンデンサVC2の駆動器7
に駆動用制御信号51と52を出力する。
CPU5 is a variable capacitor of π-type matching circuit 2
Driver 6 of VC 1 and driver 7 of variable capacitor VC 2
Drive control signals 51 and 52 are output to.

制御信号51と52はCPUの第4図のフロー
チヤートに従つて出力信号51と52を出力し
て、駆動器M16および駆動器M27を交互に作動
させて各駆動器と連結した可変コンデンサVC1
VC2を変化させる。一方A/D変換器4のデジタ
ル出力41をチエツクして出力電力の変化は判断
し、CPUに入力されるデジタル値41が大きく
なる方向に駆動器を動作させる。この一連の動作
を第4図のフローチヤートに従つて説明する。ま
ずSWR検出器10の出力電圧11がコンパレー
タ9の基準電圧91以上の時コンパレータ9の出
力92をCPU5に入力するよう構成する。即ち
SWR2以上であるかどうかを判定し2以上である
とCPU5から駆動器M16に制御信号51を出力
し駆動器M16で可変コンデンサVC1を変化させ
る。A/D変換器4からのデジタル信号41が大
きくなれば引続き制御信号51を出力し、デジタ
ル信号41が小さくなれば駆動器M16に供給す
る信号が逆方向に動く信号に変えて出力する。次
に制御信号51を停止して制御信号52を出力し
て駆動器M27を作動させて連結した可変コンデ
ンサVC2を変化させる。デジタル信号41をチエ
ツクして小さくなれば制御信号52は駆動器M2
7を逆方向に動かす信号に変えて出力する。可変
コンデンサVC2が調整されると制御信号52は停
止して制御信号51を出力して再び可変コンデン
サVC1を調整する。この制御信号51と52は調
整が終了する迄交互に繰り返し出力されてπ形整
合器が調整される。この調整の終了はSWR検出
回路10の出力電圧11は最低電圧となつてコン
パレータ9の基準電圧91以下となつたとき、す
なわち第4図のフローチヤートではSWR1.5以下
となつたときCPU5に入力する駆動電圧92は
無くなり、CPUの制御信号51,52は停止す
る。
The control signals 51 and 52 were output from the CPU according to the flowchart of FIG. 4 to alternately operate the driver M 1 6 and the driver M 2 7 and connect them to each driver. Variable capacitor VC 1 and
Vary VC 2 . On the other hand, a change in the output power is determined by checking the digital output 41 of the A/D converter 4, and the driver is operated in a direction in which the digital value 41 input to the CPU increases. This series of operations will be explained according to the flowchart of FIG. First, the configuration is such that when the output voltage 11 of the SWR detector 10 is higher than the reference voltage 91 of the comparator 9, the output 92 of the comparator 9 is input to the CPU 5. That is,
It is determined whether the SWR is equal to or greater than 2, and if it is equal to or greater than 2, the CPU 5 outputs a control signal 51 to the driver M 1 6, and the driver M 1 6 changes the variable capacitor VC 1 . If the digital signal 41 from the A/D converter 4 becomes large, it continues to output the control signal 51, and if the digital signal 41 becomes small, the signal supplied to the driver M 1 6 is changed to a signal that moves in the opposite direction and is output. . Next, the control signal 51 is stopped and the control signal 52 is outputted to operate the driver M 2 7 and change the connected variable capacitor VC 2 . Check the digital signal 41 and if it becomes small, the control signal 52 is sent to the driver M 2
7 into a signal that moves in the opposite direction and outputs it. When the variable capacitor VC 2 is adjusted, the control signal 52 is stopped and the control signal 51 is outputted to adjust the variable capacitor VC 1 again. These control signals 51 and 52 are alternately and repeatedly outputted until the adjustment is completed to adjust the π-type matching device. This adjustment ends when the output voltage 11 of the SWR detection circuit 10 reaches the lowest voltage and becomes less than the reference voltage 91 of the comparator 9, that is, when the SWR becomes less than 1.5 in the flowchart of FIG. The driving voltage 92 disappears, and the CPU control signals 51 and 52 stop.

〔考案の効果〕[Effect of idea]

本考案はπ形整合回路の調整をSWR信号で自
動整合の始動と停止を定め、出力信号を整合状態
の比較に用い、2つの可変コンデンサを自動的に
交互に調整するあたかも人が整合を行うのと同じ
方法で整合を行うよう構成してあるので整合を確
実にかつ迅速に自動調整できる効果がある。
This invention uses the SWR signal to automatically start and stop the adjustment of the π-type matching circuit, uses the output signal to compare the matching state, and automatically adjusts the two variable capacitors alternately, just as if a person were performing the matching. Since the alignment is configured to be performed using the same method as the above, there is an effect that alignment can be automatically adjusted reliably and quickly.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は基本回路図、第2図は出力レベルをチ
エツクするA/D変換回路図、第3図は本考案の
一実施例を示す送信機の自動調整回路図で、第4
図はCPUを動作させるフローチヤートである。 ……送信機出力部、……π形整合回路、
……出力検出回路、4……A/D変換機、5……
CPU、6,7……駆動器M1,M2、8……スター
トボタン、9……コンパレータ、10……SWR
検出回路、L……コイル、VC1,VC2……コンデ
ンサ。
Fig. 1 is a basic circuit diagram, Fig. 2 is an A/D conversion circuit diagram for checking the output level, Fig. 3 is an automatic adjustment circuit diagram of a transmitter showing an embodiment of the present invention, and Fig. 4 is a diagram of an automatic adjustment circuit of a transmitter showing an embodiment of the present invention.
The figure is a flowchart for operating the CPU. 1 ...Transmitter output section, 2 ...π-type matching circuit, 3
...Output detection circuit, 4...A/D converter, 5...
CPU, 6, 7...Driver M1 , M2 , 8...Start button, 9...Comparator, 10...SWR
Detection circuit, L...coil, VC1 , VC2 ...capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 送信機の出力側からSWR検出回路、コイルと
2つの可変コンデンサVC1,VC2からなるπ形整
合回路、出力検出回路およびアンテナを直列接続
し、前記SWR検出回路の出力はコンパレータで
基準電圧と比較して出力をCPUに供給し、前記
出力検出回路の出力はA/D変換器で変換して出
力レベルとして前記CPUに供給し、該CPUの出
力を前記可変コンデンサVC1に連結する駆動器
M1と可変コンデンサVC2に連結する駆動器M2
供給して前記π形整合回路を送信周波数に合うよ
う同調整合させる構成とし、SWR信号が基準値
を越えたレベルの間前記CPUから前記駆動器
M1,M2を動作させて前記π形整合回路を送信周
波数に同調させる整合信号を出力する整合信号出
力手段と、整合信号を前記駆動器M1またはM2
一方に供給して出力レベルが最大になるよう整合
させ、出力レベルが最大になると整合信号が他方
の駆動器に切換つて整合させ、出力レベルが最大
になると再び整合信号が一方の駆動器に切替り、
交互に整合を重ねて前記SWR信号が基準値以下
になると整合を停止して復旧する反復整合手段と
を備えた送信機の自動調整回路。
An SWR detection circuit, a π-type matching circuit consisting of a coil and two variable capacitors VC 1 and VC 2 , an output detection circuit, and an antenna are connected in series from the output side of the transmitter, and the output of the SWR detection circuit is connected to a reference voltage by a comparator. a driver that compares and supplies an output to a CPU, converts the output of the output detection circuit with an A/D converter and supplies it to the CPU as an output level, and connects the output of the CPU to the variable capacitor VC1 ;
M1 and a driver M2 connected to a variable capacitor VC2 are configured to tune the π-type matching circuit to match the transmission frequency, and while the SWR signal is at a level exceeding the reference value, the CPU supplies the signal to the driver M2 connected to the variable capacitor VC2. driver
a matching signal output means for operating M 1 and M 2 to output a matching signal that tunes the π-type matching circuit to the transmission frequency; and supplying the matching signal to one of the drivers M 1 or M 2 to adjust the output level. When the output level reaches the maximum, the matching signal switches to the other driver for matching, and when the output level reaches the maximum, the matching signal switches to one driver again.
An automatic adjustment circuit for a transmitter, comprising repeating matching means for alternately repeating matching and stopping and restoring matching when the SWR signal becomes less than a reference value.
JP311883U 1983-01-13 1983-01-13 Transmitter automatic adjustment circuit Granted JPS59108346U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP311883U JPS59108346U (en) 1983-01-13 1983-01-13 Transmitter automatic adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP311883U JPS59108346U (en) 1983-01-13 1983-01-13 Transmitter automatic adjustment circuit

Publications (2)

Publication Number Publication Date
JPS59108346U JPS59108346U (en) 1984-07-21
JPH0413855Y2 true JPH0413855Y2 (en) 1992-03-30

Family

ID=30134749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP311883U Granted JPS59108346U (en) 1983-01-13 1983-01-13 Transmitter automatic adjustment circuit

Country Status (1)

Country Link
JP (1) JPS59108346U (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1815603B1 (en) 2004-11-19 2014-09-17 Qualcomm Technologies, Inc. Device comprising a controlled matching stage
JP5167053B2 (en) * 2008-09-30 2013-03-21 吉川アールエフシステム株式会社 Automatic matching method and automatic matching circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS548909A (en) * 1977-06-22 1979-01-23 Patelhold Patentverwertung Automatic transmitter and antenna matching system
JPS5760739A (en) * 1980-09-29 1982-04-12 Nippon Telegr & Teleph Corp <Ntt> Transmission device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56116738U (en) * 1980-02-08 1981-09-07

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS548909A (en) * 1977-06-22 1979-01-23 Patelhold Patentverwertung Automatic transmitter and antenna matching system
JPS5760739A (en) * 1980-09-29 1982-04-12 Nippon Telegr & Teleph Corp <Ntt> Transmission device

Also Published As

Publication number Publication date
JPS59108346U (en) 1984-07-21

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