JP5167053B2 - Automatic matching method and automatic matching circuit - Google Patents

Description

  The present invention uses an automatic matching method and an automatic matching circuit that automatically match the output impedance on the high-frequency signal source side and the input impedance on the load side to increase transmission efficiency, and in particular, use a π match circuit that combines a coil and a capacitor. The present invention relates to a technique for automatically matching impedances between a high-frequency signal source side and a load side.

  Conventionally, techniques related to an automatic matching circuit are described in the following documents, for example.

JP-A-8-181626 JP-A-9-162757

  This Patent Document 1 describes a technique of a digital matching method in an antenna matching circuit having a π match circuit. Patent Document 2 describes a technique of a digital antenna matching device having a matching circuit in which a coil and a capacitor are combined.

  FIG. 25 is a schematic configuration diagram showing a matching circuit using a conventional π match circuit described in Patent Document 1 and the like.

  This matching circuit includes a π match circuit 2 connected between the drive source 1 and the load ZL. The drive source 1 includes a high-frequency signal source 1a and an equivalent signal source impedance Z, and a π match circuit 2 is connected to the output side. The π match circuit 2 includes a coil 2c having an inductance L connected between the input terminal 2a and the output terminal 2b, and a first capacitor of a variable capacitor C1 connected between the input terminal 2a and the reference potential line N1. 2d and a second capacitor 2e of a variable capacitor C2 connected between the output terminal 2b and the reference potential line N1. A load ZL is connected to the output terminal 2 b of the π match circuit 2.

  FIG. 26 is a Smith chart showing an example of the impedance matching range of the π match circuit 2 in the matching circuit of FIG.

  For example, the π match circuit 2 has an equivalent signal source impedance Z = 50Ω, the frequency of the signal source 1a is 13.56 MHz, the capacitance C1 of the capacitor 2d is 700 pF to 1750 pF, the capacitance C2 of the capacitor 2e is 270 pF to 2800 pF, and the coil 2c Inductance L = 0.2 μH. In the Smith chart of FIG. 26, the shaded portion A indicates the matching target range (matching target area), and the center point O indicates the impedance to be matched.

  In the π-match circuit 2 of FIG. 25, generally, the inductance L of the coil 2c is fixed or switched at a specific step, and the capacitances C1 and C2 of the capacitors 2d and 2e are adjusted, so that the impedance of the load ZL in a wide range can be increased. Matching with the impedance on the signal source 1a side of the range can be achieved.

  However, the conventional matching circuits described in Patent Documents 1 and 2 have the following problems (a) to (c).

(A) As shown in FIG. 26, in order to accurately convert the impedance of the wide matching target area A on the Smith chart to the center point O, it is necessary to finely adjust the wide area of the capacitors C1 and C2. . For example, a standing wave ratio (hereinafter referred to as “SWR”) indicating the relationship between a traveling wave and a reflected wave in a high-frequency transmission path is sufficiently reduced to reduce the reflection component to the load 3 in the matching target area A. In order to stably realize sufficient matching of 30 dB or more in return loss (loss), the capacitors C1 and C2 are respectively
C1 = 500 pF to 2000 pF
C2 = 200pF ~ 3000pF
Must be adjusted in small increments of about 5 pF. However, Patent Documents 1 and 2 do not disclose these specific adjustment methods.

  (B) For adjusting the capacitors C1 and C2, for example, if a variable capacitance diode is used, the circuit configuration is simplified. However, since the variable capacitance diode has a low breakdown voltage (for example, about 60V), if the level of the signal source 1a is large, a variable capacitance diode that is convenient for adjusting the capacitances C1 and C2 cannot be used. For this reason, it has been difficult to realize a circuit that has a relatively simple circuit configuration, a fast operation, and a high accuracy with a wide adjustment range and that finely and automatically adjusts the capacitors C1 and C2.

  (C) In order to reduce the reflection component by adjusting the capacitors 2d and 2e, it is difficult to automatically determine in which direction to increase / decrease the capacitances C1 and C2.

  (D) In order to solve the problems (b) and (c), in the techniques of Patent Documents 1 and 2, the impedance of the load 3 is measured to determine the matching circuit constant, or the coil 2c and the capacitor 2d, Various combinations of 2e are tried and the optimal combination is selected from them. However, this method has a problem in that it cannot cope with fluctuations in the load 3 during operation (during driving), and the circuit scale increases.

In the automatic matching method of the present invention, a variable first capacitor located on the high-frequency signal source side and a variable second capacitor located on the load side are connected to both ends of the fixed first coil. An automatic matching method for automatically matching the output impedance on the signal source side and the input impedance on the load side using a circuit, wherein a signal of a traveling wave component from the signal source toward the load and the load and detects the signal of the reflected wave component of a process of detecting a phase difference between the signal of the reflected wave component based on the signal of the incident-wave component, or the phase difference has a predetermined angle of lead or lag component And determining whether the output impedance and the input impedance are matched by increasing / decreasing the capacities of the first and second capacitors based on the determination result .
If the phase difference has a 90 ° lead component, the capacity of the first capacitor is increased. Conversely, if the phase difference has a 90 ° delay component, the capacity of the first capacitor is decreased. If the phase difference has a 45 ° delayed component, the capacity of the second capacitor is reduced. Conversely, if the phase difference has a 135 ° advanced (= 45 ° delayed reverse phase) component. The capacity of the second capacitor is increased.
Alternatively, if the phase difference has a 45 ° lead component, the capacity of the first capacitor is increased. Conversely, if the phase difference has a 135 ° delay component, the capacity of the first capacitor is decreased. If the phase difference has a 45 ° delayed component, the capacity of the second capacitor is reduced. Conversely, if the phase difference has a 135 ° advanced (= 45 ° delayed reverse phase) component. The capacity of the second capacitor is increased.

The automatic matching circuit according to the present invention includes a π match in which a variable first capacitor located on the high frequency signal source side and a variable second capacitor located on the load side are connected to both ends of the fixed first coil. And an automatic matching circuit that automatically matches the output impedance on the signal source side and the input impedance on the load side, and is connected between the signal source and the π match circuit. A directional coupler for detecting a traveling wave component signal from the source toward the load and a reflected wave component signal from the load; and a phase difference between the reflected wave component signal with reference to the traveling wave component signal. A phase detection circuit to detect, and whether or not the phase difference has an advance or delay component of a predetermined angle, and based on the determination result, the capacitances of the first and second capacitors are increased or decreased to determine the output impedance The above Determination control means for controlling the matching state with the force impedance .
The determination control means increases the capacity of the first capacitor if the phase difference has a 90 ° lead component, and conversely, if the phase difference has a 90 ° delay component, If the phase difference has a 45 ° delay component, the second capacitor is reduced. Conversely, the phase difference advances by 135 ° (= 45 ° delayed reverse phase). If it has a component, the capacity of the second capacitor is increased.
Alternatively, the determination control means increases the capacity of the first capacitor if the phase difference has a 45 ° advance component, and conversely, if the phase difference has a 135 ° delay component, If the phase difference has a 45 ° delay component, the second capacitor is reduced. Conversely, the phase difference advances by 135 ° (= 45 ° delayed reverse phase). If it has a component, the capacity of the second capacitor is increased.

  The automatic matching method and the automatic matching circuit according to the present invention are not limited to the variable capacitance in the π match circuit, which is set in advance according to conditions as in the prior art. When adjusting the capacity of the second capacitor, the adjustment direction is determined by looking at the phase difference, and the adjustment is not simply made to make the phase 0 ° as in the prior art. For this reason, even when the impedance of the load changes in a wide range, the matching can be automatically continued. Furthermore, adjustment can be performed while supplying a signal from a signal source to the load.

  In the best mode for carrying out the present invention, a π match circuit is used for impedance matching.

  When using a π-match circuit, if the load impedance (value at the connection point of the matching circuit, not the actual load, and varies depending on the cable length) is large, the Q when matched is high, depending on the application Band is too narrow. In order to achieve matching up to a range where the impedance of the load is low, the value of the inductance of the coil is reduced, so that the Q at a high impedance becomes higher. As a method for expanding the matching range, it is conceivable to change the inductance value of the variable coil or use a transformer.

  However, it is meaningless to use a variable coil with a large loss in the matching circuit for reducing the transmission loss, and there is a problem that it is difficult to obtain a transformer with a high frequency and a small loss.

  In view of the above, in the present invention, the best mode for realizing a practical automatic matching circuit will be apparent from the following description of the preferred embodiments with reference to the accompanying drawings. I will. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Example 1)
FIG. 1 is a schematic configuration diagram showing an automatic matching circuit according to a first embodiment of the present invention.

  The automatic matching circuit 10 is connected between a drive source 1 having a radio frequency (RF) signal source and a load 3 and automatically performs impedance matching when a power supply voltage VCC is applied from a power supply 4. And an input terminal 11 for inputting the high-frequency signal RFIN from the drive source 1 and an output terminal 12 for supplying the high-frequency signal RFOUT to the load 3. Here, the load 3 includes, for example, an antenna (ANT) and a transmission cable from the antenna (ANT) to the output terminal 12.

  A directional coupler 20 and a π match circuit 30 are cascaded between the input terminal 11 and the output terminal 12. The directional coupler 20 includes a high-frequency signal RFIN (ie, a traveling wave component signal) FWD from the driving source 1 toward the load 3 and a signal (ie, a reflected wave component) returned from the load 3 through the π match circuit 30. Signal) REF, and a π match circuit 30 is connected to the output side. The π match circuit 30 includes a coil 31 having an inductance L connected in series between the output side of the directional coupler 20 and the output terminal 12, and an input terminal of the coil 31 and a reference potential line N1 (for example, ground GND). ) And a second capacitor 33 of a variable capacitor C2 connected between the output terminal of the coil 31 and the ground GND.

  First and second phase detection circuits 40 and 50 are connected to output terminals of the signals FWD and REF in the directional coupler 20, and a correction direction determination circuit 60 is connected to the output side. The first phase detection circuit 40 detects the phase difference of the reflected wave component signal REF on the basis of the phase of the traveling wave component signal FWD (for example, the phase difference has a 90 ° advanced component or a 90 ° delayed component). This is a circuit for detecting whether or not the operation is being performed. The second phase detection circuit 50 detects the phase difference of the reflected wave component signal REF with reference to the phase of the traveling wave component signal FWD (for example, the phase difference is 45 ° delayed component or 135 ° advanced (45 ° It is a circuit that detects whether or not it has a negative phase component of delay). Based on the detection results of the phase detection circuits 40 and 50, the correction direction determination circuit 60 determines whether the phase correction direction with respect to the variable capacitors C1 and C2 of the π match circuit 30 is increased, decreased, or maintained as it is based on a predetermined reference. It is a circuit to do.

  Further, the automatic matching circuit 10 is provided with an oscillator 70 that outputs a timing signal (for example, a clock signal) CK at a constant time interval. The first and second outputs are connected to the output side of the oscillator 70 and the correction direction determination circuit 60. Variable capacitance control circuits 71 and 72 are connected. Based on the determination result of the correction direction determination circuit 60, the first variable capacitance control circuit 71 performs a π match at a predetermined time interval in order to reduce the amplitude of the signal of the reflected wave component REF (that is, to achieve matching). This is a circuit for controlling the variable capacitor C1 of the circuit 30. Similarly, the second variable capacitance control circuit 72 is based on the determination result of the correction direction determination circuit 60 to reduce the amplitude of the signal of the reflected wave component REF (that is, to achieve matching) at a predetermined time interval. , A circuit for controlling the variable capacitor C2 of the π match circuit 30. The correction direction determination circuit 60 and the first and second variable capacitance control circuits constitute determination control means.

FIG. 2 is a block diagram showing an example of the directional coupler 20 in FIG.
This directional coupler 20 has a conductive case 21 (for example, metal). In this case 21, a connector 22 that inputs a high frequency signal RFIN, a connector 23 that outputs a high frequency signal RFOUT, and a traveling wave component. A connector 24 that outputs a signal FWD and a connector 25 that outputs a reflected wave component signal REF are attached. One end of a coaxial cable (for example, 50Ω coaxial cable) 26 is connected to the connector 22, and only the core wire at the other end of the coaxial cable 26 is connected to the connector 23. Similarly, only the core wire of one end of a coaxial cable (for example, 50Ω coaxial cable) 27 is connected to the connector 25, and the other end of the coaxial cable 27 is connected to the connector 24.

  Ring-shaped toroidal cores 28 and 29 are mounted on the outer circumferences of the coaxial cables 26 and 27, respectively. The primary winding 28 a (for example, the number of turns 32 T) of one toroidal core 28 is connected in series between the case 21 and the connector 24. The primary winding 29 a (for example, the number of turns 32 T) of the other toroidal core 29 is connected between the core electrode of the connector 22 and the case 21.

  In this type of directional coupler 20, when the high frequency signal RFIN is input from the connector 22, the high frequency signal RFIN is output from the connector 23 through the core wire of the coaxial cable 26. At this time, since the core wire of the coaxial cable 26 passes through the toroidal core 28 as the primary side of the transformer composed of the toroidal core 28, the current flowing through the core wire of the coaxial cable 26 is attenuated by the number of windings and is secondary. Detected on the side. The voltage applied to the connector 22 is detected by a transformer composed of a toroidal core 29. Since the secondary side of the toroidal core 29 that detects the voltage component is equivalent to a winding having a winding number of 1 T by the coaxial cable 27, the secondary side is attenuated by the number of the primary winding 29 a and output between the connector 25 and the connector 24. The secondary side of the toroidal core 28 that has detected the current component is output to the core electrode of the connector 24 and the case 21. When the two connectors 24 and 25 are terminated with the characteristic impedance of the coaxial cable 27, the traveling wave component signal FWD is attenuated by the winding number ratio and output to one connector 24, and the reflected wave is output to the other connector 25. The component signal REF is attenuated by the winding ratio and output.

  Note that, depending on the connection of the directional coupler 20, the phases of the detected signals FWD and REF may be inverted. In this case, correction based on the inverted phase may be added.

FIG. 3 is a block diagram showing an example of the first or second capacitor 32, 33 in FIG.
Since the first capacitor 32 and the second capacitor 33 have the same configuration, the configuration of the first capacitor 32 will be described below.

  The first capacitor 32 includes a plurality of first unit capacitors 32a-1 to 32a-N connected in parallel to the signal line N2, and the first unit capacitors 32a1-1 to 32a-N and a reference. The first switch means (for example, a switch circuit) 32b connected between the ground line GND as the potential line N1. Each unit capacitor 32a-1 to 32a-N has a capacitance C1-1 to C1-N.

  The switch circuit 32b is a circuit that turns on / off the ground GND side of each of the unit capacitors 32a-1 to 32a-N based on the control signal from the first variable capacitance control circuit 71, and the switch speed may be slow. . The switch circuit 32b includes a switch element (for example, an NPN transistor) 32b-1 for turning on / off between the unit capacitors 32a-1 to 32a-N and the ground GND, and an emitter and an emitter of each NPN transistor 32b-1. A large-capacitance capacitor 32b-2 connected between the bases, a resistor 32b-3 connected between the base of each NPN transistor 32b-1 and the output side of the variable capacitance control circuit 71, and each NPN transistor 32b- It is composed of a plurality (N) sets of unit switch circuits including a resistor 32b-4 and a diode 32b-5 for applying a direct current (DC) bias voltage BV connected in series to one collector.

  Since the NPN transistor 32b-1 is used as the switch element, the parasitic capacitance can be made smaller than that using the MOS transistor. A large-capacitance capacitor 32b-2 inserted between the emitter and base of each NPN transistor 32b-1 has a function of blocking current flowing through each NPN transistor 32b-1 in the off state due to a large signal amplitude on the collector side. doing. This eliminates the need to make the drive impedance between the base and emitter of each NPN transistor 32b-1 sufficiently small in terms of DC. The resistor 32b-4 and the diode 32b-5 provided in each bias circuit reduce the parasitic capacitance between the collector and the base by applying a high DC bias voltage BV to the collector of each NPN transistor 32b-1. There is a function that enables matching even in a wide range of impedance (lower left area in the Smith chart).

  Each unit capacitor 32a-1 to 32a-N needs a resolution of about 10 bits, for example, but in the first embodiment, the change width of 3000 pF is realized in steps of 5 pF or less. Since each unit capacitor 32a-1 to 32a-N is a drive system, it is necessary to use a high withstand voltage capacitor. For example, if 50W system is 10W, a withstand voltage of 60Vpp is required as a reference (double + margin). is there. Furthermore, when realizing 10 bits straight, a capacitor with a variation width sufficiently smaller than 0.1% is required, but by increasing the capacitance ratio of the capacitor array to 1.8 times, a general 5% product is required. This can be realized by increasing the number of bits by using. The diode 32b-5 provided in each bias circuit has a function of reducing a load on a high frequency and suppressing the DC bias voltage BV from excessively increasing.

  Although not shown, the second capacitor 33 is connected between the plurality of second unit capacitors connected in parallel to the signal line and the ground as the reference potential node. It is constituted by connected second switch means (for example, a switch circuit).

FIG. 4 is a schematic configuration diagram showing a circuit example of a main part of FIG.
The first phase detection circuit 40 includes a phase shift circuit 41 that advances the phase of the traveling wave component signal FWD by 90 °, and a phase comparison that compares the phases of the output signal of the phase shift circuit 41 and the reflected wave component signal REF. The circuit 42 is configured. In substantially the same manner, the second phase detection circuit 50 delays the phase of the traveling wave component signal FWD by 45 °, and the phase of the output signal of the phase shifting circuit 51 and the reflected wave component signal REF. And a phase comparison circuit 52 for comparison. A correction direction determination circuit 60 is connected to the output side of these phase detection circuits 40 and 50.

  The correction direction determination circuit 60 includes first and second voltage comparators (voltage comparison circuits) 61 and 62 for comparing the output voltage of the phase comparison circuit 42 with the first and second reference voltages Vth1 and Vth2, respectively. The output voltage of the comparison circuit 52 is composed of third and fourth voltage comparison circuits 63 and 64 for comparing the third and fourth reference voltages Vth3 and Vth4, respectively. Two variable capacitance control circuits 71 and 72 are connected to each other.

  The first variable capacitance control circuit 71 is constituted by, for example, an up (UP) / down (DOWN) counter, and is incremented (UP) by an output signal of the first voltage comparison circuit 61 in synchronization with the clock signal CK. When the signal is decremented (DOWN) by the output signal of the second voltage comparison circuit 62 and there is no signal from both the first and second voltage comparison circuits 61 and 62 (that is, there is no phase difference component of 90 °). Is a circuit that enters a hold (HOLD) state without up or down, and controls the variable capacitance C1 of the first capacitor 32 based on the count result of a plurality of bits. Similarly, the second variable capacitance control circuit 72 is configured by, for example, an up (UP) / down (DOWN) counter, and is incremented by an output signal of the third voltage comparison circuit 63 in synchronization with the clock signal CK ( UP), and is decremented (DOWN) by the output signal of the fourth voltage comparison circuit 64, and there is no signal from both the first and second voltage comparison circuits 63 and 64 (that is, a phase difference component of 90 ° is present). In this case, the circuit is in a hold (HOLD) state without being up or down, and controls the variable capacitor C2 of the second capacitor 33 based on the count result of a plurality of bits.

  5A to 5C are configuration diagrams illustrating an example of the phase shift circuit 41 in FIG.

FIG. 5A is a configuration diagram illustrating an example of a phase shift circuit (phase shift 90 ° advance).
In the phase shift circuit 41, a capacitor 41a (capacitance C) and a resistor 41b (resistance value R) are connected in series between a terminal of the input signal IN and a terminal of the inverted input signal IN /. An output signal OUT having a phase advanced by 90 ° with respect to the input signal IN is output from the connection point of the resistor 41b. The relationship between the operating frequency f and C, R is
f = 1 / (2πCR)
It is.

FIG. 5B is a configuration diagram illustrating an example of a phase shift circuit (phase shift 90 ° delayed).
In the phase shift circuit 41, a resistor 41b (resistance value R) and a capacitor 41a (capacitance C) are connected in series between the terminal of the input signal IN and the terminal of the inverted input signal IN /. An output signal OUT whose phase is delayed by 90 ° with respect to the input signal IN is output from the connection point of the capacitor 41a. The relationship between the operating frequency f and C, R is
f = 1 / (2πCR)
It is.

FIG. 5A is a configuration diagram illustrating an example of a phase shift circuit (phase shift 90 ° advance).
The phase shift circuit 41 is a 90 ° phase advance circuit using LC resonance, and a resistor 41b (resistance value R) and a capacitor 41a (capacitance C) are provided between the input signal IN terminal and the output signal OUT terminal. Are connected in series, and a coil 41c (inductance L) is further connected between the capacitor 41a and the ground GND, and the phase of the input signal IN is 90 ° from the connection point between the capacitor 41a and the coil 41c. The advanced output signal OUT is output. The relationship between the resistance value R, the impedance 2πfL of the coil 41c (where the resonance frequency f = 1 / (2π√ (LC)), and the impedance 1 / (2πfC) of the capacitor 41a is
R ≧ 2πfL = 1 / (2πfC)
When the resistance value R is increased, the Q is lowered and the resonance is stabilized, but the amplitude of the output signal OUT is decreased.

FIG. 5B is a configuration diagram illustrating an example of a phase shift circuit (phase shift 90 ° delayed).
The phase shift circuit 41 is a 90 ° phase lag circuit using LC resonance, and a resistor 41b (resistance value R) and a coil 41c (inductance L) are provided between the input signal IN terminal and the output signal OUT terminal. Are connected in series, and a capacitor 41a (capacitance C) is connected between the coil 41c and the ground GND, and 90 ° phase with respect to the input signal IN from the connection point of the coil 41c and the capacitor 41a. The output signal OUT is delayed. The relationship between the resistance value R, the impedance 2πfL of the coil 41c (where the resonance frequency f = 1 / (2π√ (LC)), and the impedance 1 / (2πfC) of the capacitor 41a is
R ≧ 2πfL = 1 / (2πfC)
When the resistance value R is increased, the Q is lowered and the resonance is stabilized, but the amplitude of the output signal OUT is decreased.

FIG. 5C is a configuration diagram illustrating an example of a phase shift circuit (phase shift 45 ° delayed).
In the phase shift circuit 41, a resistor 41b (resistance value R) and a capacitor 41a (capacitance C) are connected in series between the terminal of the input signal IN and the ground GND, and a connection point between the resistor 41b and the capacitor 41a. Thus, an output signal OUT having a 45 ° phase delay with respect to the input signal IN is output. The relationship between the operating frequency f and C, R is
f = 1 / (2πCR)
It is.

FIG. 5C is a configuration diagram illustrating an example of a phase shift circuit (phase shift 45 ° advance).
In the phase shift circuit 41, a capacitor 41a (capacitance C) and a resistor 41b (resistance value R) are connected in series between the terminal of the input signal IN and the ground GND, and a connection point between the capacitor 41a and the resistor 41b. Therefore, an output signal OUT whose phase is advanced by 45 ° with respect to the input signal IN is output. The relationship between the operating frequency f and C, R is
f = 1 / (2πCR)
It is.

FIG. 6 is a block diagram showing an example of the first and second phase comparison circuits 42 and 52 in FIG.
Since the first phase comparison circuit 42 and the second phase comparison circuit 52 have the same configuration, the configuration of the first phase comparison circuit 42 will be described below.

  The first phase comparison circuit 42 is a phase comparison circuit using dual differential transistors, and includes a resistor 42a that generates a constant current from the power supply voltage VCC, and N-channel MOS transistors (hereinafter referred to as “NMOS”) 42b and 42m. P channel MOS transistors (hereinafter referred to as “PMOS”) 42c and 42d for differential amplification stage, NMOS 42e and 42f for signal FWD input of differential amplification stage, and NMOS 42g for inverted signal FWD / input, 42h, an NMOS 42k for signal REF input, and an NMOS 42j for inverted signal REF / input.

  In the first phase comparison circuit 42, when the traveling wave component signals FWD and FWD / and the reflected wave component signal REF are input, the signals FWD and FWD / are differentially generated by the NMOSs 42e, 42f, 42g, and 42h. At the same time, the signals REF and REF / are differentially amplified by the NMOSs 42i and 42j, and an output signal (output voltage) OUT as a comparison result obtained by comparing the phases of the signals FWD and REF is obtained from the connection point between the PMOS 42d and the NMOS 42f. Is output.

(Outline of automatic alignment method of embodiment 1)
When the high frequency signal RFIN output from the drive source 1 of FIG. 1 is input to the input terminal 11 of the automatic matching circuit 10, the load 3 is transmitted from the input terminal 11 via the π match circuit 30 by the directional coupler 20. A traveling wave component signal FWD heading toward the output terminal 12 on the side and a reflected wave component signal REF sent from the output terminal 12 on the load side via the π match circuit 30 are detected, and the signals FWD and REF are detected. Are sent to the first and second phase detection circuits 40 and 50. The first and second phase detection circuits 40 and 50 detect the phase difference of the reflected wave component signal REF with reference to the traveling wave component signal FWD, and send the detection result to the correction direction determination circuit 60. The correction direction determination circuit 60 determines whether or not the phase difference given from the first and second phase detection circuits 40 and 50 has an advance or delay component of a predetermined angle, and the determination result is determined as the first and first. 2 variable capacity control circuits 71 and 72. The first and second variable capacitance control circuits 71 and 72 increase or decrease the variable capacitances C1 and C2 of the first and second capacitors based on the determination result, and the output impedance of the drive source 1 and the input of the load 3 Match impedance.

  For example, the correction direction determination circuit 60 and the first and second variable capacitance control circuits 71 and 72 increase the variable capacitance C1 of the first capacitor 32 if the phase difference has a 90 ° advance component, and conversely, If the phase difference has a 90 ° delay component, the variable capacitor C1 is reduced. If the phase difference has a 45 ° delay component, the variable capacitor C2 of the second capacitor 33 is reduced. Conversely, the phase difference is 135 °. If it has an advanced component (reverse phase delayed by 45 °), the variable capacitor C2 is increased to achieve impedance matching.

(Details of automatic alignment method of embodiment 1)
7 and 8 are Smith charts showing a method of adjusting the variable capacitors C1 and C2 of the first and second capacitors 32 and 33 in FIG.

  The automatic alignment method of FIGS. 1 and 4 is processed, for example, by repeating the following steps S1 to S3.

Step S1:
Wait for the rising edge of the clock signal CK output from the oscillator 70. During this time, the first and second phase detection circuits 40 and 50 and the correction direction determination circuit 60 operate continuously as follows, and converge to an output value corresponding to the matching state in this state.

  The first and second phase detection circuits 40 and 50 detect the phase difference of the reflected wave component signal REF based on the traveling wave component signal FWD, and send the phase difference detection result to the correction direction determination circuit 60. The correction direction determination circuit 60 receives the phase difference detection result, and determines whether to increase, decrease, or maintain the current state of the π match circuit 30 with respect to the variable capacitors C1 and C2 based on the reference shown in the Smith charts of FIGS.

The criteria shown in the Smith charts of FIGS. 7 and 8 will be described.
In the Smith chart of FIG. 7, an arrow 80 is an axis showing the same phase as the input high-frequency signal RFIN, an arrow 81 is an axis showing a phase advanced by 90 ° from the high-frequency signal RFIN, and an arrow 82 is a phase delayed by 90 ° from the high-frequency signal RFIN. An arrow 83 indicates an inversion phase with respect to the high frequency signal RFIN. An arrow 84 indicates an impedance shift direction viewed from the drive source 1 side due to the change of the variable capacitor C1, and an arrow 85 indicates an impedance shift direction viewed from the drive source 1 side due to the change of the variable capacitor C2.

  Therefore, the phase detection circuits 40 and 50 detect the phase of the reflected wave component signal REF that changes according to the phase of the load 3 with respect to the input high-frequency signal RFIN, and the correction direction determination circuit 60 and the variable capacitance control circuit 71. , 72 determines the adjustment direction of the variable capacitors C1, C2. In FIG. 7, the case where the load impedance seen at the output point of the directional coupler 20 is indicated by a point XX is taken as an example. This is an example in which the phase of the reflected wave component signal REF is delayed by 45 ° with respect to the phase of the traveling wave component signal FWD, and is not matched because it is off the center point of the Smith chart. Regarding the variable capacity C1, since it is determined that there is a 90 ° delay component based on the reference of 90 ° delay or advance (ie, it is determined whether the load 3 is C-type or L-type), it is determined to be reduced, and the variable capacitance Regarding C2, since it is determined that there is a 45 ° delay component based on the 45 ° delay or 135 ° advance criterion, it is determined that it is reduced.

  In the Smith chart of FIG. 8, the phase of the reflected wave component signal REF is determined by the first phase detection circuit 40 on the basis of the signal whose phase is 90 ° from the traveling wave component signal FWD, and the Smith chart of FIG. Above, it is determined whether the alignment state is above or below the broken line 86 or above the broken line 86. For example, the area above the broken line 86 is determined to increase the variable capacity C1, the area below the broken line 86 is determined to decrease the variable capacity C1, and if the area is on the broken line 86, it is determined that the variable capacity C1 is maintained. . Further, the phase of the reflected wave component signal REF is determined by the second phase detection circuit 50 on the basis of the signal delayed by 45 ° from the traveling wave component signal FWD, and the matching state is shown on the Smith chart of FIG. Is located on the upper left, lower right or on the two-dot chain line 87 from the two-dot chain line 87. For example, the area on the upper left side of the two-dot chain line 87 is determined to increase the variable capacitance C2, and the area on the lower right side of the two-dot chain line 87 is determined to decrease the variable capacity C2. Is determined. In this way, not only the increase / decrease but also the determination of the current status is performed.

Step S2:
At the rising edge of the clock signal CK, the phase detection results of the first and second phase detection circuits 40 and 50 are taken into the correction direction determination circuit 60, and the determination results of the correction direction determination circuit 60 are the first and second. To the variable capacitance control circuits 71 and 72.

Step S3:
Depending on the determination result of the correction direction determination circuit 60, the control data of the first and second variable capacitance control circuits 71 and 72 is changed or held one step up or down, and the unit capacitor 32a- 1 to 32a-N is controlled to adjust the variable capacitors C1 and C2.

  If the above steps S1 to S3 are repeated, the output impedance of the drive source 1 and the impedance of the load 3 viewed from the output terminal 12 of the automatic matching circuit 10 are matched.

(Effect of Example 1)
According to the first embodiment, there are the following effects (a) and (b).

  (A) As in the prior art, the variable capacitance in the π match circuit is not only set to a set value prepared in advance according to the conditions, but the first and second capacitors 32 and 33 for reducing the reflection component are variable. When adjusting the capacitors C1 and C2, the adjustment direction is determined by the phase detection circuits 40 and 50 and the correction direction determination circuit 60, and the phase is simply set to 0 ° as in the prior art. I have not made any adjustments. Therefore, even if the impedance of the load 3 changes in a wide range, the matching can be automatically continued. Furthermore, adjustment can be performed while supplying the signal of the drive source 1 to the load 3.

  (B) Due to the effect of (a), for example, the load 3 is an antenna, which is suitable for applications where the environment around the antenna changes, or when the cable length to the mismatched load 3 is switched. Further, it can cope with the signal output of a high output transmitter.

(Modification 1 of Example 1)
FIG. 9 is a configuration diagram illustrating a first modification of the first capacitor 32 in FIG. 3.

  In the first capacitor 32 of FIG. 9, a switch 32b-6 is newly connected in series to the diode 32b-5 constituting the bias circuit of each stage. The switch 32b-6 at each stage is ON / OFF controlled complementarily to the NPN transistor 32b-1 by control means (not shown). That is, when the NPN transistor 32b-1 is on, the switch 32b-6 is turned off, and the application of the DC bias voltage BV to the NPN transistor 32b-1 is cut off. Thereby, power consumption can be reduced.

(Modification 2 of Example 1)
FIG. 10 is a configuration diagram showing a second modification of the unit capacitors 32a-1 to 32a-N in FIG.

  If each unit capacitor 32a-1 to 32a-N in FIG. 3 is a small signal, it may be replaced with a variable capacitance diode 32c-1. The capacitance of the variable capacitance diode 32c-1 at each stage changes depending on the control voltage supplied from the variable capacitance control circuit 71 via the resistor 32c-2, for example. If such a variable capacitance diode 32c-1 is used, the circuit configuration is simplified.

(Modification 3 of Example 1)
FIG. 11 is a configuration diagram illustrating a third modification of the first capacitor 32 in FIG. 3.

  The switch circuit 32b shown in FIG. 3 may be realized by a switch circuit 32d including MOS transistors 32d-1 in place of the low-frequency switch circuit 32b. The MOS transistor 32d-1 at each stage is on / off controlled by a control voltage supplied from the variable capacitance control circuit 71. If such a switch circuit 32d is used, the circuit configuration is simplified and the integration into an integrated circuit is facilitated.

(Modification 4 of Example 1)
FIG. 12 is a configuration diagram illustrating a fourth modification of the first capacitor 32 in FIG. 3.

  The switch circuit 32b in FIG. 3 may be realized by a switch circuit 32e in which each stage is formed of a photo MOS relay instead of the low-frequency switch circuit 32b. The photo MOS relay at each stage is variable between the two photo MOS transistors 32e-1 and 32e-2 connected in series between the unit capacitors 32a-1 to 32a-N at each stage and the ground GND, and the ground GND. A photodiode 32e-3 and a resistor 32e-4 are connected in series with the output side of the capacitance control circuit 71. The photodiode 32e-3 at each stage emits / extinguishes with the control voltage supplied from the variable capacitance control circuit 71 through the resistor 32e-4, and the photoMOS transistors 32e-1 and 32e-2 are turned on / off by the light emission. Controlled off. If such a switch circuit 32e is used, the path on the output side of the variable capacitance control circuit 71 and the path on the unit capacitor 32a-1 to 32a-N side are electrically cut off. The influence of noise can be prevented and the reliability is improved.

(Configuration of Example 2)
FIG. 13 is a schematic configuration diagram illustrating an automatic matching circuit according to the second embodiment of the present invention. Elements common to the elements in FIG. 1 illustrating the first embodiment are denoted by common reference numerals.

  This automatic matching circuit 10A is a circuit in which the detection phase in the automatic matching circuit 10 of the first embodiment is practically modified. The first and second phase detection circuits 40 and 50 and the correction direction determination circuit 60 of the first embodiment. Instead of these, first and second phase detection circuits 40A and 50A and a correction direction determination circuit 60A having different functions are provided.

  The first phase detection circuit 40A detects the phase difference of the reflected wave component signal REF with reference to the phase of the traveling wave component signal FWD output from the directional coupler 20 (for example, the phase difference advances by 45 °). Component, or a circuit that detects whether or not it has a 135 ° delay component). The second phase detection circuit 50A detects the phase difference of the reflected wave component signal REF with reference to the phase of the traveling wave component signal FWD (for example, the phase difference is 45 ° delayed component or 135 ° advanced (45 ° It is a circuit that detects whether or not it has a negative phase component of delay). Based on the detection results of the phase detection circuits 40A and 50A, the correction direction determination circuit 60A determines whether the phase correction direction with respect to the variable capacitors C1 and C2 of the π match circuit 30 increases, decreases, or maintains the current state based on the detection results. It is a circuit to do.

Other configurations are the same as those of the first embodiment.
(Outline of automatic alignment method of embodiment 2)

  As in the first embodiment, when the high frequency signal RFIN output from the drive source 1 in FIG. 13 is input to the input terminal 11 of the automatic matching circuit 10A, the directional coupler 20 causes a π match from the input terminal 11. A traveling wave component signal FWD directed to the output terminal 12 on the load 3 side via the circuit 30 and a reflected wave component signal REF sent from the output terminal 12 on the load side via the π match circuit 30 The signals FWD and REF are detected and sent to the first and second phase detection circuits 40A and 50A. The first and second phase detection circuits 40A and 50A detect the phase difference of the reflected wave component signal REF with reference to the traveling wave component signal FWD, and send the detection result to the correction direction determination circuit 60A. The correction direction determination circuit 60A determines whether or not the phase difference given from the first and second phase detection circuits 40A and 50A has an advance or delay component of a predetermined angle, and the determination result is determined as the first and the second. 2 variable capacity control circuits 71 and 72. Based on the determination result, the first and second variable capacitance control circuits 71 and 72 increase or decrease the variable capacitances C1 and C2 of the first and second capacitors to increase the output impedance of the drive source 1 and the input of the load 12. Match impedance.

  For example, the correction direction determination circuit 60A and the first and second variable capacitance control circuits 71 and 72 increase the variable capacitance C1 of the first capacitor 32 if the phase difference has a 45 ° advance component, and conversely, If the phase difference has a 135 ° delay component, the variable capacitor C1 is reduced. If the phase difference has a 45 ° delay component, the variable capacitor C2 of the second capacitor 33 is reduced. Conversely, the phase difference is 135 °. If it has an advanced component (reverse phase delayed by 45 °), the variable capacitor C2 is increased to perform impedance matching.

(Details of automatic alignment method of embodiment 2)
FIGS. 14 and 15 are Smith charts showing adjustment methods for the variable capacitors C1 and C2 of the first and second capacitors 32 and 33 in FIG. 13, and the elements in FIGS. 7 and 8 showing the first embodiment. Common elements are denoted by common reference numerals.

  The automatic alignment method according to the second embodiment is processed in the same manner as in the first embodiment, for example, by repeating the following steps S1 to S3.

Step S1:
Wait for the rising edge of the clock signal CK output from the oscillator 70. During this time, the first and second phase detection circuits 40A and 50A and the correction direction determination circuit 60A continuously operate as follows, and converge to an output value corresponding to the matching state in this state.

  The first and second phase detection circuits 40A and 50A detect the phase difference of the reflected wave component signal REF with reference to the traveling wave component signal FWD, and send the phase difference detection result to the correction direction determination circuit 60A. The correction direction determination circuit 60A receives the phase difference detection result, and determines whether to increase, decrease, or maintain the current state of the π match circuit 30 with respect to the variable capacitors C1 and C2, based on the reference shown in the Smith charts of FIGS.

Similar to FIGS. 7 and 8, the criteria shown in the Smith charts of FIGS. 14 and 15 will be described.
In the Smith chart of FIG. 14, as in the first embodiment, the arrow 84 indicates the direction of impedance shift as viewed from the drive source 1 side with the change of the variable capacitor C1, and the arrow 85 indicates the change of the variable capacitor C2. An impedance deviation direction viewed from the drive source 1 side is shown.

  Therefore, the phase detection circuit 40A, 50A detects the phase of the reflected wave component signal REF that changes according to the phase of the load 3 with respect to the input high-frequency signal RFIN, and the correction direction determination circuit 60A and the variable capacitance control circuit. The variable capacitors C1 and C2 are adjusted by 71 and 72, respectively.

  Since the arrow 84 and the arrow 85 are not orthogonal and have components that interfere with each other, the variable capacitor C1 is detected by a phase axis that is 45 ° advanced, and the variable capacitor C2 is detected by a phase axis that is delayed by 45 °. .

  In the Smith chart of FIG. 15, the phase of the reflected wave component signal REF is determined by the first phase detection circuit 40A with reference to a signal whose phase is 45 ° ahead of the traveling wave component signal FWD, and the Smith chart of FIG. Above, it is determined whether the alignment state is on the upper right, lower left or on the broken line 88 from the broken line 88. For example, the area on the upper right side of the broken line 88 is determined to increase the variable capacity C1, the area on the lower left side of the broken line 88 is determined to decrease the variable capacity C1, and the variable capacity C1 is determined to be maintained as it is on the line of the broken line 88. . Further, the phase of the reflected wave component signal REF is determined by the second phase detection circuit 50A on the basis of the signal delayed by 45 ° from the traveling wave component signal FWD, and the matching state is shown on the Smith chart of FIG. Is located on the upper left, lower right, or on the two-dot chain line 87 from the two-dot chain line 87. For example, the area on the upper left side of the two-dot chain line 87 is determined to increase the variable capacity C2, and the area on the lower right side of the two-dot chain line 87 is determined to decrease the variable capacity C2. C2 is determined to be the current status. In this way, not only the increase / decrease but also the determination of the current status is performed.

Step S2:
At the rising edge of the clock signal CK, the phase detection results of the first and second phase detection circuits 40A and 50A are taken into the correction direction determination circuit 60A, and the determination results of the correction direction determination circuit 60A are the first and second. To the variable capacitance control circuits 71 and 72.

Step S3:
Depending on the determination result of the correction direction determination circuit 60A, the control data of the first and second variable capacitance control circuits 71 and 72 is changed or held one step up or down, and the switch circuit 32b changes the variable capacitance C1, Adjust C2.

  If the above steps S1 to S3 are repeated, the output impedance of the driving source 1 and the impedance of the load 3 viewed from the output terminal 12 of the automatic matching circuit 10A match.

(Effect of Example 2)
According to the second embodiment, there are almost the same effects as the first embodiment.

(Modification of Example 2)
In the second embodiment, the first to fourth modifications of the first embodiment can be similarly applied.

  FIG. 16 is a schematic configuration diagram illustrating an automatic matching circuit according to the third embodiment of the present invention. Elements common to those in FIG. 1 illustrating the first embodiment are denoted by common reference numerals.

  In the automatic matching circuit 10B according to the third embodiment, a level ratio detection circuit 90 is added to the automatic matching circuit 10 according to the first embodiment, and instead of the first and second variable capacitance control circuits 71 and 72 according to the first embodiment. , There are provided first and second variable capacitance control circuits 71B and 72B having different functions.

  In the automatic matching circuit 10B, if a good match is obtained, the reflected wave component signal REF becomes small and an error in phase detection increases, so that an erroneous determination of the adjustment direction for the variable capacitors C1 and C2 is likely to occur. Therefore, the level ratio detection circuit 90 detects the level ratio between the traveling wave component signal FWD and the reflected wave component signal REF, and when the level ratio becomes smaller than a predetermined value, the level ratio detection circuit 90 applies to the variable capacitance control circuits 71B and 72B. And has a function of stopping the alignment operation.

Other configurations are the same as those of the first embodiment.
FIG. 17 is a schematic configuration diagram illustrating a circuit example of a main part of FIG.

  The level ratio detection circuit 90 includes first and second signal level detection circuits 91 and 92, a voltage detection circuit 93 connected to the output side, and a voltage comparison circuit 94 connected to the output side of the voltage detection circuit 93. It is comprised by.

  The first signal level detection circuit 91 is a circuit for detecting the level of the traveling wave component signal FWD output from the directional coupler 20, and is a level detection circuit (Received Signal Strength Indicator, hereinafter referred to as “RSSI”) having a large dynamic range. Circuit ”) and the like. The second signal level detection circuit 92 is a circuit that detects the level of the reflected wave component output from the directional coupler 20 in the signal FWD, and is configured by an RSSI circuit or the like. Since the first and second signal level detection circuits 91 and 92 perform so-called LOG detection that is detected according to the logarithm of the signal level of the input signal, the signal level ratio can be detected by obtaining the difference between the outputs.

  The voltage detection circuit 93 is a circuit that detects a voltage having a ratio between the signal level detected by the first signal level detection circuit 91 and the signal level detected by the second signal level detection circuit 92, and is an operational amplifier. (OPAMP) subtracting circuit or the like.

  The voltage comparison circuit 94 compares the detection result of the voltage detection circuit 93 with the reference voltage Vth5, and when the level ratio between the traveling wave component signal FWD and the reflected wave component signal REF is equal to or higher than a predetermined value (that is, matching can be achieved). And the operation of the variable capacitance control circuits 71B and 72B is set to the hold (HOLD) mode so as to hold (HOLD) the control data for controlling the variable capacitors C1 and C2. The first and second variable capacitance control circuits 71B and 72B are configured by an up / down counter having a hold mode function.

(Automatic alignment method of Example 3)
FIG. 18 is a flowchart showing the processing procedure of the automatic matching method in the automatic matching circuit 10B of FIGS.

  While the clock signal CK output from the oscillator 70 is waiting to rise (step S11), the phase detection circuits 40 and 50, the level ratio detection circuit 90, and the correction direction determination circuit 60 operate continuously, and the matching state in this state It converges to the output value according to. When the clock signal CK rises, the variable capacitance control circuits 71B and 72B capture the detection results of the level ratio detection circuit 90, and the correction direction determination circuit 60 captures the detection results of the first and second phase detection circuits 40 and 50. (Step S12).

  Next, it is determined whether or not the level ratio between the traveling wave component signal FWD and the reflected wave component signal REF output from the directional coupler 20 is equal to or higher than a predetermined value by the matching determination process by the level ratio detection circuit 90 (that is, It is determined whether or not matching is achieved (step S13). When matching is achieved (Yes in step S13), the operations of the variable capacitance control circuits 71B and 72B are set as data hold and are not changed. On the other hand, if the matching is not achieved (No in step S13), the control data of the variable capacitance control circuits 71B and 72B is changed up or down by one step or one according to the determination result of the correction direction determination circuit 60. Is held and the variable capacitors C1 and C2 are adjusted.

  These processes in steps S11 to S15 are repeated to obtain a desired alignment state.

(Effect of Example 3)
According to the third embodiment, since the level ratio detection circuit 90 looks at the signal level ratio and stops the matching operation, erroneous determination of the adjustment direction with respect to the variable capacitors C1 and C2 can be prevented.

(Modification of Example 3)
In the third embodiment, the first to fourth modifications of the first embodiment can be similarly applied.

(Configuration of Example 4)
FIG. 19 is a schematic configuration diagram showing an automatic matching circuit according to the fourth embodiment of the present invention. Elements common to those in FIG. 16 showing the third embodiment are denoted by common reference numerals.

  In the automatic matching circuit 10C according to the fourth embodiment, instead of the π match circuit 30 in the automatic matching circuit 10B according to the third embodiment, a π match circuit 30C having a different configuration is provided. A switch control circuit 73 for controlling is added.

  The π match circuit 30C is similar to the coil 31 and the first and second capacitors 32 and 33 in the third embodiment, and a transformer (hereinafter referred to as “transformer”) in which the primary winding side is connected to the coil 31 in parallel. ) 34 and a switch (SW) 35 for releasing / short-circuiting (short-circuiting) the secondary winding side of the transformer 34. The switch control circuit 73 inputs the clock signal CK output from the oscillator 70, the control data of the first variable capacitance control circuit 71B, and the detection result of the level ratio detection circuit 90, and controls on / off of the switch 35. The SW control signal 73a is output and has the following functions.

  That is, the switch control circuit 73 determines that the matching is achieved, the reflection component signal REF output from the directional coupler 20 is sufficiently smaller than the traveling wave component signal FWD, and the level ratio detection circuit 90 is matched. Even when the variable capacitance C1 of the first capacitor 32 is smaller than the predetermined lower limit value, it is determined that the value of the inductance L of the coil 31 is too large, and the switch 35 is turned on to decrease the value of the inductance L. To do. If the value of the inductance L is already small, it is left as it is because the matching adjustment range is limited. Even if it is determined that the reflection component signal REF output from the directional coupler 20 is sufficiently smaller than the traveling wave component signal FWD and the level ratio detection circuit 90 determines that the matching is achieved, the first capacitor If the variable capacity C1 of 32 is larger than the predetermined upper limit value, it is determined that the value of the inductance L of the coil 31 is too small, and the switch 35 is turned off to increase the value of the inductance L. If the value of the inductance L is already large, it is left as it is because the matching adjustment range is limited. Furthermore, the switch control circuit 73 counts the number of clocks of the clock signal CK, detects a period in which the state of non-matching continues continuously, and if the matching is not achieved even if the predetermined number of clocks is exceeded. The value of the inductance L is determined to be inappropriate, and the switch 35 is controlled to switch the value of the inductance L.

(Outline of Automatic Matching Method of Example 4)
In the automatic matching circuit 10C of the fourth embodiment, the primary winding of the transformer 34 is short-circuited by using the switch 35 controlled by the SW control signal 73a of the switch control circuit 73 to short-circuit the secondary winding of the transformer 34. The value of the inductance L viewed from the side is switched. The switching control is determined by the value of the variable capacitor C1 in the first capacitor 32. When the variable capacitance C1 becomes a value smaller than a predetermined value, the value of the inductance L is switched to make it smaller. Conversely, when the variable capacitor C1 is larger than a predetermined value, the value of the inductance L is switched and increased. When the matching cannot be achieved, the value of the inductance L is switched regardless of the condition of the variable capacitor C1. The principle of this method is as follows.

  When the number of turns (number of turns) in the secondary winding of the transformer 34 is increased, the change width of the inductance L increases and the withstand voltage requirement of the switch 35 increases, but the on-resistance value requirement of the switch 35 becomes loose. Become.

In the π match circuit 30C, the relationship between the minimum pure resistance load (resistance value Rmin) that can be matched and the value of the inductance L is given by the following equation.
Rmin = (XL) ² / Zo
However, coil impedance XL = 2πfL
f: Signal frequency
Zo: Characteristic impedance (usually 50Ω)

  In order to expand the matching range in a small direction, it is necessary to reduce the value of the inductance L. At this time, since the variable capacitance C1 of the first capacitor 32 also becomes the minimum value, when the variable capacitance C1 becomes a value smaller than a predetermined value, the value of the inductance L is switched to be small. Conversely, when the variable capacitor C1 is larger than a predetermined value, the value of the inductance L is switched and increased. If the value of the inductance L is selected to be small, matching can be achieved over a wide range of loads. However, if matching is performed with a load having a large impedance in this state, the Q of the automatic matching circuit 10C increases and the band is narrowed. It is desirable to select a value of the inductance L according to the required band.

  If matching is not achieved after a predetermined time has elapsed, the value of the inductance L is switched regardless of the condition of the variable capacitor C1. Since the variable capacitor C2 of the second capacitor 33 varies greatly due to the phase variation of the load 3, it is not used for the determination of switching the inductance L.

  The winding of the transformer 35 is desirably made of a wire material having a sufficiently low high-frequency resistance in order to reduce loss due to the current flowing in the secondary winding.

(Details of automatic alignment method of embodiment 4)
FIG. 20 is a flowchart showing the processing procedure of the automatic matching method in the automatic matching circuit 10C of FIG.

  While the clock signal CK output from the oscillator 70 is waiting to rise (step S21), the phase detection circuits 40 and 50, the level ratio detection circuit 90, and the correction direction determination circuit 60 operate continuously, and the matching state in this state It converges to the output value according to. When the clock signal CK rises, the detection results of the level ratio detection circuit 90 are taken in by the variable capacitance control circuits 71B and 72B and the switch control circuit 73, and the detection results of the first and second phase detection circuits 40 and 50 are corrected. The determination circuit 60 takes in, and the switch control circuit 73 increases the execution history count of the control step number N by 1 (step S12). The level ratio between the traveling wave component signal FWD and the reflected wave component signal REF output from the directional coupler 20 is equal to or higher than a predetermined value by the matching determination process of the level ratio detection circuit 90 (that is, matching is achieved). ) Is determined (step S23).

  When matching is not achieved (No), the switch control circuit 73 determines whether or not the number of execution histories of the control step number N is equal to or greater than a predetermined maximum value (step S24). When the determination result is negative (No), the control data of the variable capacitance control circuits 71B and 72B is changed up or down by one step according to the determination result of the correction direction determination circuit 60, or one of them is held, and the variable capacitance C1 , C2 are adjusted (step S25). When the determination result of step S24 is affirmative (Yes), the switch control circuit 73 controls the switch 35 to switch the value of the inductance L (step S26). The switch control circuit 73 sets the execution history of the control step number N to “0” (step S27).

  In the matching determination processing in step S23, when the matching determination result is affirmative (Yes) (when matching is achieved), the first and second variable capacitance control circuits 71B and 72B do not change the operation as data hold. At the same time, the switch control circuit 73 sets the execution history count of the control step number N to “0” (step S28). By the range determination process of the variable capacitor C1 in the switch control circuit 73, it is determined whether or not the control data of the variable capacitor C1 is equal to or greater than a predetermined minimum value (step S29). When the determination result is negative (No) (the value of the inductance L is too large), the switch control circuit 73 controls the switch 35 and switches the value of the inductance L to a smaller value (however, the L value is already smaller). If so, step S30).

  If the determination result of step S29 is affirmative (Yes), it is determined by the range determination process of the variable capacitor C1 in the switch control circuit 73 whether or not the control data of the variable capacitor C1 is equal to or less than a predetermined maximum value (step S31). If the determination result is affirmative (Yes), the process is terminated. If the determination result is negative (No) (the value of the inductance L is too small), the switch control circuit 73 controls the switch 35 and the inductance L The value is switched to the larger one (however, if the L value has already been larger, the step is continued as is).

  The above process (steps S21 to S32) is repeated to execute the matching process.

(Effect of Example 4)
According to the fourth embodiment, there are almost the same effects as the third embodiment.

(Modification of Example 4)
Even when the primary winding side of the transformer 34 is connected in series to the coil 31, the same effect as described above can be obtained. In the fourth embodiment, the first to fourth modifications of the first embodiment can be similarly applied.

(Configuration of Example 5)
FIG. 21 is a schematic configuration diagram illustrating an automatic matching circuit according to the fifth embodiment of the present invention. Elements common to those in FIG. 19 illustrating the fourth embodiment are denoted by common reference numerals.

  In the automatic matching circuit 10D of the fifth embodiment, instead of the π match circuit 30C in the automatic matching circuit 10C of the fourth embodiment, a π match circuit 30D having a different configuration is provided. Further, the switch control of the fourth embodiment Instead of the circuit 73, a third variable capacitance control circuit 74 is provided.

  The π match circuit 30D includes the first coil 31 having the same inductance L1 as the coil 31 having the inductance L in the fourth embodiment. In addition to the transformer 34 and the switch 35 in the fourth embodiment, the second circuit having the inductance L2 is used. A coil 36 and a third capacitor 37 having a variable capacitance C3 are provided. In other words, the π match circuit 30D includes first and second coils 31 and 36 connected in series to the output side of the directional coupler 20, and an input / output side of the coils 31 and 36 and the ground GND. The first, second, and third capacitors 32, 33, and 37 are connected in parallel. The first and second coils 31 and 36 have the same circuit configuration, and the first, second, and third capacitors 32, 33, and 37 also have the same circuit configuration.

  Although not shown, the third capacitor 33 is provided between a plurality of third unit capacitors connected in parallel to the signal line, and the ground as a reference potential line. It is comprised by the 3rd switch means (for example, switch circuit) connected.

  The third variable capacitance control circuit 74 inputs the clock signal CK output from the oscillator 70, the control data of the first variable capacitance control circuit 71B, and the detection result of the level ratio detection circuit 90, and the third capacitor 37. This circuit controls the variable capacitor C3 and has the following functions.

  That is, the third variable capacitance control circuit 74 is matched, the reflection component signal REF output from the directional coupler 20 becomes sufficiently smaller than the traveling wave component signal FWD, and the level ratio detection circuit 90 is matched. If the variable capacitance C1 of the first capacitor 32 is smaller than the predetermined lower limit value even if it is determined that the third capacitor 37 has been removed, it is determined that the value of the variable capacitance C3 of the third capacitor 37 is too large, and the third capacitor 37 To reduce the value of the variable capacitor C3. If the value of the variable capacitor C3 is already small, it is left as it is because the matching adjustment range is limited. Even if it is determined that the reflection component signal REF output from the directional coupler 20 is sufficiently smaller than the traveling wave component signal FWD and the level ratio detection circuit 90 determines that the matching is achieved, the first capacitor If the variable capacitor C1 of 32 is larger than the predetermined lower limit value, it is determined that the value of the variable capacitor C3 is too small, and the third capacitor 37 is controlled to increase the value of the variable capacitor C3. If the value of the variable capacitor C3 is already large, it is left as it is because the limit of the matching adjustment range. Further, the third variable capacitance control circuit 74 counts the number of clocks of the clock signal CK, detects a period in which the state of non-matching continues continuously, and matches even if the predetermined number of clocks is exceeded. If it cannot be obtained, the value of the variable capacitor C3 is determined to be inappropriate, and the third capacitor 37 is controlled to switch the value of the variable capacitor C3.

(Outline of automatic alignment method of embodiment 5)
In the automatic matching circuit 10D of the fifth embodiment, the variable capacitor C3 of the third capacitor 37 is switched under the control of the third variable capacitor control circuit 74. At this time, the third variable capacitance control circuit 74 switches the variable capacitance C3 according to the value of the variable capacitance C1 of the first capacitor 32, and when the variable capacitance C1 becomes larger than a predetermined value, the value of the variable capacitance C3 is changed. Switch to enlarge. Conversely, when the value is smaller than the predetermined value, the value of the variable capacitor C3 is switched to make it smaller. Further, when the matching cannot be achieved, the value of the variable capacitor C3 is switched regardless of the condition of the variable capacitor C1. The principle of this method is as follows.

  When the impedance of the load 3 viewed from the output terminal 12 of the automatic matching circuit 10D is small, the value of the variable capacitor C3 is decreased so as to obtain matching. Even when the impedance of the load 3 viewed from the output terminal 12 of the automatic matching circuit 10D is large, matching is possible by adjusting the variable capacitor C1 to be large. However, there is a problem that even if matching is achieved, Q becomes high and the transmission band becomes narrow. Since this state can be detected by the variable capacitor C1 being large, the value of the variable capacitor C3 is substantially changed by switching the value of the variable capacitor C3 from the small first value to the second value so that the Q does not become too high. It can be used. It is also possible to increase the change range of the load 3 to the larger side and further increase the number of stages to be switched between the third and fourth.

(Details of automatic alignment method of embodiment 5)
FIG. 22 is a flowchart showing the processing procedure of the automatic matching method in the automatic matching circuit 10D of FIG.

  While the clock signal CK output from the oscillator 70 is waiting to rise (step S41), the phase detection circuits 40 and 50, the level ratio detection circuit 90, and the correction direction determination circuit 60 operate continuously, and the matching state in this state It converges to the output value according to. When the clock signal CK rises, the variable capacitance control circuits 71B, 72B, and 74 capture the detection results of the level ratio detection circuit 90, and the detection results of the first and second phase detection circuits 40 and 50 are corrected direction determination circuits 60. The third variable capacitance control circuit 74 increases the execution history count of the control step number N by 1 (step S42). The level ratio between the traveling wave component signal FWD and the reflected wave component signal REF output from the directional coupler 20 is equal to or higher than a predetermined value by the matching determination process of the level ratio detection circuit 90 (that is, matching is achieved). ) Is determined (step S43).

  If not matched (No), the third variable capacitance control circuit 74 determines whether or not the number of execution histories of the control step number N is equal to or greater than a predetermined maximum value (step S44). When the determination result is negative (No), the control data of the variable capacitance control circuits 71B and 72B is changed up or down by one step according to the determination result of the correction direction determination circuit 60, or one of them is held, and the variable capacitance C1 , C2 are adjusted (step S45). If the determination result of step S44 is affirmative (Yes), the third variable capacitance control circuit 74 controls the third capacitor 37 to switch the value of the variable capacitor C3 (step S46). The third variable capacitance control circuit 74 sets the execution history of the control step number N to “0” (step S47).

  In the matching determination processing in step S43, when the matching determination result is affirmative (Yes) (when matching is achieved), the first and second variable capacitance control circuits 71B and 72B do not change the operation as data hold. At the same time, the third variable capacitance control circuit 74 sets the number of execution histories of the control step number N to “0” (step S48). By the range determination process of the variable capacitor C1 in the third variable capacitor control circuit 74, it is determined whether or not the control data of the variable capacitor C1 is equal to or greater than a predetermined minimum value (step S49). If the determination result is negative (No) (the value of the variable capacitor C3 is too large), the third variable capacitor control circuit 74 controls the third capacitor 37 and switches the value of the variable capacitor C3 to the smaller one (however, If the value of the variable capacitor C3 has already become smaller, the process continues as it is at step S50).

  If the determination result of step S49 is affirmative (Yes), it is determined whether or not the control data of the variable capacitor C1 is equal to or less than a predetermined maximum value by the range determination process of the variable capacitor C1 in the third variable capacitor control circuit 74 ( Step S51). If the determination result is affirmative (Yes), the process is terminated. If the determination result is negative (No) (the value of the variable capacitor C3 is too small), the third variable capacitance control circuit 74 uses the third capacitor. 37 is switched and the value of the variable capacitor C3 is switched to the larger one (however, if the value of the variable capacitor C3 has already become the larger one, the process proceeds to step S52).

  The above process (steps S41 to S52) is repeated to execute the matching process.

(Effect of Example 5)
According to the fifth embodiment, there are the following effects (i) and (ii).

  (I) FIGS. 23 and 24 are Smith charts showing impedance conversion by the inductance L2 and the variable capacitor C3 in the automatic matching circuit 10D of FIG.

  The impedance conversion conditions in FIG. 23 are: frequency = 13.56 MHz, L2 = 0.22 μH, C2 = 100 pF.

  Each of the four impedance points (1), (7), (4), and (10) shown on the Smith chart of FIG. 23 is connected to a capacitor 100 pF in parallel, so that the impedance points clockwise. Converted. The point (4) having a small absolute value of the impedance at the starting point has a small movement, and conversely, the point (1) has a large movement. Next, impedance conversion is performed clockwise by connecting the coil L2 = 0.22 μH to the series. As a result, (1) → (2) → (3), (7) → (8) → (29), (4) → (5) → (6), (10) → (11) → (12) As a whole, impedance conversion is performed in the left direction. Thus, although each impedance point on the Smith chart rotates to the right, there is little movement in the entire area.

  The impedance conversion conditions in FIG. 24 are: frequency = 13.56 MHz, L2 = 0.22 μH, and C2 = 330 pF.

  Each impedance point (0), (7), (3), (5), (1), (4), (24), (2), (6) 9 shown on the Smith chart of FIG. First, the impedance is converted clockwise by connecting a capacitor 330 pF in parallel. The point (1, 4, 5) having a small absolute value of the impedance at the starting point has a small movement, and conversely (0, 6, 7) has a large movement. Next, impedance conversion is performed clockwise by connecting the coil L2 = 0.22 μH to the series. As a result, (0) → (8) → (9), (7) → (22) → (23), (3) → (14) → (15), (5) → (20) → (21) , (1) → (10) → (11), (4) → (16) → (17), (24) → (25) → (26), (2) → (12) → (13), 6) → (18) → (19) As a whole, impedance conversion is performed in the left direction. Thus, each impedance point on the Smith chart rotates to the right, and the entire area is left. It can be seen that an area that cannot be covered by the conventional one-stage π-matching circuit 2 shown in FIG. 25 is brought into the matching range in the fifth embodiment to perform an accurate impedance matching. Therefore, according to the fifth embodiment, there are almost the same effects as the fourth embodiment.

  (Ii) As a result of trial manufacture of the automatic matching circuit 10D of the fifth embodiment, SWR is 1.065 or less and return loss is 30 dB or more with respect to the load 3 in the range of 8 or less in SWR and 2.2 dB or more in return loss. Matching (99.9% in transmission efficiency) was obtained automatically and continuously.

(Modification of Example 5)
In the fifth embodiment, the first to fourth modifications of the first embodiment can be similarly applied.

(Other variations of Examples 1 to 5)
The directional coupler 20, the π match circuits 30 to 30D, the phase detection circuits 40, 40A, 50, and 50A, the correction direction determination circuits 60 and 60A, the variable capacitance control circuits 71, 71B, 72, 72B, and 74 are illustrated. However, the circuit configuration is not limited to the circuit configuration shown in FIG. Also, the processing procedure of the automatic alignment method is not limited to the procedure of the flowchart shown in the figure, and may be changed to other processing procedures and processing contents other than those shown in the figure.

It is a schematic block diagram which shows the automatic matching circuit in Example 1 of this invention. It is a block diagram which shows an example of the directional coupler 20 in FIG. It is a block diagram which shows an example of the 1st or 2nd capacitor | condenser 32,33 in FIG. FIG. 2 is a schematic configuration diagram illustrating a circuit example of a main part of FIG. 1. FIG. 5 is a configuration diagram illustrating an example of a phase shift circuit 41 in FIG. 4. FIG. 5 is a configuration diagram illustrating an example of a phase shift circuit 41 in FIG. 4. FIG. 5 is a configuration diagram illustrating an example of a phase shift circuit 41 in FIG. 4. FIG. 5 is a configuration diagram showing an example of first and second phase comparison circuits 42 and 52 in FIG. 4. 3 is a Smith chart showing a method of adjusting the first and second capacitors 32 and 33 in FIG. 1 with respect to the variable capacitors C1 and C2. 3 is a Smith chart showing a method of adjusting the first and second capacitors 32 and 33 in FIG. 1 with respect to the variable capacitors C1 and C2. FIG. 4 is a configuration diagram illustrating a first modification of the first capacitor 32 in FIG. 3. It is a block diagram which shows the modification 2 in each unit capacitor | condenser 32a-1 to 32a-N in FIG. FIG. 6 is a configuration diagram showing a third modification of the first capacitor 32 in FIG. 3. FIG. 6 is a configuration diagram showing a fourth modification of the first capacitor 32 in FIG. 3. It is a schematic block diagram which shows the automatic matching circuit in Example 2 of this invention. 14 is a Smith chart showing a method for adjusting the variable capacitors C1 and C2 of the first and second capacitors 32 and 33 in FIG. 14 is a Smith chart showing a method for adjusting the variable capacitors C1 and C2 of the first and second capacitors 32 and 33 in FIG. It is a schematic block diagram which shows the automatic matching circuit in Example 3 of this invention. FIG. 17 is a schematic configuration diagram illustrating a circuit example of a main part of FIG. 16. 18 is a flowchart showing a processing procedure of an automatic matching method in the automatic matching circuit 10B of FIGS. 16 and 17; It is a schematic block diagram which shows the automatic matching circuit in Example 4 of this invention. It is a flowchart which shows the process sequence of the automatic matching method in 10 C of automatic matching circuits of FIG. It is a schematic block diagram which shows the automatic matching circuit in Example 5 of this invention. It is a flowchart which shows the process sequence of the automatic matching method in automatic matching circuit 10D of FIG. 22 is a Smith chart showing impedance conversion by an inductance L2 and a variable capacitor C3 in the automatic matching circuit 10D of FIG. 22 is a Smith chart showing impedance conversion by an inductance L2 and a variable capacitor C3 in the automatic matching circuit 10D of FIG. It is a schematic block diagram which shows the matching circuit using the conventional (pi) match circuit. 26 is a Smith chart showing an example of an impedance matching range of the π match circuit 2 in the matching circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Drive source 3 Load 10, 10A, 10B, 10C, 10D Automatic matching circuit 20 Directional coupler 30, 30C, 30D π match circuit 31, 36 Coil 32, 33, 37 Capacitor 34 Transformer 35 Switch 40, 40A, 50, 50A phase detection circuit 60, 60A correction direction determination circuit 70 oscillator 71, 71B, 72, 72B, 74 variable capacity control circuit 73 switch control circuit 90 level ratio detection circuit

Claims (16)

Using the π-match circuit in which a variable first capacitor located on the high-frequency signal source side and a variable second capacitor located on the load side are connected to both ends of the fixed first coil, the signal source An automatic matching method for automatically matching output impedance on the load side and input impedance on the load side,
Detects a traveling wave component signal from the signal source toward the load and a reflected wave component signal from the load, and detects a phase difference between the reflected wave component signal and the traveling wave component signal as a reference. Processing to
It is determined whether the phase difference has an advance or delay component of a predetermined angle, and the output impedance and the input impedance are matched by increasing / decreasing the capacities of the first and second capacitors based on the determination result. Processing and
If the phase difference has a 90 ° lead component, the capacity of the first capacitor is increased. Conversely, if the phase difference has a 90 ° delay component, the capacity of the first capacitor is decreased.
If the phase difference has a 45 ° delay component, the capacity of the second capacitor is reduced. Conversely, if the phase difference has a 135 ° degree advance (= 45 ° delay reverse phase) component, An automatic matching method, wherein the capacity of the second capacitor is increased. Using the π-match circuit in which a variable first capacitor located on the high-frequency signal source side and a variable second capacitor located on the load side are connected to both ends of the fixed first coil, the signal source An automatic matching method for automatically matching output impedance on the load side and input impedance on the load side,
Detects a traveling wave component signal from the signal source toward the load and a reflected wave component signal from the load, and detects a phase difference between the reflected wave component signal and the traveling wave component signal as a reference. Processing to
It is determined whether the phase difference has an advance or delay component of a predetermined angle, and the output impedance and the input impedance are matched by increasing / decreasing the capacities of the first and second capacitors based on the determination result. Processing, and
If the phase difference has a 45 ° lead component, the capacity of the first capacitor is increased. Conversely, if the phase difference has a 135 ° delay component, the capacity of the first capacitor is decreased.
If the phase difference has a 45 ° delay component, the capacity of the second capacitor is reduced. Conversely, if the phase difference has a 135 ° degree advance (= 45 ° delay reverse phase) component, An automatic matching method, wherein the capacity of the second capacitor is increased. A variable first capacitor located on the high-frequency signal source side and a variable second capacitor located on the load side having a π-match circuit connected to both ends of the fixed first coil; An automatic matching circuit that automatically matches the output impedance on the load side and the input impedance on the load side,
A directional coupler connected between the signal source and the π-matching circuit for detecting a traveling wave component signal from the signal source toward the load and a reflected wave component signal from the load;
A phase detection circuit that detects a phase difference of the reflected wave component signal based on the traveling wave component signal;
It is determined whether or not the phase difference has an advance or delay component of a predetermined angle, and the output impedance and the input impedance are matched by increasing or decreasing the capacitances of the first and second capacitors based on the determination result. Determination control means for controlling
The determination control means includes
If the phase difference has a 90 ° lead component, the capacity of the first capacitor is increased. Conversely, if the phase difference has a 90 ° delay component, the capacity of the first capacitor is decreased, and If the phase difference has a 45 ° delay component, the capacity of the second capacitor is reduced. Conversely, if the phase difference has a 135 ° advance (= 45 ° delay reverse phase) component, the second capacitor is reduced. 2. An automatic matching circuit characterized by increasing the capacitance of the second capacitor. A variable first capacitor located on the high-frequency signal source side and a variable second capacitor located on the load side having a π-match circuit connected to both ends of the fixed first coil; An automatic matching circuit that automatically matches the output impedance on the load side and the input impedance on the load side,
A directional coupler connected between the signal source and the π-matching circuit for detecting a traveling wave component signal from the signal source toward the load and a reflected wave component signal from the load;
A phase detection circuit that detects a phase difference of the reflected wave component signal based on the traveling wave component signal;
It is determined whether or not the phase difference has an advance or delay component of a predetermined angle, and the output impedance and the input impedance are matched by increasing or decreasing the capacitances of the first and second capacitors based on the determination result. Determination control means for controlling
The determination control means includes
If the phase difference has a 45 ° lead component, the capacity of the first capacitor is increased. Conversely, if the phase difference has a 135 ° delay component, the capacity of the first capacitor is reduced. If the phase difference has a 45 ° delay component, the capacity of the second capacitor is reduced. Conversely, if the phase difference has a 135 ° advance (= 45 ° delay reverse phase) component, the second capacitor is reduced. 2. An automatic matching circuit characterized by increasing the capacitance of the second capacitor. The determination control means includes
It is determined whether the phase difference detected by the phase detection circuit has an advance or delay component of the predetermined angle, and an increase / decrease direction with respect to the capacities of the first and second capacitors is determined based on the determination result. A correction direction determination circuit to perform,
A first variable capacitance control circuit for controlling an increase / decrease value with respect to the capacitance of the first capacitor based on the increase / decrease direction determined by the correction direction determination circuit;
A second variable capacitance control circuit for controlling an increase / decrease value with respect to the capacitance of the second capacitor based on the increase / decrease direction determined by the correction direction determination circuit;
The automatic matching circuit according to claim 3 or 4, characterized by comprising: The automatic matching circuit according to claim 5, further comprising:
A level ratio between the traveling wave component signal and the reflected wave component signal detected by the directional coupler is detected, and when the level ratio exceeds a predetermined value, the first and second variable capacitors An automatic matching circuit having a level ratio detection circuit for stopping a matching operation with respect to a control circuit. The automatic matching circuit according to claim 5 or 6,
The π match circuit further includes:
A transformer having a primary winding and a secondary winding, the primary winding side being connected in parallel or in series with the first coil;
A switch for releasing or short-circuiting the secondary winding side,
Further, the automatic matching circuit includes:
The output of the first variable capacitance control circuit and the output of the level ratio detection circuit are input, and the switch is turned on / off based on the capacitance value of the first capacitor, and the primary winding of the transformer An automatic matching circuit comprising a switch control circuit for increasing or decreasing an inductance value viewed from the line side. The switch control circuit includes:
The switch is controlled, and when the capacitance of the first capacitor becomes smaller than a predetermined value, the inductance value is switched to be decreased, and when the capacitance of the first capacitor is larger than a predetermined value, 8. The automatic matching circuit according to claim 7, wherein when the value of the inductance is switched to be increased and matching is not achieved, the value of the inductance is switched regardless of the value of the capacitance of the first capacitor. The automatic matching circuit according to claim 5 or 6,
The π match circuit further includes:
A fixed second coil connected in series between the first coil and the load side;
A variable third capacitor connected in a branched manner between the second coil and the load side;
Further, the automatic matching circuit includes:
The output of the first variable capacitance control circuit and the output of the level ratio detection circuit are input, and the capacitance value of the third capacitor is controlled by controlling the third capacitor based on the capacitance value of the first capacitor. An automatic matching circuit comprising a third variable capacitance control circuit for increasing / decreasing the value. The third variable capacitance control circuit includes:
The capacitance value of the third capacitor is controlled, and when the capacitance of the first capacitor becomes larger than a predetermined value, the capacitance value of the third capacitor is switched to increase the capacitance of the first capacitor. Is smaller than a predetermined value, the capacitance value of the third capacitor is switched to a small value, and when the matching is not achieved, the capacitance value of the third capacitor is not related to the capacitance value of the first capacitor. The automatic matching circuit according to claim 9, wherein the automatic matching circuit is switched. The first capacitor is
A plurality of first unit capacitors connected in parallel between the output side of the directional coupler and the first coil, each capacitance ratio being about 1.8 times;
A plurality of first switch means controlled by the first variable capacitance control circuit to change the capacitance value of the first capacitor by connecting or releasing the first unit capacitors respectively;
The second capacitor is:
A plurality of second unit capacitors connected in parallel between the first coil and the load side, each capacitance ratio being about 1.8 times;
A plurality of second switch means that are controlled by the second variable capacitance control circuit to change the capacitance value of the second capacitor by connecting or releasing each of the second unit capacitors. The automatic matching circuit according to any one of claims 5 to 10, wherein: 12. The automatic matching circuit according to claim 11, wherein a bias voltage is applied to each of the first switch means and each of the second switch means. A bias voltage is applied to each of the first switch means and each of the second switch means when the first unit capacitors and the second unit capacitors are released. The automatic matching circuit according to claim 11. The third capacitor is:
A plurality of third unit capacitors connected in parallel between the second coil and the load side;
And a plurality of third switch means that are controlled by the third variable capacitance control circuit to change the capacitance value of the third capacitor by connecting or releasing each of the third unit capacitors. The automatic matching circuit according to any one of claims 9 to 11, wherein: 15. The automatic matching circuit according to claim 14, wherein a bias voltage is applied to each of the third switch means. 15. The automatic matching circuit according to claim 14, wherein a bias voltage is applied to each of the third switch means when the third unit capacitors are released.

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