JPH04138510A - Bus connection type multiprocessor device - Google Patents

Abstract

PURPOSE:To prevent the generation of troubles such as the increment of electric load or the generation of signal delay by forming wiring areas between respective power supply lines and between respective ground lines and forming bus lines in the wiring areas. CONSTITUTION:Since the power supply lines 21 on a power supply layer 20 are formed by wring patterns directed only in one direction (x direction), a surface margin can be formed over a wide range among respective lines 21. Since the ground lines 31 on a ground layer 30 are formed by wiring patterns directed only in the direction (y direction) rectangular to the lines 21, a surface margin can be formed over a wide range also among the lines 31. Thereby, bus lines 22, 23 can be formed in the space parts, so that the wiring of the bus lines 22, 32 can be shortened or the wiring patterns of respective lines can be simplified. Consequently, the generation of troubles such as the increment of electric load and the generation of signal delay can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus-coupled multiprocessor device in which a plurality of processors are connected via a bus.

(Prior art) What is a bus-coupled multiprocessor device?1.
A processing unit (hereinafter referred to as cPU),
Local memory (hereinafter referred to as LM, ROM and RAM)
) and an interface (hereinafter referred to as l
/F), etc.
A plurality of processors that operate independently according to instruction codes therein are connected by various buses such as a data bus, an address bus, and a control signal bus, and data is exchanged between each processor via these buses. This is a device that performs desired arithmetic processing.

Such a bus-coupled multiprocessor device has conventionally generally been configured as shown in FIG. 7 or FIG. 8. That is, in the bus-coupled multiprocessor device shown in FIG. 7, a CPU board (processor) is configured by mounting cPUSLM11/F etc. on a printed wiring board, and multiple CPU boards are stored in a rack. At the same time, the CPU boards are connected via a common bus or the like via a connector, and data is exchanged between the CPU boards. Further, in the bus-coupled multiprocessor device shown in FIG. 8, the CPUSLM.

A plurality of CPU modules (processors) equipped with 1/F, etc. are mounted on a motherboard, and data is exchanged via a bus formed on the motherboard.

(Problem to be Solved by the Invention) However, in the conventional bus-coupled multiprocessor device shown in FIG. 7 or 8, the number of CPU boards and CPU modules increases (that is, As the number of bus lines increases, the wiring for the bus lines becomes longer, causing problems such as heavier electrical loads and signal delays, and the overall size of the equipment. There will also be a volumetric disadvantage.

Therefore, the present invention was devised, and its purpose is to enable miniaturization and to avoid problems such as heavy electrical loads and signal delays. An object of the present invention is to provide a bus-coupled multiprocessor device.

(Means for Solving the Problems) In order to solve the above problems, the means taken by the present invention are described with reference numerals corresponding to the embodiments. (22)(32)(
A bus-coupled multiprocessor device (100) connected via a bus-coupled multiprocessor device (41), comprising a mounting layer (10) on which each of the processors (11) is mounted.
and a power layer (20) in which a power line (21) for supplying power to each of the processors (11) is wired in one direction;
The ground line (31) of each of the processors (11) is constituted by a ground layer (30) wired in a direction perpendicular to the power supply line (21), and the power supply layer (
A bus line (2) connecting the processors (11) between each power line (21) in the ground layer (30) and between each ground line (31) in the ground layer (30);
2) A bus-coupled multiprocessor device (100) characterized in that (32) is provided.

In other words, the bus-coupled multiprocessor device (100) according to the present invention, as shown in FIG. Configure and implement the implementation layer (10
) includes a processor (
11), and the power layer (20) and ground layer (30
) is provided with a power line (21) and a ground line (31) for supplying power to each processor (11). The power supply line (21) is formed by a wiring pattern directed only in one direction (for example, the X direction),
The ground line (31) is formed by a wiring pattern that runs only in a direction perpendicular to the power line (21) (for example, the y direction), and furthermore, a wiring pattern is formed in the wiring area between each power line (21) and the ground line (31). Each processor (1
1) and the data bus (22) and address bus (3
2) and other bus lines were established. Note that the fourth layer is provided with a control signal bus (41) among the bus lines.

(Actions of the Invention) With the above configuration, the bus-coupled multiprocessor device (100) according to the present invention has the following effects.

That is, as shown in FIGS. 1 to 5, the power layer (20
) is formed by a wiring pattern that goes only in one direction (X direction), so there is a wide surface margin between each power supply line (21), and the ground The ground line (31) in the layer (30) is formed by a wiring pattern that runs only in the direction (y direction) perpendicular to the power supply line (21), so there is a wide range of surface area between each ground line (31). You can have more room above. Therefore, the bus lines (22) (32) can be provided in this vacant part, that is, the power line (21) or the ground line (31) and the bus lines (22) (32) can be provided on the same layer. Therefore, the bus line (22) (32
) wiring can be shortened and the wiring pattern of each line can be simplified. In addition, the bus line (
22) and (32) can be shortened, making it possible to downsize the entire device.

Moreover, by configuring as described above, the present invention provides two
Because it is possible to arrange and connect the processors (11) in a dimensional manner,
This is also effective for a bus-coupled multiprocessor device (100) using lattice-type bus coupling.

(Example) Next, a bus-coupled multiprocessor device t according to the present invention
(100) will be explained according to an embodiment shown in the drawings.

First, as shown in FIGS. 1 to 5, the bus-coupled multiprocessor device (100) according to this embodiment has a mounting layer (
10), a four-layer printed wiring board consisting of a power layer (20), a ground layer (30), and a control layer (40).

In the mounting layer (10), as shown in FIGS. 2 and 6,
A large number of CPU modules (processors (11) in the present invention) each consisting of circuits such as CPU, LM, I/F, etc. are formed, and each of these processors (11) can exchange data via a bus. Vce terminal and GND for supplying power to each circuit.
It has terminals, and from each of these terminals a power line (described later) is connected.
21) and a ground line (31), respectively.

In the power supply layer (20), a power supply line (21) that supplies power to each of the processors (11) is connected from the left to the right (toward the X direction in the drawing).
In addition, between each of these power lines (21), each of the processors (11)
) from the left to the right (toward the reverse X direction in the drawing),
It is formed at a position corresponding to each processor (11). In other words, the data bus line (22) is formed in the wiring area between each power supply line (21).

Next, the ground layer (30) has a ground line (31
) from the bottom to the top (toward the y direction of the drawing,
In other words, they are formed at positions corresponding to each processor (11) (towards a direction perpendicular to the aforementioned power supply line (21)), and each of these ground lines (31)
In between, an address bus line (32) for specifying the address of each processor (11) runs downward from above (toward the reverse y direction in the drawing).
) is formed at a position corresponding to In other words, each ground line (31) as well as the data bus line (22)
An address bus line (32) is formed in the wiring area between them.

In addition, in the control layer (40), a control signal bus line (41) for controlling each processor (11) is formed from left to right.

Each layer (20) (30) (40) configured as above
Each line (21) (32) (41) in is connected to each processor (11) via a through hole (50), thereby exchanging data between each processor (11). , to perform desired arithmetic processing.

(Effects of the Invention) As detailed above, the bus-coupled multiprocessor device according to the present invention is “a bus-coupled multiprocessor device in which a plurality of processors are connected via a bus, in which each of the processors is a power layer in which a power line for supplying power to each processor is routed in one direction, and a ground layer in which a ground line for each processor is routed in a direction perpendicular to the power supply line. In addition, a bus line connecting the processors is provided between each power supply line in the power supply layer and between each ground line in the ground layer.

Therefore, according to this bus-coupled multiprocessor device, a wiring area can be provided between each power supply line and each ground line, and by providing the bus line in this wiring area, the wiring of the node line can be 1. Because it can be shortened and the wiring pattern of each line can be simplified. It is possible to avoid the conventional disadvantages of heavy electrical loads and signal delays. Also,
Since the bus line wiring can be shortened, the entire device can also be downsized.

Moreover, by configuring as described above, the present invention provides two
Since processors can be arranged and connected in a dimensional manner, it is also effective for bus-coupled multiprocessor devices using lattice-type bus coupling.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view showing an embodiment of a bus-coupled multiprocessor device according to the present invention, FIG. 2 is a plan view showing only the mounting layer of the embodiment shown in FIG. 1, and FIG. 1 is a plan view showing only the power layer of the embodiment shown in FIG. 1, FIG. 4 is a plan view showing only the ground layer of the embodiment shown in FIG. 1, and FIG. 5 is a plan view showing only the ground layer of the embodiment shown in FIG. 6 is a plan view showing the configuration of each processor in the mounting layer shown in FIG. 1; FIG. 7 is a perspective view showing an example of a conventional bus-coupled multiprocessor device; FIG. 8 is a perspective view showing another conventional bus-coupled multiprocessor device. Explanation of code 100...Bus-coupled multiprocessor device, IO/
... Mounting layer, 11... Processor, 20... Power supply layer, 21... Power supply line, 22... Data bus line, 30... Ground layer, 31... Ground line,
32...address bus line, 40...f14Ij
Layer, 41...1ml signal bus line, 50..., through hole. that's all

Claims (1)

[Claims] A bus-coupled multiprocessor device in which a plurality of processors are connected via a bus, the mounting layer having each of the processors mounted thereon, and the power supply layer having a power line for supplying power to each of the processors in one direction. and a ground layer in which the ground line of each of the processors is wired in a direction perpendicular to the power supply line, and each of the A bus-coupled multiprocessor device characterized by having a bus line for connecting processors.