JPH04137815A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To realize a synchronizing circuit with a hazard elimination function and simple circuit constitution by providing 1st and 2nd latch circuits latching an output of an asynchronizing circuit synchronously with the leading and the trailing of a 2nd clock. CONSTITUTION:A system clock TC is given to a T input of a D flip-flop (D-FF) 10 and the inverse of a system clock TC is given to a T input of a D-FF 20. The D-FF 10 latches an output A of an asynchronizing circuit 3 operated according to an asynchronizing clock CLK synchronously with the leading of the system block TC and the D-FF 20 latches an output A of the circuit 3 synchronously with the trailing of the clock TC. Then an AND gate 100 ANDs an output signal B of the D-FF 10 and an output signal C of the D-FF 20. Hazard is eliminated from the signal A and an output signal OUT is obtained synchronously with the system clock TC. Thus, the circuit constitution is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization circuit that receives the output of a circuit that operates according to a first clock and synchronizes the output with a second clock.

[Conventional technology]

FIG. 5 is a block diagram showing a conventional synchronization circuit with a hazard removal function. In the figure, 1 is a system clock input terminal which is input manually by the system lock TC, and 2 is an asynchronous clock input terminal to which an asynchronous clock CLK which is not synchronized with the system clock is input.

3 is the asynchronous clock C from the asynchronous clock input terminal 2
This is an asynchronous circuit that operates according to LK.

The asynchronous circuit 3 includes, for example, a counter 3a and a decoder 3b that decodes the output of the counter 3a as shown in FIG. 6(a), or a counter 3 as shown in FIG. 6(b).
a, and a comparator 3c which compares the output (2) of the counter 3a with a reference value (5) and outputs the comparison result.

4 is a D flip-flop (hereinafter D-F) for hazard removal.
(abbreviated as F). In the D-FF4, the output A of the asynchronous circuit 3 is input to the zero input, and the asynchronous clock CLK is input to the T input. 5 and 6 are both the output A of the asynchronous circuit 3
This is a D-FF for synchronizing the system clock TC with the system clock TC. The D-FF5 has either the signal E from the output Q of the D-FF4 or the system clock TC inputted to its T input. The D-FF6 is manually input with the signal F from the output Q of the D-FF5 and the system clock TC at the T input, and outputs an output signal OUT from the output Q.

Hereinafter, the operation of the circuit shown in FIG. 5 will be explained while stating the necessity of Di-FF4.6. First, as shown in FIG. 7, a case where the D-FFs 4 and 6 are not provided will be described. As shown in FIG. 8, a hazard occurs at the output A of the asynchronous circuit 3 immediately after the asynchronous clock CLK rises. When the system clock TC is input at the timing shown in FIG. 8, the output signal OUT contains a signal due to the influence of hazard in synchronization with the rising edge of the system clock TC. In order to eliminate the influence of this hazard, as shown in FIG.
I)-FF4 for hazard removal, which operates in synchronization with the asynchronous clock CLK, is provided between the F5 and the F5.

Figure 10A, 1st. The operation of the circuit shown in FIG. 9 will be explained using the OB diagram and FIG. 10C.

1st. In the OA diagram to Figure 10C, the hazard occurs immediately after the rising edge of the asynchronous clock CLK, so the output A
There are no hazards occurring.

Therefore, the influence of the hazard does not appear on the signal E.

Next, a case will be described in which the signal E is synchronized with the system clock TC. In FIG. 10A, the rising edge of the system clock TC and the rising edge of the signal E do not coincide. Therefore, in this case, the signal F that rises in synchronization with the rise of the system clock TC that occurs immediately after the rise of the signal E is output, and the signal E can be synchronized with the system clock TC.

In FIGS. 10B and 10C, the rising edge of the system clock TC and the rising edge of the signal E coincide. FIG. 10B shows a case where signal E is successfully launched with the rise of system clock TC coinciding with signal E. In other words, the signal E
A signal F that rises in synchronization with the rising edge of the system clock TC that occurs at the rising edge of the signal F is output, and the signal E can be synchronized with the system clock TC.

On the other hand, in FIG. 10C, when the signal E is not successfully latched at the rising edge of the system clock TC that coincides with the rising edge of the signal E (a state in which it does not completely become "H" or "L" (metastable) occurs) (If you end up doing something like that). Metastability occurs in the signal F at the rising edge of the system clock TC. However, the signal F rises in synchronization with the next rise of the system clock TC, making it possible to synchronize the signal E with the system clock TC.

As mentioned above, the first. In any of the cases shown in FIG. OA to FIG. 10C, a signal F synchronized with the system clock TC can be obtained, but metastability may occur in the signal F as shown in FIG. 10C. In order to eliminate this metastability, a D-FF6 that operates in synchronization with the system clock TC is provided on the output side of the D-FF5, as shown in FIG. D-FF6 is the system clock TC
Since the signal F is latched in synchronization with the rising edge of the signal F, the output signal OUT can be a signal synchronized with the system clock TC without being affected by metastability in any of the cases shown in FIGS. 10A to 10C.

[Problem to be solved by the invention]

The conventional synchronization circuit with a hazard removal function has D-FF4 for hazard removal and D-FF5 for synchronization as described above.
, 6 are required, and there is a problem that the circuit configuration becomes complicated.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a synchronization circuit with a simple circuit configuration and a hazard removal function.

[Means to solve the problem]

The present invention is applied to a synchronization circuit that receives the output of a circuit that operates according to a first clock and synchronizes the output with a second clock.

The synchronization circuit according to the present invention receives the second clock and synchronizes with the rise of the second clock,
a first latch circuit that latches the pressure of the circuit; a second launch circuit that receives the second clock and latches the output of the circuit in synchronization with the falling edge of the second clock; 1st. It is provided with an AND gate that receives the output of the second latch circuit and outputs the logical product of these outputs, or an OR gate that outputs the logical sum of these outputs.

[Effect]

The first latch circuit in this invention latches the output of a circuit that operates according to the first clock in synchronization with the rise of the second clock. The second latch circuit latches the output of the circuit in synchronization with the falling edge of the second clock. 1st. The output of the second latch circuit is given to an AND gate or an OR gate, and the output of the first . The outputs of the second latch circuit are ANDed or ORed, and at that time,
The first generated due to the buzz at the output of the circuit
．． Erroneous signals at the output of the second latch circuit are removed.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a synchronization circuit according to the present invention. In this circuit, when the normal output A of the asynchronous circuit 3 rises from "L" to "Ho" and a positive buzzer exists, the buzzer is removed and the output A is synchronized with the system clock TC. The output A of the asynchronous circuit 3, which operates according to the asynchronous clock CLK, is given to the D input of each D-FFIo, 20.The system clock T is input to the T input of the D-FF 10.
C is the system clock TC at the T input of D-FF20.
An inverted clock is given. DFFIO output Q
The signal B from the D-FF 20 and the signal C from the output Q of the D-FF 20 are applied to an AND gate 100.

Next, the operation when a positive hazard occurs will be explained using FIG. 2A, FIG. 2B, and FIG. 2C. Immediately after the asynchronous clock CLK rises, a positive hazard occurs as shown in FIGS. 2A to 2C. If no hazard exists at the timing when the system clock TC is as shown in FIG. 2A, that is, at the edge of the system clock TC, the signals B and C become signals that are not affected by the hazard as shown in FIG. 2A. And AND
When the gate 100 performs the AND of the signal B and the signal C,
As shown in Figure 2A, the hazard is removed from signal A,
Moreover, an output signal OUT synchronized with the system clock TC can be obtained.

Figures 2B and 2C show signal B, due to the influence of the hazard.
This shows a case where an erroneous signal is included in C. Of these, in Figure 2B, there is a hazard at the rise and fall of the system clock TC, which causes the signal B,
The case where C rises to "H" is shown. Second
As shown in Figure B, H0 due to the influence of the hazard becomes the signal B.
, C does not overlap. Therefore, when the outputs B and C are ANDed, the hazard is removed from the signal A as shown in FIG. 2B, and an output signal OUT synchronized with the system clock TC is obtained.

FIG. 2C shows that there is a hazard at the rise and fall of the system clock TC, and this causes the signal B,
The case where metastability occurs in C is shown. Second
As shown in Figure c, metastability due to the influence of hazards does not cause signal B and signal C to overlap. Therefore, by taking the logical product of signal B and signal C, the hazard is removed from signal A as shown in FIG. 2c, and the system clock TC
An output signal OUT synchronized with is obtained.

According to this embodiment, the circuit can be constructed without using three D-FFs as in the conventional case, so the circuit construction can be simplified.

FIG. 3 is a circuit diagram showing another embodiment of the invention. In this embodiment, the AND gate 100 in the circuit shown in FIG. 1 is replaced with an OR gate 200+, :. In this circuit, the normal output A of the asynchronous circuit 3 changes from “H” to “
falls to L'', and if there is a highly negative hazard,
This circuit eliminates hazards and synchronizes the output A with the system clock TC.

Next, the operation will be explained using FIGS. 4A, 4B, and 4C. As shown in FIGS. 4A to 4C, a negative hazard occurs immediately after the asynchronous clock CLK rises. If there is no hazard at the timing when the system clock TC is as shown in FIG. 4A, that is, at the edge of the system clock TC, the signal B,
C becomes a signal that is not affected by hazards as shown in FIG. 4A. Then, when the OR gate 200 takes the logical sum of the signals B and C, the hazard is removed from the output A as shown in FIG. 4A, and an output signal OUT synchronized with the system clock TC is obtained.

Figures 4B and 4C show signal B, due to the influence of the hazard.
This shows a case where an erroneous signal is included in C. Of these, in Figure 4B, there is a /) signal at the falling and rising edges of the system clock TC, which causes the signal B
, C falls to "L". 4th B
As shown in the figure, “L” or signal B due to the influence of the hazard
, C do not overlap. Therefore, when the signal B and the signal C are logically summed, 71 sats are removed from the output A as shown in FIG. 4B, and an output signal OUT synchronized with the system clock TC is obtained.

Figure 4C shows that a noise signal exists at the rising and falling edges of the system clock TC, and this may be the cause of the signal B.
, C shows the case where metastability occurs. As shown in FIG. 4C, signals B and C do not overlap due to metastability due to the influence of noise. Therefore, when the logical sum of the signal B and the signal C is taken, as shown in FIG. 4C, the hazard is removed from the output A and an output signal OUT synchronized with the system clock TC is obtained.

In this way, by providing the OR gate 200, even if the normal signal of the output A of the asynchronous circuit 3 falls from "H" to "L" and a negative I\third exists, the hazard can be removed from the output A. and output A can be synchronized to the system clock TC.

In addition, in FIG. 2B, FIG. 2C, FIG. 4B, and FIG. 4C in the above embodiment, a case has been described in which both signals B and C are affected by a buzzard. Even when this occurs, the same effect as in the above embodiment is obtained.

Furthermore, in the above embodiment, the case where the asynchronous clock CLK and the system clock TC are asynchronous is explained.
The clocks may be synchronized with each other.

Further, in the above embodiment, a case was explained in which the D-FFIo, 20 was used, but any configuration may be used as long as it is a latch circuit that can launch the output A of the asynchronous circuit 3 in synchronization with the system clock TC. , is not limited to D-FF.

〔Effect of the invention〕

As described above, according to the present invention, the second clock is input, and the first clock latches the output of the circuit operating according to the first clock in synchronization with the rising edge of the second clock.
a second latch circuit in which a second clock is input manually and latches the output of the circuit in synchronization with the falling edge of the second clock; An AND gate that receives the output of the second launch circuit and outputs the logical product of these outputs or an OR gate that outputs the logical sum is provided, so there is no need to use three D-FFs as in the conventional case, making it simple. This has the effect that the output of the circuit operating according to the first clock can be synchronized with the second clock while eliminating hazards by using a circuit configuration that is similar to the above.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the synchronization circuit according to the present invention, FIGS. 2A, 2B, and 2C are diagrams for explaining the operation of the circuit shown in FIG. The figures are circuit diagrams showing other embodiments of the present invention, FIG. 4A, FIG. 4B, and FIG.
Figure C is a diagram for explaining the operation of the circuit shown in Figure 3.
Fig. 5 is a circuit diagram showing a conventional synchronization circuit, Fig. 6 is a block diagram showing an example of the configuration of an asynchronous circuit, Figs. 7, 8, 9, 10A, 10B, and 10C. This figure is a diagram for explaining the operation of the circuit shown in FIG. 5. In the figure, 10 and 20 are D-FF, 100 is AND
The gate 200 is an OR gate. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A synchronization circuit that receives the output of a circuit that operates according to a first clock and synchronizes the output with a second clock, wherein the second clock is input and the synchronization circuit synchronizes the output with a second clock. a first latch circuit that synchronously latches the output of the circuit; and a second latch circuit that receives the second clock and latches the output of the circuit in synchronization with the falling edge of the second clock.
A synchronization circuit comprising: a latch circuit; and an AND gate that receives outputs from the first and second latch circuits and outputs a logical product of these outputs or an OR gate that outputs a logical sum.