JPH04137160A - Bus arbitrating system - Google Patents

Abstract

PURPOSE:To improve the system performance by arbitrarily setting the frequency with which a bus use request in the high level interrupts that in the low level to use a bus. CONSTITUTION:A first OR circuit 8 operates logical OR among MHBRQs 3-11, 3-21, and 3-31, and a second OR circuit 9 operates logical OR among LBRQs 2-10, 2-20, and 2-30. The frequency with which the output signal of the circuit 8 is changed from the active state to the inactive state in the period when the output signal of the circuit 9 is active is counted by a counter 10, and its value is inputted to a comparator 11. An arbitrary value is preliminarily set to a register 15, to which an integer other than 0 can be set, by software, and the comparator 11 compares the value of the counter 10 and the value set to the register 15 with each other; and when they coincide with each other, the comparator 11 makes a mask signal 14 active. Thus, the system performance is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bus arbitration system, and in particular, has two arbitration levels, and within each level, arbitration is performed in a round robin manner, but between levels, arbitration is performed in a fixed order. Regarding the arbitration method of buses such as

[Conventional technology]

Conventionally, in this type of arbitration system, a low-level bus master positioned at a low rank can use the bus only after a high-level bus master positioned at a high rank finishes using the bus. Even if a low-level bus master becomes available for bus use, if a high-level bus use request occurs while the bus is being used, interrupt use of the bus will be interrupted even if low-level bus use requests remain. The use of the low-level bus is made to wait until all services for the bus use requests interrupted at that time are completed. This pattern will continue to be used for arbitration.

[Problem to be solved by the invention]

In the conventional bus arbitration method described above, interrupt bus usage is allowed as many times as a high level bus usage request occurs until all services are completed in response to a low level bus usage request. A disadvantage is that the waiting time for a low-level bus master to grant bus access can be significant.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a bus arbitration system that can prevent the bus usage waiting time of a bus φ master positioned at a low level from becoming excessively long.

[Means to solve the problem]

The bus arbitration method of the present invention receives a plurality of bus use request signals at the first level and a plurality of bus use request signals at the second level, and arbitrates in a round robin manner within the same level. In a bus arbitration method that arbitrates to give priority to the first level, the number of times the first level bus request signal changes from active to inactive while the second level bus request signal is active is counted. , the first level bus use request signal that is input when the number of times exceeds a predetermined number is masked.

Further, the bus arbitration method of the present invention includes means for taking in a high-level bus use request HBRQ and a low-level bus use request LBRQ in the priority control section, a mask circuit for masking HBRQ by a mask signal, and a mask circuit. OR the signal MHBRQ obtained via
A first OR circuit that ORs LBRQ, and a second OR circuit that ORs LBRQ.
circuit and the output of the second OR circuit is active.
A counter that counts the change point at which the output of the OR circuit changes from active to inactive, a register that can be arbitrarily set to an integer greater than or equal to 0 by software, and the value set in that register and the output value of the counter. a comparison circuit that generates a mask signal by comparing the MHBR
An arbitration circuit is provided which inputs Q and LBRQ and performs round robin arbitration within the same level in a fixed order between different levels to generate a bus use permission signal.

Further, in another aspect of the present invention, at least one central processing unit, a main storage device connected to the central processing unit via a bus, and at least one peripheral control device connected to the main storage device via a bus. An information processing device is provided that includes a device, at least one peripheral device controlled by a peripheral control device, and a priority control unit connected to a bus and arbitrating requests for use of the bus. The priority control unit of this information processing device is configured to respond to at least one high level bus usage request, ie HBRQ.
and at least one low level bus use request, i.e. L
BRQ, a mask circuit that masks HBRQ with a mask signal, and a first OR that logically ORs the signal obtained via the mask circuit, that is, MHBRQ.
a second OR circuit that logically ORs the LBRQ; and a first OR circuit that logically ORs the LBRQ;
A counter that counts the change point at which the output of the circuit changes from active to inactive, a register that can be arbitrarily set to an integer greater than or equal to 0 by software, and the value set in this register and the output value of the counter. A comparison circuit that compares and generates a mask signal, MHBRQ and L
BRQ, and performs round-robin arbitration within the same level, and fixed order arbitration between different levels, and generates a bus use permission signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, an information processing apparatus 1 according to an embodiment of the present invention includes three central processing units 2-1.2-2.2-
3, three peripheral control devices 3-1.3-2.3-3,
The main storage device 6, the bus 7 to which they are connected, the central processing unit 2-1゜2-2.2-3, and the peripheral control device 3-
It also includes a priority control section 5 that arbitrates requests for use of the bus 7 of L3-2.3-3.

Peripheral devices 4-1.4-2.4-3 are connected to each of the peripheral control devices 3-1.3-2.3-3.

Referring to Figure 2, the priority in Figure 1 is
In one embodiment of the present invention, the control unit 5 sends a high level use request signal HBRQ3-1 to the bus 7 of each of the peripheral control devices 3-1.3-2.3-3.
0.3-20.3-30 and central processing unit 2-1.2-2
．． 2-3 to the bus 7 of each device, and input the low φ level use request signal LBRQ2-10.2-20.2-30 to the mask circuit 12. Then, masking is performed using the mask signal 14. Outputs of the mask circuit 12 MHBRQ3-11.
3-21.3-31 to LBRQ2-10.2-20.2
-30 and is input to the arbitration circuit 13, and the arbitration circuit 13 is input between HBRQ3-10, 3-20, and 3-30 and L
Between BRQ2-10, 2-20, and 2-30, round robin arbitration is performed, and HBRQ and LBR are used.
Arbitration is performed with Q in a fixed order (giving priority to HBRQ), and peripheral control device 3-L 3-2.3-3
Usage permission signal HBAK3-12.3- for bus 7 of
22.3-32 and central processing unit 2-1.2-2.2
-3 bus 7 use permission signal LBAK2-12.
2-22. Generate 2-32. The priority control section further includes two OR circuits 8 and 9, a counter 10, a register 15, and a comparison circuit 11. The first OR circuit 8 is MHBRQ3-11.3-2
1. 3-31 is logically ORed, and the second OR circuit 9 is LBR.
Logically OR Q2-10.2-20.2-30. Second
77) The first O when the output signal of the OR circuit 9 is active
A counter 10 counts the number of times the output signal of the R circuit 8 changes from active to inactive, and the value is input to a comparator 11. An arbitrary value is set in advance by software in the register 15, which can be set to an integer greater than or equal to 0. The comparator 11 compares the value of the counter 10 and the value set in the register 15, and if they match, the comparison is made. device 11 activates mask signal 14.

FIG. 3 is a timing chart for explaining the operation of the priority control section shown in FIG.
, (b) + (c) are peripheral control devices 3-L, respectively.
3-2.3-3 usage request for bus 7 HBRQ3
-10.3-20.3-30, (d) shows the mask signal 14, and (e), (f), and (g) show the bus 7 use request signals obtained through the mask circuit 12, respectively. M.H.
BRQ3-11.3-21.3-31 is shown. (h), (i), and (j) in FIG. 3 are the central processing unit 2-L, respectively.
2-2.2-3 Use request signal LBR for bus 7
Indicates Q2-10.2-20.2-30, (k)+
(1) + (m), (n)t(o), and (p) are the peripheral control device 3-1゜3-2.3-3, respectively. Bus 7 use permission signal HBAK3-12.3-22.3-32 for central processing unit 2-1.2-2-2-3. LBAK2-
12.2-22.2-32 is shown. (r) is the first OR
This is the output signal of circuit 8. This timing chart is
This is the case where "'2" is set in the register 15 by software, and the embodiment will be described below with reference to FIGS. 2 and 3.

The output signal of the second OR circuit 9 ((j in FIG. 3)
(same timing as) is active (logic “O” level)
When the output signal (r) of the first OR circuit 8 changes from active to inactive (from logic "O" level to logic "1" level) twice during this period, the comparator 11 The mask signal 14 becomes active (logical "'1" level) as shown in FIG. 3(d). When the mask signal 14 becomes active, the mask circuit 12 operates and the H
Even if BRQ becomes active (logic "'0" level), the MHBRQ signal input to the arbitration circuit 13 does not become active (logic "0" level), that is, as shown in (e) and (g) in FIG. The case will not be as indicated by the broken line, and will not be subject to mediation. Therefore, the arbitration circuit 13 arbitrates the LBRQ that is input at that time, and
Until all are gone, that is, until (h) and (iL(j) are all inactive (logical "1 level"),
Allow bus 7 to be used by low e level bus masters. When all the low level LBRQ signals become inactive, the output of the second OR circuit 9 becomes inactive and the counter 10 is reset. As a result, the mask signal 14 also becomes inactive, returning to normal bus arbitration.

In FIG. 2, if the mask circuit 12 according to the present invention and the circuit groups 8 to 11 and 15 for generating the mask signal 14 are not present, LBAK becomes inactive as shown in the timing chart of FIG. High until LBAK goes active for the next bus contention master.
If a level bus usage request occurs, it will be interrupted.

〔Effect of the invention〕

As explained above, the present invention allows the frequency at which a high-level bus use request can interrupt a low-level bus use request to use the bus to be arbitrarily set. This has the effect that it is possible to reduce the meaningless bus usage waiting time of the level bus master, and as a result, system performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the bus arbitration system of the present invention, FIG. 2 is a block diagram of a priority control section in the embodiment of FIG. 1, and FIG. 3 is for explaining the operation of FIG. 2. FIG. 4 is a timing diagram for explaining the operation of the prior art. 1... Information processing device, 2-L 2-2.2-3...
Central processing unit, 3-1.3-2.3-3... Peripheral control device, 4-1.4-2.4-3... Peripheral device, 5...
・Priority control unit, 6... Main storage device, 7... Bus, 8... First OR circuit, 9...
Second OR circuit, 10... Counter, 11... Comparator, 12... Mask circuit, 13... Arbitration circuit, 14
...Mask signal, 15...Register, 3-10.3
-20°3-30... Peripheral control device 3-1.3-2.
Use request signal (high level) for bus 7 from 3-3, 2-10.2-20.2-30... central processing unit for bus 7 from 2-1.2-2.2-3 Use request signal (low φ level), 3-11°3-2L 3-3
1... Signal obtained from HBRQ3-10.3-20.3-30 via mask circuit 12, 3-12.3-22
．． 3-32... Peripheral control device 3-1.3-2.3-3
Enable signal for bus 7 to 2-12.2-22
．． 2-32...Central processing unit 2-1.2-2.2-3
bus 7 permission signal to the bus 7.

Claims (1)

[Claims] 1. Upon receiving a plurality of bus use request signals at the first level and a plurality of bus use request signals at the second level, arbitration is performed in a round robin manner within the same level, and between different levels, the above-mentioned bus use request signals are received. In the bus arbitration method that arbitrates to give priority to level 1,
Counting the number of times the first level bus use request signal before arbitration changes from active to inactive while the second level bus use request signal is active, and when the number of times exceeds a predetermined number of times; A bus arbitration method characterized in that the first level bus use request signal input to the bus is masked. 2. means for inputting the first level bus use request signal into the priority control section; means for inputting the second level bus use request signal; and means for inputting the input first level bus use request signal by a mask signal. a mask circuit for masking a signal; and a first circuit for ORing the first level bus use request signal obtained through the mask circuit.
and a second OR circuit that ORs the input second level bus use request signal, and the output of the first OR circuit is active while the output of the second OR circuit is active. a counter that counts the change point from to inactive; a register that can arbitrarily set a predetermined integer greater than or equal to 0; and a register that compares the value set in the register with the output value of the counter. a comparison circuit that generates a mask signal; a first level bus use request signal obtained through the mask circuit;
and an arbitration circuit that receives a bus use request signal of the same level, performs arbitration in a round robin manner within the same level, and gives priority to the first level between different levels, and generates a bus use permission signal. 2. The bus arbitration system according to claim 1. 3. at least one central processing unit, a main memory connected to the central processing unit via a bus, at least one peripheral control device connected to the main memory via the bus, and the peripheral An information processing device comprising at least one peripheral device controlled by a control device, and a priority control section connected to the bus and arbitrating requests for use of the bus, wherein the priority control section includes at least one first peripheral device. a mask circuit for masking the first level bus use request signal with a mask signal; a mask circuit for masking the first level bus use request signal with a mask signal; a first arithmetic circuit that computes the logical sum of the signals obtained through the second level bus request signal; a second arithmetic circuit that computes the logical sum of the second level bus request signal; a counter that counts the change point at which the output of the first arithmetic circuit changes from active to inactive; and a register that can be arbitrarily set to an integer greater than or equal to 0 by software;
A comparison circuit that compares a value set in the register with an output value of the counter to generate the mask signal, and a signal obtained through the mask circuit and the second level bus request signal are input. An information processing device comprising: an arbitration circuit that performs round-robin arbitration within the same level and a fixed order of arbitration between different levels to generate the bus use permission signal.