JPH0413677Y2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to a display for a fish finder that emits ultrasonic pulses into water and displays the reflected waves, as well as enlarging and displaying a part of them in parallel. .

"Prior Art" Some conventional fish finder display devices display reflected signals as display lines so that the depth direction is vertical, and the display lines are arranged in chronological order. Moreover, the display surface of the display device can be moved up and down by 2
Some systems allow detailed observation by selectively enlarging one half of the image, for example, a portion in the depth direction displayed in the upper half and displaying it in the lower half.

In this case, it has been proposed to display an enlargement marker in the lower half of the display to indicate which part of the upper half of the display the selected enlarged display is. It is conceivable to display this enlarged marker as a line extending in a direction perpendicular to the depth direction. According to such an enlarged marker, the enlarged marker and the display of the reflected wave in the display section may overlap, and in that case,
The display of reflected waves may be hidden. Even when such a situation does not occur, an enlarged marker is displayed in addition to the reflected wave display, and the number of displays on the display screen increases, which may make it difficult to read the reflected wave display.

"Means for Solving the Problem" According to this invention, the display surface of the display device is divided into a plurality of upper and lower display areas, and the first display area displays a selected part of the other second display area. It is displayed enlarged in the depth direction, and displayed as a linear enlarged marker in which the display range in the first display area is extended vertically on one side of the second display area.

In this way, according to this invention, the enlarged marker is displayed on one side of the display area in the form of a line that extends vertically, so there is little risk that the reflected wave display will be hidden by the enlarged marker. can be displayed avoiding the enlarged marker display area, and in this case, the reflected wave display is not affected at all by the enlarged marker display, and the reflected wave display can be read correctly. .

``Embodiment'' An embodiment of this invention will be described below with reference to the drawings in the case where it is applied to something controlled by an electronic computer. In the figure, 11 indicates an operation panel,
The contents set on the operation panel can be read by the CPU 12. For example, as shown in FIG. 2, the operation panel 11 is configured so that it is possible to use high frequencies (hereinafter referred to as high frequencies) and low frequencies (hereinafter referred to as low frequencies) as the frequency of the ultrasonic waves to be transmitted in this example. In this case, when high frequency is used, the detection range is set by the detection range setting means 13h, which is set by, for example, a so-called digital switch.
The detection range setting means 13l sets the range for low frequencies. The display standard displayed on the display screen should not be set from sea level, but for example, 100 meters below sea level.
200 meters or less...Shift setting levers 14h and 14l for setting display standards are provided for high frequency and low frequency, respectively. Furthermore, levers 15h and 15l are provided for moving the movable marker. These operating levers 15h and 15l are used not only to move the movable marker, but also to adjust the enlarged position by switching the switch 16. Furthermore, by operating the mode selection knob 17, there is a setting position 18 for displaying the full screen using low frequency, a setting position 19 for displaying the full screen using low frequency and high frequency simultaneously, and a setting position 19 for displaying the full screen using low frequency and high frequency at the same time. A position 21 for displaying the high frequency waves separately on the side, an operation position 22 for displaying only the high frequency on the entire screen, a position 23 for displaying the high frequency normal display and the seabed enlarged display divided into screens, and the low frequency normal display and the seabed enlarged display. Parallel display setting position 3 for enlarged display
4, a parallel display setting position 25 for a high frequency normal display and its partially enlarged display, and a parallel display setting position 2 for a low frequency normal display and its partially enlarged display.
6 can be selected. Furthermore, a switch 27 for attaching or deleting a depth marker, a button 28 for displaying the current position, an operation button 29 for modifying the followable range of the seabed, a screen brightness adjustment knob 31, and a high frequency magnification selection knob 32.
h.Low-frequency magnification selection knob 32lOther settings not shown in the figure, such as sensitivity adjustment, image feed speed selection, gain settings, markers to indicate the mesh position, and amplitude and color characteristics settings for color display. Various operating knobs are provided, including switches for synchronized operation based on signals from other fish finders.

Returning to the explanation of FIG. 1, the CPU 12 performs various operations by reading, decoding and executing programs stored in the program memory 33.
A readable/writable memory 34 is provided to store information necessary for calculations or to temporarily store information such as the status of the operation panel. A so-called input/output port 35 is provided which performs an operation for supplying signals to external parts when decoding and executing a program, or for reading signals from the outside. These operation panel 11, CPU 12, program memory 33, readable/writable memory 34, and input/output port 35 are connected to a data bus 36 and an address bus 37, respectively, and the CPU 12 and input/output port are connected to a control bus 38. .

The CPU 12 performs necessary calculations corresponding to various operation modes input from the operation panel 11 to obtain various operation parameters. For example, the period of the transmission pulse, the reception sample interval, the reception start time, etc. are calculated in the CPU 12, and the calculation results are controlled by the input/output port 35 of the timing generator 39, and the operating parameters are given through the data bus 36. . The timing generator 39 generates, for example, a transmission pulse based on the given operating parameters, drives the transmitter 41, excites the transducer 43 through the transmission/reception switch 4, and transmits the ultrasonic pulse. do. The reflected wave of the ultrasonic pulse, that is, the detection signal, is received by the transducer 43, amplified and detected by the receiver 44, and the detected output is sent to the AD converter 45, which outputs a plurality of signals corresponding to the level at regular intervals. It is converted into a bit, for example a 4-bit digital signal.

The digital detection signal is stored in the buffer memory 46. The detection signal stored in buffer memory 46 is transferred to image memory 47. This image memory 47 can be read by the so-called DMA method, that is, the CPU 1
Not only can it be read and written by the sub-scanning address generator 48, but also it can be periodically read out using the sub-scanning address obtained from the sub-scanning address generator 48 and the main-scanning address obtained from the synchronization signal generator 49. The main scanning synchronizing signal and the sub-scanning synchronizing signal obtained by the synchronizing signal generator 49 cause a raster scanning display, such as a CRT.
The display 51 is raster scan controlled, and this display 51
The readout output of the image memory 47 is sent to the synthesis circuit 5.
2 and displayed as an image. Next, generation of a scanning signal in the raster scanning display 51, synchronization signal generator 49 and image memory 4
Regarding the generation of address signals for 7, etc., the third
Let me explain with reference to the diagram. A clock is supplied from the terminal 53 to the line synchronization signal generation counter 54 and counted, and the count is converted into a predetermined value by the decoder 55, that is, one main line on the display screen 56 of the display 51 in FIG. A count value indicating the end of scanning of scanning line 57 is decoded by decoder 55 .
The output sets flip-flop 58. The line synchronization signal generation counter, that is, the main scanning counter 54 is reset by the Q output, and at the same time, the output of the flip-flop 58 becomes low level, the reset for the blanking counter 59 is released, and the clock from the terminal 53 is reset. Count. When this counter 59 counts the blanking period in main scanning, this is counted by the decoder 61.
is detected and the flip-flop 58 is reset, so the counter 59 is in the reset state,
The main scanning counter 54 starts counting again after the reset is released. Therefore, the main scanning blanking pulse 62 is obtained from the output of the flip-flop 58.

A signal indicating the end of the main scanning blanking period obtained from the output of the decoder 61 is supplied to the sub-scanning counter 64 through the gate 63. The gate 63 has the Q output of the flip-flop 65 connected to the NOR gate 66.
A high level is normally applied through the gate 63, so that the main blanking pulse is counted by the sub-scanning counter 64 through the gate 63. Sub-scanning counter 6
The output of 4 is decoded by a decoder 67, and when a predetermined number of main scanning lines are counted, that is, until the end position of the sub-scanning on the display screen, a flip-flop 65 is set by the output. The Q output becomes high level, gate 63 is closed, and therefore the counting operation of counter 64 is stopped. At the same time, the output of flip-flop 65 becomes low level, and the reset of blanking counter 68 for sub-scanning is canceled. , main scanning blanking pulses from the decoder 61 are counted. The output of the counter 68 is decoded by a decoder 69, and when the sub-scanning blanking is completed, it is detected at the output of the decoder 69, the flip-flop 65 is reset, the gate 63 is opened, and the sub-scanning counter 64 is decoded. Counting starts again and the blanking counter 68 is reset. A sub-scanning blanking pulse 71 is obtained from the output of the flip-flop 65. Blanking pulses 62, 71 are applied to raster scan display 51 in FIG. 1 to raster scan display 51.

In this embodiment, the display screen 56 is divided into upper and lower parts, that is, 1/2 in the extending direction of the scanning line 57.
The upper screen 56a and the lower screen 5 are divided into
This is a case where different images can be displayed for each of the 6b and 6b. In other words, one image can be displayed on the entire display screen 56, or the screen can be divided into upper and lower parts to display two images. Two sub-scanning address generators 72a and 72b are provided corresponding to the display screens 56a and 56b. These sub-scanning address generators 72
a, 72b are counters, for example, and gate 63
Count the output of The contents of these counts are sub-scanning addresses and are supplied as upper addresses to the image memory 47 in FIG. 1 through the gates 73a and 73b and also through the OR gate 74.

The lower address for the image memory 47 is the main scanning counter 54 in the synchronization signal generator 49.
The contents of , that is, the main scanning address are given. In the following description, the main scanning address will be referred to as the Y address, and the sub-scanning address will be referred to as the X address.

The contents of image memory 47 are read out in synchronization with raster scanning of display 51 in the following manner. For example, when one image is displayed on the entire display screen 56, one detection signal is displayed by one scanning line 57 on the display screen 56. In this case, since the display is for a fish finder, the screen 56 is generally displayed with the upper side facing the sea surface and the lower side facing the seabed. Further, in this example, the raster scanning display 51 is configured to display a color image, and the display is displayed in different colors depending on the level input to the display 51. For example, the reflected wave is from zero to the weakest. Levels are displayed in blue when the level is high, and red when the strongest and maximum level is displayed.

New data, that is, detection signals, are written to the image memory 47 in advance on the display screen 56 so that, for example, the newest detection signal is always displayed on the rightmost scanning line, and the oldest detection signal is displayed on the left side of the screen 56. To display a new signal at a determined display position. Therefore, near the end of the sub-scanning of the screen, for example, when there are n scanning lines in total, the (n-1)th scanning is detected by the decoder 67,
Based on the detection output, the sub-scanning address generator 72
The contents of a and 72b are written to write address registers, that is, X address registers 75a and 75b, respectively. This X address register 7
The contents of 5a and 75b are such that the signal from the input/output port 35 is transmitted to the gate 77 through the terminals 76a and 76b.
a, 77b, is taken into the CPU 12 via these gates and the data bus 36, and is used as a sub-scanning address when writing to the image memory 47.

As described above, the screen 56 can be divided into the upper screen 56a and the lower screen 56b to display two images, so that the detection signal for the upper screen 56a and the detection signal for the lower screen 56b can be read out. This is done separately from the reading of the data. That is, the output of the main scanning counter 54 is decoded by a decoder 55, and signals indicating the upper half and lower half of the display screen 56 are sent from the decoder 55 to terminals 78a and 78a, respectively.
78b, respectively. These terminals 78
Gates 73a and 73b are opened by the outputs of a and 78b, respectively. Therefore, on the upper screen 56a of the display screen 56, the image memory 47 is read out according to the contents of the counter 72a, and on the lower screen 56b, the image memory 47 is read out according to the contents of the counter 72b.

Furthermore, when data is written to the image memory 47, in order for the new data to be displayed, for example, on the right edge of the screen, as described above, the old data is sequentially moved to the left by one scanning line. In the case of pop-up scanning, it is moved by a predetermined value, such as by two lines. For this purpose, the sub-scanning address generator 7
The X addresses of 2a and 72b and the sub-scanning of the display 51, that is, the contents of the sub-scanning counter 64, are relatively shifted. In this example, each time data is written to the upper screen 56a and lower screen 56b in the image memory 47, the sub-scanning address generator, that is, the X counter 7
2a and 72b are subtracted by one.

In the timing generator 39 of FIG.
As shown in the figure, a set command is given to the transmission interval determining counter 81 from the input/output port 35 through the terminal 82, and a value indicating the transmission interval calculated by the CPU 12 is set via the data bus 36. In addition, reception start detection counters 84a and 8 are activated according to commands from input/output port 35 through terminals 83a and 83b.
4b, data indicating the start time of reception is set through the data bus 36. Further, data indicating the reception sample interval is stored in the reception interval register 85.
a, 85b through the data bus 36,
Terminals 86a and 8 from the input/output port 35, respectively
6b. In these explanations and in the subsequent explanations as well, the subscripts a and b of the symbols refer to the upper display screen 56a and the lower display when the display screen is divided and displayed, respectively, as can be understood from the previous explanation. This means those provided corresponding to the screen 56b.

The various operating parameters for these counters and registers in the timing generator 39 are set by the CPU 12 at the end of each transmission interval, and then the basic pulses from the terminal 87 are sent to the counters 81,
Counters 84a and 84b perform subtraction counting, and counters 88a and 88b perform addition counting. When the transmission pulse counter 81 counts as many basic pulses as the number indicating the set transmission cycle, the counter 81 generates a carry down output, and the flip-flop 89 is set by this output. On the other hand, a value corresponding to the transmission pulse width is also set for the transmission pulse width determination counter 91 via the data bus 36 in accordance with a command from the input/output port through the terminal 92, and the flip-flop 89 is set. The gate 93 is opened by this output, and the basic pulse from the terminal 87 is supplied to the counter 91 through the gate 93 and counted down. When the counter 91 outputs a carry down output, the flip-flop 89 is reset by the output. The output of flip-flop 89 is applied as a transmit pulse to transmitter 41 (FIG. 1).

An ultrasonic pulse is transmitted by this transmission pulse, and a reflected wave is returned, and when the set reception start time point is reached, the reflected wave is taken in. That is, counters 84a and 84b for the reception start point.
As mentioned above, when the basic clock at the terminal 87 is subtracted and counted and the values set there are counted, a down-digit output is produced, and the output sets the flip-flops 93a and 93b, and the respective Q outputs set the flip-flops 93a and 93b. Gates 94a and 94b are each opened. On the other hand, counters 84a, 84
OR gates 95a, 95b are generated by the lowering output of b.
through the reception interval counters 88a, 8, respectively.
8b are each reset.

From this state, the counters 88a and 88b start counting from zero, and the coincidence detection circuit 9 detects that these counted values and the contents of the reception interval registers 85a and 85b match.
6a and 96b, and each time the two match, the matching output is sent to the gate 9.
4a, 94b, and further or gates 97a, 9
7b to address counters 98a, 98b, respectively.
8b is incremented by 1, and the coincidence detection circuits 96a,
The outputs of 96b are sent to delay circuits 99a and 99b, respectively.
After a slight delay through the respective OR gates 95a and 95b, the reception interval counters 88a and 88b are reset, respectively.

Therefore, sampling pulses are obtained from the coincidence detection circuits 96a, 96b at time intervals corresponding to the values set in the reception interval registers 85a, 85b, and detection signals are written into the buffer memories 46a, 46b by these pulses. . Gate 94a,
The output of 94b is also applied to write terminals for buffer memories 46a and 46b. Furthermore, flip-flops 101a and 101b are reset by the outputs of these gates 94a and 94b, respectively, and gates 102a and 102 are reset by their outputs.
b is open.

As for writing to the memories 46a and 46b, detection signals are written in accordance with various operating modes as described above with reference to FIG. For this purpose, flip-flops 103 and 104 for display screen selection are provided. Flip-flop 103 is input/output port 35
It is set by a signal from the terminal 105 indicating that a high frequency detection image is to be displayed on the upper screen 56a, and is reset by a signal passing through the terminal 106 indicating that a low frequency detection signal is to be displayed on the upper screen 56a. . The flip-flop 104 is set by a signal indicating display on the lower screen 56b or full display by a high frequency detection signal from the input/output port through the terminal 107, and is set by a signal indicating display on the lower screen 56b or full display by a low frequency detection signal. It is reset by a command through terminal 108 shown.

When both the high frequency detection signal and the low frequency detection signal are displayed on the same screen at the same time, a high level is set in the register 111 by a signal from the input/output port through the terminal frequency 109. The output of this register 111 opens the gate 112, and the output of the gate 112 is the output of the OR gate 11.
3 and 114, respectively, to switch 115 and 1.
16 as a control signal. Also, each Q output of the flip-flops 103 and 104 is connected to the gate 11.
3,114. Switching parts 115, 116
If the control signal is high level, respectively
The output of the AD converter 45h, that is, the high frequency detection signal is output, and if the level is low, the AD converter 45l,
That is, a low frequency detection signal is output, and these switching devices 11
5 and 116 are supplied to buffer memories 46a and 46b as write data. AD converter 45
The outputs of h and 45l are compared in magnitude in a comparator 117, and if the high frequency detection signal is larger, the output of the comparator 117 becomes high level, and this is supplied to the gate 112. In this way, the high frequency detection signal is taken into the upper display buffer memory 46a, and the low frequency detection signal is taken into the lower buffer memory 46b, depending on the states of the flip-flops 103, 104 and the register 111 set from the terminals 105 to 109. The combination of acquisitions, such as

The sampling interval is determined by the values set in the sample interval registers 85a and 85b.In other words, if the sampling interval is short, the display will be enlarged, and if it is long, the display will be reduced. The starting point is determined by the reception starting point counters 84a and 84b, and when receiving from zero level without enlarging, the counter 8
4a and 84b are set to zero, and when the shift state, that is, the display reference level is set below sea level, a corresponding value is set on the counter 84.
a, 84b, and from the time the reflected wave from the display reference level arrives, the reflected wave is written into the buffer memories 46a, 46b.

The count states of address counters 98a and 98b are decoded by decoders 118a and 118b, respectively, and when the specific values are decoded, outputs are generated by selectors 119a and 119b. That is, the selectors 119a and 119b are each controlled by the state of the output of the screen division number register 121. In this example, the screen is divided into two or not divided, so the register 12
1 is given a command from the input/output port through the terminal 122, the decoder 36 writes information indicating whether or not to divide from the CPU, which is 1-bit information in this example. For example, when the output of the register 121 is at a low level, the decoder 118
A signal indicating that a value, for example, 512, corresponding to one scanning line of the display screen has been counted at a and 118b passes through selectors 119a and 119b and is applied to gates 102a and 102b.
On the other hand, when the output of the register 121 is at a high level and the screen is divided into upper and lower parts, the decoder 11
When it is detected at 8a and 118b that half the number of bits of the scanning line on the display screen, 256 in this example, has been counted, the selectors generate respective outputs. The output of these selectors is gate 1
After passing through delay circuits 123a and 123b, address counters 98a and 98b are reset, and OR gates 124a and 124b are reset.
Through this, flip-flops 101a and 101b are set, and gates 102a and 102b are therefore closed.

When outputs are generated from gates 102a and 102b, a signal is generated through terminals 125a and 125b indicating that writing of necessary data has been completed in buffer memories 46a and 46b. This is given to the CPU 12 in FIG. 1, and the CPU 12 detects the write completion signal for each buffer memory of these terminals 125a and 125b and moves to the operation of reading out the detection signal from the buffer memory. The signals from these terminals 125a and 125b are
It may be given to the CPU 12 as an interrupt, or the CPU 12 may send it to the terminals 125a, 125.
The signal may be detected while monitoring the state of b.

Buffer memory 4 is controlled by CPU 12.
To transfer the contents of 6a and 46b to the image memory 47, the CPU 12 transfers the contents of terminals 126a and 46b to the image memory 47 via the IO port.
126b to clock generators 127a, 12.
Start up 7b. Clock generator 127a, 12
7b automatically stops when a 16-bit clock is generated, and these clocks are supplied to address counters 98a and 98b through OR gates 97a and 97b, respectively, and these address counters are incremented. In this example, in order to be able to write and read detection signals to and from a large number of addresses in the image memory 47 at a relatively low speed in a short time, each data for, for example, 16 addresses is input and output in parallel, and each Since the data for each address is, for example, 4 bits, 16 bits×4 bits are simultaneously written in the image memory 47.

That is, the data read out from the buffer memories 46a and 46b, that is, the detection signal, is supplied to the image memory 47 through the terminal 128. On the other hand, CPU1
2 to the image memory 47 through the address bus 37 and the address switching circuit 129 in FIG.
The address for is given. The address switching circuit 129 is controlled to switch the supplied address through the IO port 35. Normally, as mentioned above, the Y address from the synchronizing signal generator 49 and the X address from the address generator 48 are supplied to the image memory 47 as addresses and read out, but when writing, the X address is The address switching circuit 129 is controlled so that the image is supplied from the CPU 12 to the image memory 47 via the address bus 37. At the time of writing, the X address is designated by the contents of the write address registers 75a and 75b in FIG. 3, and the Y address at that time is given by the synchronization signal generator 49 to designate the address for the image memory 47. Although not shown in the figure, in this write operation, the image memory 47 is also controlled so that 16 addresses are written in parallel to the memory 47. A detection signal is transferred from the CPU 12 to each of the 16 addresses of the buffer memories 46a and 46b, and the terminals 126a and 126b are
Signals are applied as write commands through the input/output ports, read from the buffer memory, and supplied to the image memory 47.

As described above, a transmission pulse is transmitted and its reflected wave is received according to the operation mode corresponding to the setting state of the scanning panel, but the signal indicating the end of the transmission cycle is the output of the transmission cycle counter 81. The signal is generated through the terminal 130 and is supplied to the CPU 12. In the CPU 12, if this occurs as an interrupt or by monitoring the signal of this terminal 130 and knowing that this has occurred due to a change in its state,
Operating parameters pre-calculated in the CPU 12,
In other words, in Fig. 5, the transmission interval, transmission pulse width,
The above operation is repeated by giving the reception start point, sample interval, etc. to the timing generator 39, respectively.

When the seabed is detected, the detected depth can also be displayed. For this reason, the seabed is generally located within a certain range of the previous detection points, and the detection is performed by following the seabed. Detection is performed by taking advantage of the fact that the reflection of the seabed is much larger than that of other waves, but the deeper the seabed is, the lower the level of the received reflected waves even with waves reflected from the seafloor. Therefore, a reference signal for determining the seabed is selected depending on the depth of the seabed.

That is, each time a down-down output is generated from the transmission cycle counter 81, the depth counter 131 is reset and starts counting the basic pulses at the terminal 87 from zero, and the count contents are supplied to the depth level discrimination circuit 132, 132 generates different reference signals from the seabed level reference selector 133 depending on the depth. That is, when the depth is deep, the reference signal generated from the seabed level reference selector 133 is set to a low value. This reference signal is expressed in 4 bits, for example, and is divided between the output of the switch 116 and the comparator 13.
4 is compared.

As long as the output of the seabed level reference selector 133 is greater than the output of the switch 116 as a result of the comparison of the comparator 134, the output of the comparator 134 is used to set the seabed confirmation counter 1.
35 is in a reset state. However, when this is reversed and the reception level becomes higher than the reference signal of the seabed level reference selector 133, the reset of the seabed confirmation counter 135 by the output of the comparator 134 is canceled, and this counter 135 counts the reference pulses from the terminal 87. This counter 135 successively counts a predetermined number of reference pulses to confirm that the reflected wave is from the ocean floor. This means that the decoder 136 detects that the seabed confirmation counter 135 has counted a predetermined number. The output gate of decoder 136 is fed to 138 and to the clock terminal of a D-type flip-flop 137 to read the high level on its data terminal. Its output is fed to gate 138 and decoder 1
A pulse passes through gate 138 at the moment the detected output from 36 is obtained. In addition, flip-flop 1
37 is reset in advance by the output of the transmission cycle counter 81 through the gate 139.

Furthermore, the detection of the seabed is limited to a certain range to prevent a false detection of the seabed due to strong reflections not from the seabed but from dense, thick schools of fish along the way. In other words, the gate 138 is opened only between a portion shallower by Δ and a portion deeper by Δ with respect to the ocean floor, and the output of the decoder 136 obtained at that time is selected as the ocean floor. For this purpose, counters 141 and 142 are provided, and counter 141 has terminal 14.
3, in response to a command from the input/output port, the data indicating a value of the seabed shallowing by △ is stored from the data bus 36 from the CPU 12, and the value of 2△ is stored in the counter 142 by a command from the input/output port through the terminal 144. is set by the CPU 12. The counter 141 subtracts and counts the reference pulse from the terminal 87. Therefore, when the point reaches a point shallower than the set seabed by △, the flip-flop 145 is set by the output of the counter 141, and the gate 138 is opened by its Q output. with gate 1
46 will be held. Terminal 8 passed through gate 146
The counter 142 subtracts the reference pulse of 7, counts 2△, and when the counter 142 outputs a carry down, the flip-flop 145 is reset and the gate 138 is closed. In this way, only the outputs of the decoder 136 that correspond to a range of ±△ with respect to the ocean floor pass through the gate 138.
The output of flip-flop 145 also resets flip-flop 137 through OR gate 139.

In this way, the output of the gate 138 is obtained as a seabed detection signal, which is transmitted to the terminal 14.
7 to the CPU 12. This acts as an interrupt signal in the CPU 12, or
CPU12 detects the seabed detection signal and CPU1
2 controls the input/output port in FIG. 5, opens the gate 149 through the terminal 148, and sends the contents of the depth counter 131 to the CPU through the data bus 36.
Import into 12. Therefore, the CPU 12 can know the depth of the ocean floor.

Generally, a so-called depth marker corresponding to a scale indicating depth may be displayed on the display screen 56 of the raster scanning display 51 together with the displayed image. For example, in FIG. 6, depth markers 154 indicating depth are displayed on the upper screen 56a of the display screen 56 at appropriate intervals from an oscillation line 151 corresponding to the sea surface toward an image 152 of the ocean floor. In FIG. 6, an image 153 above a seabed image 154 is, for example, an image of a school of fish. The depth marker of the oscillation line 151 indicates 0 meters, and depending on the set detection range, for example, a depth marker 154 is placed at the deepest position of 100 meters, and a white line is drawn horizontally at the middle 50 meters. Is displayed. The lower screen 56b shows a case where a part of the display image on the upper screen 56a is enlarged and displayed, and the enlarged display is displayed on the upper screen 5.
This is the case when the moving marker 155 shown in 0a is enlarged, and the detected position of the moving marker 155 can be easily known and the position can be freely controlled. For example, by controlling the moving marker lever 15h or 15l in FIG. 2 and aligning the moving marker 155 with the position of the fish school image 153, that part is enlarged and displayed on the lower screen 56b, and its depth is also displayed. . This moving marker 155 is displayed, for example, in orange.

Furthermore, in this invention, as shown in Figure 6,
An enlargement marker 156 indicating an enlarged portion of the normal display image shown on the upper screen 56a on the lower screen 56b is displayed as a vertical line on one side of the screen 56a, on the right side in this example. Fixed markers, that is, depth markers 154 are also displayed on the lower screen 56b as white horizontal lines at appropriate depths. Further, a boundary line 157 indicating the boundary position between the upper screen 56a and the lower screen 56b is displayed, for example, as a red line.

In order to display such a marker, for example in FIG. The signal is applied to an AND circuit 63. flip flop 15
When 8 is set, counters 64 and 72
The counting operations of a and 72b are stopped. Further, the output of the flip-flop 158 is supplied to the reset terminal of the counter 159, and when the flip-flop 158 is set, the reset of the counter 159 is released. Therefore, counter 159 counts the blanking pulses from decoder 61. In other words, when the sub-scanning blanking period ends, the counter 159 immediately starts counting, and the enlarged marker 156
When counting the number corresponding to the thickness of the decoder 1,
Output is obtained from 61 and flip-flop 158
is reset.

The Q output and the output of the flip-flop 158 are supplied to gates 163 and 164, respectively, and the readout output of the image memory 47 is supplied to the gate 164. Therefore, when the enlarged marker is output, the output of the image memory 47 is stopped from being supplied to the display 51. On the other hand, data a indicating the upper depth of the enlarged marker 156 is sent from the CPU 12 to the registers 165 and 166 via the data bus 36.
and data b indicating the lower depth are given as positions on the scanning line on the display screen 56, and are set by a set command through terminals 167 and 168 from the input/output port. register 16
The value set to 5,167 is determined by calculation from the values set by the enlargement knobs 32h, 32l and the moving marker lever 15h or 15l, respectively, and the set value of the detection range, etc., as described in connection with FIG. be done.

The values of these registers 165 and 166 are supplied to coincidence detection circuits 169 and 171.
69 and 171 are given the Y address from the main address counter 54, and when they match, the flip-flop 172 is set or reset by the output. That is, the flip-flop 172 is set by the coincidence output indicating the upper end of the enlarged marker from the coincidence detection circuit 169, and the gate 163 is opened by its Q output. Therefore, at the gate 163, each Q of the flip-flops 158 and 172 is
If the outputs match, the step is OR gate 1.
73, and then sequentially through an AND gate 174, an OR gate 175, and an OR gate 176. In this case, the level of the output of the gate 163 is selected so that a predetermined color, for example, orange, is displayed on the display screen of the display 51.

The flip-flop 172 is reset by the coincidence detection output from the coincidence detection circuit 171. In this way, the enlargement marker 156 indicating the enlargement range is displayed on the display screen of the display 51. Therefore, it is possible to intuitively see which part of the enlarged image displayed on the lower screen 56b is enlarged on the upper screen 56a using the enlargement marker 156. It is possible to display the enlarged marker 156 as a horizontal line like the fixed marker 154 or the movable marker 155 without providing such a thick vertical line, but in that case, the number of horizontal lines would increase and it would be difficult to see. , this display of the enlarged marker 156 using vertical lines is easier to see. This vertical line enlarged marker 156 is CPU 12
It can also be applied to fish finders other than fish finders that use

To display the moving marker 155, for example, register 1 is input from the input/output port through the terminal 177.
A set command is given to 78 and the CPU 12
A Y address indicating the display position of the moving marker 155 is given to the register 178 via the data bus 36. Y indicates this movement marker
The address is compared with the Y address in the match detection circuit 179, and if the two match, the output is supplied to the OR gate 175 and the inverter 1
81 to AND gate 172, and passage through gate 172 is blocked. In this case, the output of the coincidence detection circuit 179 is set to a level that displays, for example, green, and the moving marker 155 is displayed as a green line. The display position of the moving marker 155 is determined by calculation in the CPU 12, but this is because the operating lever of the moving marker is controlled as described with reference to FIG. Starts to move in a shallow direction.

While the operating lever of the moving marker is controlled, for example, clocks are counted, and each time the clock count reaches a certain number, the moving marker 155 is moved on the display screen by a corresponding amount. Even if the set detection range changes, the predetermined number of clocks for moving the moving marker is changed so that the moving speed of the moving marker 155 remains constant on the screen 56.

As shown in FIG. 6, when enlarged display and normal display are performed simultaneously on the display screen 56, the moving speed of the moving marker in the enlarged portion becomes very fast, making it difficult to read the moving marker accurately. becomes difficult to set. Therefore, in such a case, the CPU 12 performs the following process to set the calculated value in the register 178 for setting the moving marker.

That is, as shown in FIG. 7, in step _S1 , it is checked whether the operating lever of the moving marker is turned on or off, and if it is off, the process moves to other processing, but if it is on, the process goes to step _S2 .
At step S3, it is checked whether a pulse (clock) exists or not, and if so, it is checked at step _S3 whether or not the position of the moving marker 155 is in the enlarged portion of the normal display screen. If it is not in the counter section, a constant number corresponding to the detection range is calculated in step _S4 , and this is set as K in the register. If the moving marker is in the enlarged area, a constant number K corresponding to the enlargement rate is set in step _S5 , and this value is selected to be larger than the value when it is not in the previous enlarged area. Thereafter, in step _S6 , after setting these K, the counter value C is incremented by 1, and in step _S7 , it is checked whether the contents of the counter match the previously set K. If they do not match, the process returns to step _S2 , and if they do match, the value indicating the position of the moving marker 155 is incremented by, for example _, plus 1 or minus 1, depending on the operating direction of the moving marker lever. At the same time, the content C of the counter is made zero and the process returns to step _S1 . By performing such operations, it is possible to finely set the movement marker within the enlarged range. The Y address corresponding to the movement marker 155 thus given is set in the register 178 in FIG. 3 at regular intervals.

For example, a Y address is decoded by a decoder 182 to display the fixed depth marker 154, and the output of the decoder is selected by a selector 183 according to the contents of the register 121 indicating the number of screen divisions. For example, when four depth markers 154 are displayed on the screen in normal display, eight depth markers appear if the display screen is divided into screens 56a and 56b. Each position of the depth marker 154 is determined in advance on the display screen 56. For example, when displaying the entire screen as one image without being divided, the position of the Y address for every 1/4 on each scanning line is determined in advance. The decoder 18 outputs it through the selector 183, and when the screen is divided into the upper screen 56a and the lower screen 56b and is displayed, the Y address for each 1/8 of each operation line is output from the decoder 182 through the selector 183. . The output of the selector 183 is supplied to the OR gate 176, and at this time the output of the selector 183 is selected to a level that displays, for example, a white level.

If data indicating the depth is directly displayed in the form of numbers near each marker, especially the depth marker 154, moving marker 155, or seafloor image 152, the data will be very easy to read. In order to display such numbers, a character code memory 184 is provided in FIG. This character code memory 184 is also read out using the so-called DMA method. The read address for this character code memory 184 is given by a signal from the synchronizing signal generator 49, that is, the contents of the Y address counter 54 and the X address counter 64 in FIG. CPU12
This character code memory 184 is accessed from the address bus 37 and the switch 185, and the contents of the data bus 36 at that time can be written into the memory 184.

For example, one character is displayed as an 8×8 dot pattern, and the position on the display screen 56 to be displayed is specified by dividing the display screen 56 by the display area of one character. be done. The display screen 56 is displayed by an address in which the lower three bits of the contents of the Y address counter 54 and the X address counter 64 are omitted.
The parts that should be displayed above are shown. At each address position of the character code memory 184, a character to be displayed at a corresponding location on the display screen 56, a color of the character to be displayed, and data indicating whether or not to display the character are stored, respectively. Character code memory 184
The contents of are read out by the Y address and X address from the synchronization signal generator 49 as described above, and the read output is sent to the character pattern generator 186
is applied to generate the character pattern, and the pattern is supplied to the display 51 through the synthesis circuit 59.

For example, as shown in FIG. 8, the Y address of the counter 54 and the Y address of the address bus 37 are transferred to the character code memory 18 through the
4, but the lower 3 bits of the Y address are not given,
The lower 3 bits are the character pattern generator 186
supplied to On the other hand, the X address of the X address counter 64 and the address bus 37 is set by the switch 185.
The data is supplied to the character code memory 184 through the character code memory 184.
The switch 185 is controlled by the control bus 38, and during writing, the output of the address bus 37 is selected and supplied as an address to the character code memory 184, and data from the data bus 36 is written. The lower three bits of the X address of the X counter 64 are not supplied to the character code memory 184 but are supplied to the character pattern generator 186. At the time of reading, each address of the Y address counter 54 and the X address counter 64 is stored in the character code memory 1.
84.

The code indicating the color of the character to be displayed in the signal read from the character code memory 184 is transferred to the switch 18.
8, and this code is switched with the readout output from the image memory 47 and supplied to the display 51. On the other hand, the output of the terminal 189 of the character code memory 184 is supplied to the NAND gate 191, and the code indicating the displayed character is supplied to the character pattern generator 186.

The character pattern generator 186 is given the lower 3 bits of the Y address and the lower 3 bits of the X address, and data (1 bit) indicating the presence or absence of each dot in the pattern to be generated at each address position is sequentially generated. The generated pattern is passed through the NAND gate 191 to the switch 188.
supplied to The output of NAND gate 191 is supplied to switch 188 through switch 192.
When the output of the NAND gate 191 is at a high level, the output of the image memory 47 of the switch 188 is selected, and when it is at a low level, the color code being output from the character code memory 184 is selected. Accordingly, each character pattern output from the character pattern generator 186 is outputted from the character code memory 184 by dot output in the matrix and supplied to the display 51.

In this way, characters, that is, numerical values, are displayed on the display screen 56 of the display device 51. In this case, in order to make the characters easier to see, the dot matrix of the characters is displayed in the area where the dot matrix of the characters should be displayed, for example, in an 8×8 dot pattern. , within the 8×8 area to be displayed, the background color is set so that it does not match the color of the display image, especially the color of the display of a school of fish or the display of the seabed. Therefore, within one character to be displayed, all output from the image memory 47 is prevented within that area. Therefore, the output of the terminal 189 is also supplied to a NAND gate 193, and the output of the character pattern generator 186 is supplied to this NAND gate 193 through an inverter 194. Accordingly, in the NAND gate 193, although this is an area where a character should be displayed, it indicates that there are no dots in the character pattern, and when the output of this NAND gate 193 is at a low level, the output of the switch 188 is transferred to the image memory 47. For example, a zero level is output without selecting the level, and that level becomes the background color. In this way, when the number is displayed on the display screen as shown in FIG. 6, the display area of that one character,
In other words, no image is displayed in the area surrounded by the dotted line, and the displayed characters are easy to see.

The display for the depth marker 154 and the display for the moving marker 155 each display a number indicating the depth near the display marker. These displayed numbers vary depending on each operation set by the operation panel.
It is determined by calculation by the CPU 12. When characters are displayed on the display screen in this way, an image or the like is displayed in the character area.In other words, displaying a constant background color is performed by the CPU 12 as shown in this embodiment. The present invention can be applied not only to fish finders using , but also to general displays using raster scanning displays.

For example, there is a display method in which the seabed is set as a reference and the seabed forms one horizontal line, and the state above the seabed is displayed. The present invention can also be applied in that case. Information for this purpose is obtained in the same manner as in the past. In addition, various combinations of seabed display and split display can be performed in this way, that is, for example, as shown in FIG. 9, the display screen 56
In the above, a normal display image is displayed on the upper screen 56a, the upper half 56c of the lower screen 56b is partially enlarged, and the lower half 56d is displayed as the bottom. The enlarged portion in the upper half 56c is displayed on the normal display of the upper screen 56a by the enlarged marker 156, and similarly the displayed portion in the lower half 56d is displayed by the bottom marker 195. In this case, the enlarged marker 156 is displayed in yellow, and the bottom marker 195 is displayed in a color different from orange. These markers 156,
The overlapping portion of markers 195 is displayed in brown, and even if the markers 156 and 195 overlap, the respective display ranges can be determined.

Fixed depth marker 1 in case of text display
The text indicating the depth for 54 is displayed in the same white color corresponding to the color of the marker, and the text indicating the depth indicated by the moving marker 155 is displayed in green like the moving marker 155. For example, the character 197 indicating the depth can be displayed in yellow, and different display colors can be used depending on each display object to avoid misreading the displayed content. If the displayed image becomes difficult to see due to the display of text, as shown in FIG. cannot be given to Displaying the magnification marker 156, bottom marker 195, etc. as vertical lines to indicate the display range is not limited to this example, and can be applied to various display devices. This display is also possible in an example that does not use a computer.

In FIG. 1, the portion that detects the seabed described with reference to FIG. 5 is represented as a seabed detection section 198. Further, the basic pulse from the terminal 87 is displayed as a basic pulse wave generator 199, and the generated basic pulse is determined in correspondence with the sampling rate for pixels on the main scanning line in the minimum detection range. Therefore, the minimum detection range is 10 meters.
When the number of pixels in one scanning line of the display screen is 512, the speed of sound in water is 155 m/sec, and since this is the round trip time, 512 x 20/1500 = 37 kHz is selected as the basic pulse.

If the detection signal is written a plurality of times in the buffer memory 46 and then transferred to the image memory 47 as one detection signal, it may be done as shown in FIG. 10, for example. That is, the output of the AD converter 45 is supplied to the buffer memory 46 through the buffer memory switch 201, and the output is sent to the address counter 9.
Writing is performed using address No.8. When writing of one detection signal is completed, as mentioned earlier, a write end signal is generated from the selector 119 to the terminal 125, and the CPU 12 detects this signal.
If the CPU 12 does not issue a transfer command, that is, does not issue a set command to the flip-flop 203 from the input/output port through the terminal 202, the flip-flop 203 is in a reset state, and its Q output is at a low level, which causes the NOR gate 20
4, and the NOR gate 204 is given to the switch 201 as a control signal. When the output of the NOR gate 204 is low level, the switch 201 switches the output of the AD converter 45 to the buffer memory 46.
If the level is high, the output of the register 205 is supplied to the buffer memory 46.

Therefore, when the next detection information is received while the detection signal is stored in the buffer memory 46 without being read out, the contents of the buffer memory 46 are supplied to the register 205, and the contents of the register 205 and the AD converter 45 are The comparator 206 compares the currently detected information. As a result of the comparison, if the current one is larger than the previous one, comparator 2
The output of 06 becomes high level, therefore the output of NOR gate 204 becomes low level, and the switch 201 becomes
New data from AD converter 45 is stored in buffer memory 46. However, if the level of the previous signal in the comparator 206 is high, the output of the NOR gate 204 becomes high level, the switch 201 selects the output of the register 205, and the previous storage contents are stored in the buffer memory 46. In this way, even if the level drops due to some kind of noise, parts of the data with high levels remain.

corresponding to the feed rate set on the operation panel.
When a read command is applied to terminal 202 from CPU 12, flip-flop 203 is set, gate 207 is opened, and data read from buffer memory 46 is supplied to image memory 47 through register 205. At the same time, when reading from buffer memory 46 is completed, flip-flop 203 is reset. While flip-flop 203 is set, the output of NAND gate 204 is always at a low level regardless of the output of comparator 206, and switch 201 inputs the output of AD converter 45 to buffer memory 46.

The flow of the operation in the CPU 12 mentioned above will be explained with reference to FIG. 11. When the power is first turned on, as shown in FIG. _11A , interrupts from the outside are prohibited in step S11, and in step _S12 , each memory, That is, the image memory 47, character code memory 184, etc. are reset to the initial state,
Further, in step _S13 , various setting states of the operation panel 11 are read, in step _S14 , various operating parameters are calculated and updated based on the reading, and then, in step _S15 , interrupts are permitted.

After that, if no other routine is performed or if no interrupt processing is being performed, the settings on the operation panel 11 are always read in step _S16 , and whether or not there has been a change in the settings is checked in step _S17 . checked,
If there is no change, the process returns to step _S16 , and if there is a change, the operating parameters are calculated and the display is updated based on the change in step _S18 , and then the process returns to step _S16 . In other words, the setting state of the operation panel 11 is constantly monitored and operating parameters are calculated accordingly.

As shown in Figure 11B, the transmission end signal is sent to terminal 1.
30, the CPU 12 disables interrupts in step _S19 , sets various operating parameters calculated so far for the timing generator 39 and other various parts in step _S21 , and then cancels the interrupt in step _S22 . This operation ends.

Further, when a signal indicating that the seabed has been detected is obtained at the terminal 147 in FIG. 5, interrupts are disabled in step _S23 , as shown in FIG. 11c, and then in step _S24.
The display of the seabed depth is updated in step _S25 , the seabed detection range, that is, the value to be set in the counters 141 and 142 in FIG. 5, is updated, and the interrupt is canceled in step _S26 .

Furthermore, when the completion of reading of the buffer memory is detected from _the terminal ₁₂₅ , as shown in FIG. is carried out, and in step _S29 , the image of the display screen on which the detection signal is to be displayed is sent, and in step _S31 , the interrupt prohibition is canceled. still,
It is not necessary to perform all of these operations; for example, the operation based on detection of the seabed can be stopped, the width of the transmitted pulse can be constant, and various functions can be performed as necessary. You can also remove or add .

"Effect of the invention" As described above, according to this invention, the enlarged portion of the lower screen is displayed as a vertical line enlarged marker on one side of the normal display image of the upper screen, and the normal display image You can immediately know which part of the image is being enlarged. Moreover, the enlarged marker is 1
Since the normal display image is displayed as a vertical line on the side, the normal display image is not affected by the enlarged marker, and the normal display image can be read correctly.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the entirety of the fish finder according to this invention, Figure 2 is a diagram showing part of its operation panel, and Figure 3 shows the generation of the scanning signal of the display and the generation of various markers. Figure 4 is a diagram showing the display screen of the display unit, Figure 5 is a block diagram showing an example of the timing generator, bottom detector, buffer memory, and read/write control section, and Figure 6 is a diagram showing an example of the display on the display screen. Figure 7 is an operation flowchart for changing the moving speed of the moving marker in the enlarged part, Figure 8 is a diagram showing an example of the composite part of the character code generation signal and the output of the image memory, and Figure 9 is A diagram showing another example of the display state of the display screen, FIG. 10 is a diagram showing an example of buffer memory storage control when slowing down the feed speed from the buffer memory, and FIG. 11 is a diagram showing the CPU
It is an operation flowchart. 11...Operation panel, 12...CPU, 33...
...Program memory, 34...Writable memory, 35...I/O port, 36...Data bus, 37...Address bus, 38...Control bus,
39...timing generator, 41...transmitter, 4
2... Transmitter/receiver switch, 43... Transducer/receiver, 44...
Receiver, 45...AD converter, 46...Buffer memory, 47...Image memory, 51...Raster scanning display, 52...Synthesizing circuit, 48...Sub-scanning address generator, 49...Synchronizing signal generation Vessel, 98...
...Address counter, 125...Buffer memory data import end signal generation terminal, 129, 185
... Address switching circuit, 130 ... Transmission cycle end signal terminal, 131 ... Depth counter, 149 ...
Depth detection output terminal, 184...Character code memory, 186...Character pattern generator, 198...
Seabed detection section, 199...Basic pulse generator.

Claims (1)

[Claims for Utility Model Registration] Reflected signals are displayed as display lines so that the depth direction is the vertical direction, and the display lines are arranged and displayed in chronological order, and the display surface is arranged vertically in multiple display areas. The selected part in the depth direction of the other second display area is displayed enlarged in the depth direction in the first display area, and the enlarged marker indicating the selected part is displayed in the second display area. In the display device of a fish finder in which is displayed, the enlarged marker is displayed as a linear marker extending vertically to reach the upper and lower ends of the selected portion on one side of the second display area. A distinctive feature of the fish finder display device.