JPH04130934A - Terminal for detecting memory parity error generating address - Google Patents

Abstract

PURPOSE:To enable a user to specify an address generating a memory parity error at the time of generating the parity error by providing this memory parity error generating address detecting terminal with a function for checking the parity check of data read out from a memory corresponding to a reading address. CONSTITUTION:A CPU 1 specifies one of addresses A1,A2,... An and reads out data corresponding to the specified address from a memory 2 through an address bus 6. At the time of detecting the generation of a memory parity error, a memory parity checking circuit 3 activates a memory parity error generating signal and supplies the memory parity error generation signal to the clock terminal CP of a corresponding flip flop(FF) circuit out of FF circuits 4-1,4-2,...4-n and the state of the address generating the error is latched in the FF circuit concerned. On the other hand, a high level signal corresponding to the input of the latched address is generated on the output side of the FF circuit, an LED corresponding to the high level signal is turned on out of n LEDs 5-1,5-2,...5-n, so that the address generating the memory parity check error can be specified by its lighting display.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory parity error occurrence address detection terminal, and more particularly to a memory parity error occurrence address that makes it possible to identify the parity error occurrence address of a terminal having a memory parity check circuit. Regarding a detection circuit.

[Conventional technology]

Conventionally, in a terminal equipped with a memory parity check circuit, when a memory parity error occurs, the user has to check the NMI (Non Maskable) of the terminal, for example.
e Interrupt) processing, an error message or
The occurrence of a parity error was confirmed by a lamp indicating the occurrence of a parity error.

[Problem to be solved by the invention]

The above-mentioned conventional parity error processing has the disadvantage that no information is left when a parity error occurs, and although the user can confirm that a parity error has occurred, it is not possible to confirm whether a memory parity error has occurred anywhere. .

[Means to solve the problem]

A memory parity error occurrence address detection terminal according to the present invention is a terminal equipped with a memory parity check circuit that performs a parity check on data read from a memory under the control of a CPU, in which a memory parity error occurs when a memory parity error occurs. It has scales that detect and display the address by lighting it up.

Further, the memory parity error occurrence address detection terminal of the present invention is provided with the same number of address latch circuits as the address latches and a plurality of semiconductor light emitting elements lit by the outputs of these address latch circuits at branch destinations of the address bus, The address latch circuit is configured to control the address latch circuit to output an output corresponding to an address where a memory parity error has occurred.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The embodiment shown in FIG. 1 includes a CPU, a memory 2 connected to the CPU via an address bus 6, and a memory 2 that reads data at a specified address under the control of the CPU, and a parity error in the data read from the memory 2. a memory parity check circuit 3 which checks a memory parity error and outputs a memory parity error occurrence signal when a memory parity error exists;
n flip-flop circuits 4-1, 4-2 as n address latch circuits that input n addresses Al, A2, . . . An branched from n address bus lines included in the address bus 6; ...4-n and power supply ■DD
is supplied to the flip-flop circuit 4 via the resistor R.
-1.4-2. ... LED5-1.5- as a plurality of n semiconductor light emitting elements that are connected to the output of 4-n and turn on corresponding to the state of the address latched by the memory parity error generation signal. 2. -5
-n.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

The CPUI has addresses Al, A2. -An is specified and data is read from the memory 2 via the address bus 6. When the memory parity check circuit 3 detects the occurrence of a memory parity error, the memory parity error occurrence signal becomes active, and this is activated by the 7 lip-flop circuit 4-1.4.
-2. ...is supplied to the clock terminal CP of 4-n,
These flip-flop circuits latch the address state at that time. A high level signal corresponding to the input of the latched address is generated on the output side of the flip-flop circuit, and the n LEDs 4-1, 4-2, . ...
The corresponding one of 4-n lights up, which causes the corresponding L
The ED lights up, and the address where the memory parity check error occurred can be identified by the lighting display.

In the above-described embodiment, the flip-flop 11 circuit is used as the address latch circuit, but it is clear that this may be replaced with any number of address latch circuits having the same function.

〔Effect of the invention〕

As explained above, the present invention has a function of checking the parity of data read from memory in accordance with the read address, so that when a memory parity error occurs, the user can identify the address where the parity error occurred. The effect is that it can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...CPU, 2...Memory, 3...Memory parity check circuit, 4-1 to 4-n...Flip-flop circuit, 5-1 to 5-n・LED.

Claims (1)

[Claims] 1. In a terminal equipped with a memory parity check circuit that performs a parity check on data read from memory under the control of a CPU, a memory parity error occurs when a memory parity error occurs. A memory parity error occurrence address detection terminal characterized by being capable of detecting an address and displaying it by lighting it. 2. The branch destination of the address bus is provided with address latch circuits of the same number as address latches and a plurality of semiconductor light emitting elements that are lit by the outputs of these address latch circuits, respectively,
2. A memory parity error occurrence address detection terminal according to claim 1, wherein said address latch circuit is controlled to output an output corresponding to an address where a memory parity error has occurred.