JPH04130748A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To screen all MIS capacities with high accuracy and surely by a method wherein an electrode for capacity inspection use is formed at the stage of a wafer, a definite voltage is applied, a MIS capacity having a possibility of a failure at an early stage is destroyed and the electrode for capacity inspection use is removed. CONSTITUTION:An insulating film 8 by an SiO2 film is formed selectively on the main face of a wafer 20; and electrodes 32, 33, for capacity inspection use, which are composed of Al are formed at contact holes 30, 31 where the insulating film 8 has not been formed. The electrodes 32 for capacity inspection use on one side are overlapped with an insulating film 4 for capacity use so as to come into contact with it; and the electrodes 33 for capacity inspection use on the other side are overlapped with a capacity formation part 2 so as to come into contact with the part. Probe needles 40 for a wafer prober are pushed to inspection terminals 36 in a chip region 34, and an inspection voltage is applied. An intrinsic dielectric breakdown voltage of an Si3N4 film is applied to the insulating film 4 for capacity use for a short time of less than one second; and a capacity is destroyed so as to cause a failure at an early stage. Then, the insulating film 4, for capacity use, which has been destroyed by the wafer prober is detected; then, the electrodes 32, 33 for capacity inspection use are etched and removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a technique that is effective when applied to a screening technique for the capacitance of a semiconductor integrated circuit device that has a capacitance due to an insulating film. .

[Conventional technology]

2. Description of the Related Art Semiconductor devices such as ICs and LSIs are becoming increasingly finer in element structure as they become more highly integrated and performant. As the element structure becomes finer in this way, for example,
National Technical Report (Na
tional Technical Report)”1
As described in February 1986 issue, P2S5-P162, the electric field inside the element increases. Therefore, the degradation stress during operation of integrated circuits becomes more severe,
As pointed out in the above-mentioned literature, the thin oxide film also deteriorates over time (destruction over time). In the said document, DRA
The oxide film used for the capacitive element of the memory cell in M is
256 K D R A M (Dynamic Ra
In the case of domAccess Memory (anytime read/write memory element), the thickness is about 200 to 150, and in the case of IM-DRAM, it is about 100. D.R.
In the case of AM, an electric field of 5 MV/cm is applied to the oxide film, which is close to the IOMV/cm of the oxide film's intrinsic breakdown electric field, which is used for boat fishing, and is a harsh field for oxide films. From a credibility perspective, TDDB (TimeDependent)
It is described that the deterioration phenomenon of the oxide film called dielectric breakdown (dielectric breakdown over time) becomes a serious problem. In addition, this document also states that in an accelerated life test for the dielectric of a memory cell capacitor,
An example is disclosed in which screening was performed with an acceleration factor of approximately 1000 times (10').

-4. Regarding the capacitor'MA membrane, see "Electronics J, February 1989 issue, published by Ohmsha, P47-P
51.

[Problem to be solved by the invention]

As ICs and LSIs become more highly integrated and miniaturized, acoustic ICs
There has been an increasing customer need to reduce the number of parts by incorporating external capacitors in consumer linear ICs such as , and television ICs.

On the other hand, conventional large capacity MOS (M
etal Oxide Sem1conductor)
Although ICs have been developed using capacitors, the chip size has increased and there have been problems with Ml uniformity in ffl film formation.

Therefore, the present applicant has proposed that the dielectric constant is superior to that of 5iO1 film, which allows the capacitance per unit area to be increased and the capacitance area to be reduced.Furthermore, because the capacitance accuracy is high, the variation in film thickness is small. We considered using a nitride (Si3Na) film because of its advantage of being thinner. For example, in the case of conventional MO3 capacity,
Since the dielectric constant of a 5loz film with a film thickness of 170 nm is 3.9, the capacitance per unit area is 2.04XIO
-'pF/μm, and the capacitance area per 100 pF is 700 μm. On the other hand, in the case of nitride capacitance, the dielectric constant is 7.5, which is slightly less than twice that of the 5iCh film, and the film thickness can be reduced to approximately half, 80 nm, so the capacitance per unit area is , 8,15xlO-'
pF/μm, and the capacitance area per 100 pF is 3
The opening is as small as 38 μm. Therefore, by employing a nitride capacitor, for example, higher integration of the capacitor density can be achieved.

However, MTS (Met
al In5ulator Se+5iconduct
or) The capacitance is as thin as 80 nm in thickness of the 5i384 film,
Screening for time-related breakdown of the insulating film is also necessary from the viewpoint of reliability.

Conventionally, the screening conditions for oxide film breakdown over time have been set to 103 to 1 compared to normal usage conditions due to high voltage acceleration.
Screening is performed at a voltage equivalent to 0.04 times.

The applicant uses QCTEG (ΩualHyContr) in the process to check for destruction of thin oxide films.
ol Te5t Elementary Group)
Accordingly, a method is adopted in which early failures are removed by checking several chip parts (semiconductor integrated circuit device parts) per wafer and finally aging the product. This method is called MOS FET (Field Effect).
This is a standard specification for transistor (field effect transistor) products, but is rarely implemented for bipolar linear products.

This time, aging was applied as a screening for the initial failure mode of MIS container 1 in bipolar linear, but the inventors found that there were problems as described below.

(1) In bipolar linear ICs, the voltage applied to the capacitor is determined by the power supply voltage and the circuit, so in most cases it is not possible to apply an arbitrary voltage to the capacitive element, for example, a voltage that significantly exceeds the device maximum rating. .

(2) Therefore, the applicant predicts the failure rate due to capacity and determines the aging conditions, but this requires consideration of whether the screening conditions are appropriate for each product, which is time-consuming. It costs a lot.

(3) Also, under the aging conditions determined in this way,
It cannot be said that a substantial amount of screening is being carried out. Therefore, it becomes impossible to completely remove a device having an incomplete capacity, and the device that cannot be removed will fail (initial failure) during actual use by the customer.

(4) Also, due to (3), it is not possible to apply a specified voltage to the entire capacitance at the product stage.

(5) Bipolar linear IC products have a low unit price, and the work of attaching and detaching the product during aging is troublesome, leading to a rise in aging costs.

Particularly in the case of surface-mounted products, it takes time and effort to attach and detach the product to an aging machine, and in some cases, there are also inconveniences such as the aging cost becoming close to the product cost.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can accurately and reliably screen the capacitance of a bipolar linear IC product.

Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can reduce screening costs for bipolar linear IC products.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the method for manufacturing an MIS capacitor in a semiconductor integrated circuit device (bipolar linear IC) of the present invention,
First, a nitride film is formed on a semiconductor substrate as a capacitor insulating film. Thereafter, a capacitance testing electrode having a detection terminal is formed, and the intrinsic breakdown voltage of the nitride film is applied to this capacitance testing electrode for a short time of about 0.1 seconds for screening. Next, the presence or absence of breakdown of the capacitor insulating film is inspected using the detection terminal. This information is recorded as a defective mark on the surface of the semiconductor substrate or stored in a storage medium, and is used during a later assembly process. Next, the capacitance testing electrode is removed, and a new capacitance electrode as a bipolar linear IC is formed.

Next, the semiconductor substrate is subjected to various treatments, and the semiconductor substrate is divided vertically and horizontally into chips.

Among the chips made into chips, good chips whose capacitor insulating film is not destroyed are assembled into a predetermined package. In this way, a bipolar linear IC with built-in capacitance is manufactured.

[Effect]

According to the above means, in the method of manufacturing a semiconductor integrated circuit device of the present invention, after forming the capacitance insulating film and the capacitance testing electrode, an intrinsic breakdown voltage is applied for a short time to the capacitance testing electrode. After that, the incomplete capacitor insulating film that causes the initial failure is destroyed, and after the incomplete capacitance is detected, the capacitance test electrode is removed and a new capacitor electrode is formed. Capacity that may lead to failure can be screened accurately and reliably.

Furthermore, in the present invention, since screening can be performed in the state of a wafer for manufacturing bipolar linear ICs,
This is well suited for shipping products in the form of wafers.

In addition, in the present invention, since the capacitive insulating film, which is a cause of initial failure, is destroyed by the above screening,
Defective products can be removed in the subsequent wafer inspection process. Therefore, it is possible to omit capacity aging as screening at the finished product stage.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a process diagram showing a method for manufacturing a capacitive part in manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a capacitive part in the same semiconductor integrated circuit device, and FIGS. 9 is a diagram showing a method for manufacturing a capacitor according to the present invention, FIG. 3 is a schematic cross-sectional view of a substrate used for manufacturing a capacitor, FIG. 4 is a cross-sectional view of a substrate provided with a capacitor formation region, and FIG. The figure is a cross-sectional view of a substrate provided with an insulating film for capacitance formation, Figure 6 is a cross-sectional view of a substrate provided with electrodes for capacitance testing, and Figure 7 is a sectional view of a wafer showing capacitance testing by probe needle contact. A schematic plan view, FIG. 8 is a schematic plan view showing a capacitor portion and probe needles in a single chip area arranged on a wafer, and FIG. 9 is a cross-sectional view showing a substrate portion from which capacitance testing electrodes have been removed. FIG. 10 is a perspective view of a semiconductor integrated circuit device manufactured by the method of the present invention, and FIG. 11 is a graph showing the correlation between the strength of screening stress and the defect removal effect.

In manufacturing the capacitor in the semiconductor integrated circuit device of the present invention, that is, a bipolar linear IC, as shown in FIG. It is manufactured through the steps of removing electrodes for capacitance testing and forming electrodes for capacitance. Capacity screening will also be completed at the same time as this manufacturing.

FIG. 2 is a cross-sectional view showing a capacitive part in a bipolar linear IC. A semiconductor layer having a conductivity type opposite to that of the substrate 1, that is, a capacitor forming portion 2, is formed on the main surface of a silicon semiconductor substrate (substrate) 1 having a p conductivity type or an n conductivity type. Further, a thick insulating film 3 made of a 5iOz film is provided around the capacitor forming portion 2, so that the capacitor forming portion 2 is electrically independent. Further, a capacitor insulating film 4 is provided on the capacitor forming portion 2 . This capacitor insulating film 4 is a Si3N4 film (nitride film) with a thickness of 80 nm.
It is formed of. Furthermore, capacitor electrodes 5 and 6 made of aluminum (AJl) are provided on the capacitor insulating film 4 and the capacitor forming portion 2, respectively. In addition,
In the figure, 7 is a buried CVD film made of an insulating film, and 8 is an insulating film. This capacitor is formed of an St and N4 film with a dielectric constant of 7.5 and a thickness of 80 nm, so the capacitance per unit area is 8. 15 X l O-'p F/
It becomes pm. Therefore, the capacitance area per 100 pF is 338 .mu.m, which is approximately half or less of 7 oot Im in the case of a 170 nm thick SiO2 film (dielectric constant 3.9).

Next, how to manufacture such a capacity, in other words,
Describe capacity screening.

In the production of bipolar linear ICs, silicon (S
A thin substrate consisting of t) is prepared. This board is subjected to various processing steps, and at the final stage it is divided vertically and horizontally into chips (IC chips).
As shown in FIG. 10, it is assembled into a rectangular package 21 made of ceramic and plastic to form a semiconductor integrated circuit device (bipolar linear IC) 22. A plurality of glue portions 23 protrude horizontally from the package 21 of the semiconductor integrated circuit device 22 . Further, although not particularly illustrated, each electrode of the chip within the package 21 is electrically connected to the inner end of the lead 23 via a wire. Note that the substrate 1 until it is made into chips is generally referred to as a wafer (semiconductor wafer), and each process is performed on a wafer basis.

FIG. 3 is a diagram showing the manufacturing state of only the capacitive part in manufacturing a bipolar linear IC. In the figure, a semiconductor N25 having a conductivity type opposite to that of the substrate 1 is provided on the main surface of a wafer 20 made of a silicon substrate 1. Also, LOG OS (Local Oxid
In order to form the insulating film 3 by the cation or 5ilicon) method, an insulating film 26 made of a 5izN- film is selectively provided in the capacitance formation region of the wafer 20. Thereafter, by oxidation treatment, as shown in FIG. 4, the semiconductor layer 25 separated from the insulating film 26 is oxidized to form the insulating film 3.

Next, as shown in FIG. 5, a buried CVD film 7 made of StO is selectively formed on the main surface of the wafer 2° by a CVD (vapor phase chemical growth) method. A portion of this buried CVD film 7 partially extends over the capacitor forming portion 2 . Thereafter, a capacitor insulating film 4 is formed on the exposed capacitor forming portion 2 . This capacitor insulation WJ, 4 is 80
It consists of a Si, N, film (nitride film) with a thickness of nm, and its periphery extends to a part of the insulating film 3 and the buried CVD film 7.

Next, as shown in FIG. 6, an insulating film 8 made of a Sin film is selectively formed on the main surface of the wafer 20, and in the contact hole 30, 31 portion where the insulating film 8 is not provided,
Capacity testing electrodes 32 and 33 made of pure Al are provided. One capacitance testing electrode 32 is provided in an overlapping manner so as to contact the capacitance insulating film 4 , and the other capacitance testing electrode 33 is provided in an overlapping manner so as to contact the capacitance forming portion 2 .

This results in the formation of a capacitive structure. Further, the capacitance testing electrodes 32 and 33 have a wiring portion 35, as schematically shown in FIG. This wiring section 35
connects the capacitance test electrodes 32 and 33, or connects the test terminals 36 similarly provided around the chip area 34.
(This terminal may also be used by providing a wire bonding bat at the same time). In addition,
For convenience, this example shows the formation of only the wiring for capacitance testing, but for example, it is also possible to fill only the contact hole portions of other elements (transistors, resistors, etc.) with A-rings. In this case, the capacitance wiring This makes it easier to perform the process, and it also becomes convenient to form the original wiring later.

FIG. 7 shows the arrangement of chip areas 34 on the wafer 20. Further, FIG. 8 describes an example in which two capacitors are arranged in a single chip region 34, and the capacitors other than the capacitors of the bipolar linear IC are omitted.

Next, as shown in FIGS. 8 and 7, a probe needle 40 of a wafer prober is pressed against the test terminal 36 of each chip region 34, and a test (screening) voltage is applied. In this screening, if the capacitor insulating film 4 has even the slightest problem, it must be destroyed to increase the screening accuracy. time is applied. If the intrinsic breakdown voltage continues to be applied to the capacitor insulating film 4, all the capacitor insulating films 4 will break down, so it is necessary to set the voltage (electric field) application time. An example of this study is shown in the graph of FIG. In this example, there is no screening (none), 40V, 6
The following describes screening performed by applying voltages of 0 V and 80 V for 0.1 seconds each, and screening performed by applying voltage of 80 V for 1 second. In addition, the white part of the same bar graph shows the percentage of defects caused by the mask, the hatched part with a straight line rising to the right shows the percentage of defects that could be removed by screening, and the dotted part shows the short lifespan that could not be removed by screening. (0.5S≦Tba<Is) and the probability of market defect is small.
ba<0.5S), which accounts for a high possibility of market defects. As you can see from this graph, 80■
(Electric field strength of 10 MVcm) applied for 1 second will deteriorate the life of the product and require a destructive test.
Approximately 1 second is an appropriate condition.

Screening is performed under these conditions to cause capacity destruction leading to initial failure.

Next, the capacitor insulating film 4 destroyed by the wafer blower is detected. Although not shown, this detection information is displayed as a defective mark in the chip area 34 or stored in a storage medium as a wafer map, so that only good chips are used for assembly when they are made into chips.

Next, as shown in FIG. 9, the capacitance testing electrodes 32 and 33 are removed by etching. In this etching, since the capacitance testing electrodes 32 and 33 are made of pure AJIL, it is only necessary to use an etchant specifically designed for AI, and there is no adverse effect on other elements or capacitance parts. If so, generally Al wiring has St.
However, if a wiring material containing St is used, when the Al wiring is peeled off after screening, St residue etching will adversely affect other elements and the main capacitor (nitride capacitor). Sometimes I let them do it.

Next, AJIL is deposited on the main surface of the wafer 20 again and patterned to form the original capacitor electrode 5.6 as shown in FIG. 2.

After that, the remaining elements other than the capacitors are processed, and then the wafer 20 is cut horizontally into chips. This chip is assembled into a package 21 as shown in FIG. 10, for example, to form a semiconductor integrated circuit device 22.

According to the present invention based on such an embodiment, the following effects can be obtained.

(1) According to the method for manufacturing a capacitor in a bipolar linear IC of the present invention, after forming a capacitor insulating film, a capacitance testing electrode is provided to perform capacitance screening, and then the capacitance testing electrode is removed, and By adopting the method of providing original capacitor electrodes, a desired voltage can be applied to each capacitor for a predetermined period of time, resulting in the effect that capacitance can be accurately and reliably screened.

(2) In the method for manufacturing capacitors in bipolar linear ICs of the present invention, screening can be performed chip-by-chip on the wafer used to manufacture bipolar linear ICs, and the entire capacitance can be screened at the highest breakdown voltage of the process. Effects can be obtained.

(3) According to (2) above, the bipolar linear [
In the capacitor manufacturing method in C, screening is performed by contacting the probe needle with the wafer used to manufacture bipolar linear ICs, so once the initial positioning operation between the wafer and the probe needle is performed, there On the other hand, by relatively pitch-feeding the Ueno chip area, it is possible to screen thousands of bipolar linear ICs arranged on a wafer, which has the effect of reducing screening costs. .

(4) According to the above (2), according to the present invention, since the capacity can be screened in the wafer state, it is possible to obtain the effect that it can be well adapted to the form of a product shipped in the wafer state.

(5) According to the present invention, since the capacitive insulating film, which is a cause of initial failure, is destroyed by screening, defective products can be detected and removed in the subsequent wafer inspection process. Therefore, it is possible to omit capacity aging as screening at the finished product stage.

(6) According to the above (1) to (5), according to the present invention, capacitance screening can be performed at a process common voltage at a processing stage for each wafer, which is called a pre-process, without depending on the power supply voltage. A synergistic effect can be obtained in that a bipolar linear IC with built-in capacitance with high reliability can be provided at low cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, the capacitor insulating film is a single layer, but if it is multilayer,
Further, the same effects as in the above embodiment can be obtained in screening for a capacitor using an oxide film or the like other than a nitride film.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to bipolar linear ICs with built-in MIS capacitors, which is the field of application that formed the background of the invention.
It is not limited to this, but MO3 by oxide film etc.
It can also be applied to screening for O3 capacity equivalence.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the manufacturing of the MIS capacitor in the bipolar linear IC of the present invention, at the wafer stage, only one part of the MTS capacitor is wired to form a capacitance testing electrode, and this capacitance testing electrode is used to conduct a wafer blower tester. After applying a constant voltage to destroy MIS capacitors that may have initial failures, the capacitance testing electrodes are removed to form the original capacitor electrodes, which allows screening of the entire MIS capacitance with high precision. You can definitely do it. Further, according to the present invention, since screening is performed at the wafer stage rather than at the finished product stage, screening costs are also reduced.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a method for manufacturing a capacitive part in manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a capacitive part in a semiconductor integrated circuit device, and FIG. FIG. 4 is a schematic cross-sectional view of a substrate used for capacitor production; FIG. 4 is a cross-sectional view of a substrate provided with a capacitor formation region; FIG. Figure 6 is a cross-sectional view of the substrate on which capacitance testing electrodes are provided, Figure 7 is a schematic plan view of the wafer showing the state of capacitance testing by probe needle contact, and Figure 8 is a single chip arranged on the wafer. FIG. 9 is a schematic plan view showing a capacitance portion and a probe needle in the region, FIG. 9 is a cross-sectional view showing a substrate portion from which capacitance testing electrodes have been removed, and FIG. 10 is a semiconductor integrated circuit device manufactured by the method of the present invention. FIG. 11 is a graph showing the correlation between the strength of screening stress and the defect removal effect. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Capacitance formation part, 3... Insulating film,
4... Insulating film for capacitance, 5.6... Electrode for capacitance, 7.
...Embedded CVD film, 8...Insulating film, 20...Ueno\, 21...Package, 22...Semiconductor integrated circuit bag! (/<Ibora Linear ICL23...Lead, 25...Semiconductor layer, 26...Insulating film, 30.31
...Contact hole, 3233...Capacitance testing electrode,
34... Chimp area, 35... Wiring section, 36...
- Inspection terminal, 40...probe needle.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor integrated circuit device having a capacitance using an insulating film, which includes: forming a capacitive insulating film on a predetermined portion of a substrate; forming a capacitance testing electrode; The method includes the steps of applying a testing voltage to the capacitance testing electrode, detecting whether or not the capacitance is destroyed, removing the capacitance testing electrode, and forming a capacitance electrode. A method for manufacturing a semiconductor integrated circuit device characterized by: 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an intrinsic breakdown voltage of an insulating film is applied to the capacitance testing electrode for a short time of less than 1 second. 3. A plurality of semiconductor integrated circuit devices are formed on one semiconductor substrate, and electrodes for capacitance testing are formed while each semiconductor integrated circuit device is arranged on the one semiconductor substrate;
4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an insulating film test by applying a voltage, removal of a capacitance testing electrode, and formation of a capacitance electrode are performed, respectively.