JPH04130661A - Method of estimating power consumed by semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To estimate the power consumed by a semidoncutor integrated circuit in conformity with the actual operation, and contrive to shorten a turn around time of the semiconductor integrated circuit and reduce consts thereof, by a method wherein the power consumed by a MOS LSI is estimated at an earlier stage of manufacturing it. CONSTITUTION:By line-coupling data 5 of various MOS logic circuits, consumed power data 6 containing average consumed power of various MOS logic circuits operating at a specific cycle and consumed power for each voltage of output signals, various input signal data 7 to be inputted into various MOS logic circuits, and external setting conditions data 8 showing an input voltage to be inputted from a circuit added to the outside of the MOS logic circuit and/or a transition period of time of the input voltage, a timewise change of the output signal voltage of the MOS logic circuit based on the line-coupling data 5 and the input signal data 7 is demanded. Next, by calculating the timewise change of the output signal voltage and the consumed power data, the power consumed by the MOS logic circuit itself at a specific time is calculated. Lastly, the consumed power is calculated at a specific time based on the consumed power data 6 and the external setting conditions data 8.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a power consumption estimation method for determining the power consumption of a semiconductor integrated circuit including a MOS logic circuit. With the aim of providing a method for estimating power consumption that is more consistent with actual operation, we have compiled the wiring data of various MOS logic circuits, the average power consumption of various MOS logic circuits that operate in a specific cycle, and the voltage of each output signal. Power consumption data including power consumption, various input signal data input to various MOS logic circuits, input voltage input from a circuit added outside the MOS logic circuit, and/or external setting indicating the transition period of the input voltage After determining the temporal change in the output signal voltage of the MOS logic circuit based on the connection data and input signal data, the temporal change in the output signal voltage and the power consumption data are calculated to determine the MOS logic circuit. The power consumption of the circuit itself in a predetermined time is calculated, and the power consumption in a predetermined time is calculated based on the power consumption data and external setting condition data.

[Industrial application field]

The present invention relates to a power consumption estimation method for determining power consumption of a semiconductor integrated circuit including a MOS logic circuit.

In recent years, MOS logic circuits have been changed to MO including Bi-CMOS circuits.
As S-type semiconductor integrated circuits (MOSLSI) become more highly integrated and have shorter delivery times, CAD (Computer Aided)
d Design) LSI design is being automated. Regarding the power consumption of MOSLSI, it is important to check the power consumption at an earlier stage, that is, at the design stage such as CAD before manufacturing the LSI.
If we can obtain something that better matches actual operations, it will be possible to shorten delivery times and reduce losses during manufacturing.

[Prior art] Conventionally, MOs including MOS logic circuits and Bi-CMOS circuits
The estimation of the power consumption of SLSI is based on the λ Ibora LSI which includes the Nordic Ibora logic circuit! Compared to this, it is difficult due to its characteristics.

Since a bipolar logic circuit maintains its operating state by constantly flowing current when in a predetermined operating state, power consumption can be easily determined by measuring the current value. However, MO8 logic circuits, especially CMOS
Inno/evening, etc., the output is reversed (switching)
At this time, only instantaneous current flows due to charging and discharging of the capacitor formed at the output terminal. Therefore, the power consumption was measured while visually checking the current value during switch notching using an analog meter.

[Problems to be Solved by the Invention] Therefore, in order to estimate the power consumption of the entire MOSLSI, first, the M
Assuming an OS logic circuit, determine the unit frequency and unit capacity of human output as a reference, calculate the power consumption per unit time using the conventional means described above, calculate the power consumption value of all 3L MOSLSr, and calculate the maximum operating frequency. Approximate power consumption can be determined by taking into account the actual operating rate.

However, in today's MOSLSI, even one type of MOS logic circuit has various different design conditions, and the operating frequency and actual operating rate also vary. In this way, if the power consumption value of the entire MOSLSI is calculated only from various basic MO5 logic circuits and basic operating conditions, only the approximate power consumption value of the entire MOSLSI can be obtained. If the IC requested by the user requires low power consumption, the power consumption estimation method described above will require re-prototyping if the power consumption value of the prototype is outside the standard, reducing the LSI production time. It will take a long time and increase manufacturing costs.

Therefore, it is an object of the present invention to provide a method for estimating the power consumption of a semiconductor integrated circuit that can estimate the power consumption of a MOSLSI at an earlier stage of manufacturing and is more in line with actual operation.

[Means for Solving the Problems] An object of the present invention is to provide connection data of various MOS logic circuits, average power consumption of various MOS logic circuits operating in a specific cycle, and power consumption for each output signal voltage. Power consumption data, various input signal data input to various MOS logic circuits, input voltage input from a circuit added outside the MOS logic circuit, and external setting condition data indicating the transition period of the input voltage. In preparation, after determining the temporal change in the output signal voltage of the MOS logic circuit based on the connection data and input signal data, the temporal change in the output signal voltage and the power consumption data are calculated to determine the predetermined value of the MOS logic circuit itself. This is achieved by calculating the power consumption over time and also calculating the power consumption over a predetermined time based on power consumption data and external setting condition data.

[Effect]

In the present invention, the MOS logic circuit is provided with data indicating wiring relationships, data on various human input signals, average power consumption data in a specific cycle, data on voltage of output signals, and external setting condition data. In other words, there are many types of data that indicate the operating state of the MOS logic circuit, and the power consumption value is calculated from the average power consumption data due to the operation of the MOS logic circuit itself and the external setting condition data based on the external conditions of a specific MO5 logic circuit. Therefore, it is possible to estimate power consumption more closely based on actual operation.

Furthermore, since the operating state of the MOS logic circuit exists as data, it can be used in CAD and logic simulation devices, and power consumption can be estimated at an earlier stage.

〔Example〕

An embodiment embodying the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of an apparatus for carrying out the present invention.

The power consumption estimating device 1 of this embodiment is composed of a CAD device, and includes a data storage section 2, a logic simulator 3, a power consumption calculation section 4, and the like. The data storage section 2 includes various MOSs such as input and output buffers, inverter circuits, and resistors.
Connection data 5 of the logic circuit, power consumption data 6 having functions and data indicating the power consumption of various MOS logic circuits, signal data 7 of input signals input to the MOS logic circuit, and setting conditions outside the MOS logic circuit. external setting condition data 8 and logic simulator execution results 9 that store results from the logic simulator 3.

The power consumption estimation method of this embodiment is based on the connection data 5 of the MOS logic circuit stored in the data storage section 2 and the input signal of the signal data, and the logic simulator 3 calculates input/output signals at a predetermined time. The number of changes in the voltage level of data, etc. is stored in the logic simulator execution result 9, and the power consumption calculation unit 4 calculates the execution result of the logic simulator and the per unit time in the MOS logic circuit stored in the power consumption data 6. The power consumption of the MOS logic circuit is calculated from the average power consumption data of , and the calculation result of the power consumption is also calculated from the power consumption data external setting condition data 8.

Each configuration will be explained below.

Regarding 1'-, the connection data 5 stores data such as the type of MOS logic circuit or buffer, the number of fan-ins, and the wiring capacity.

The signal data 7 stores data corresponding to various signals such as the frequency of the human input signal input to the MOS logic circuit, and the input voltage.

The power consumption data 6 stores data such as average power consumption data during operation and functions of power consumption with respect to input signals for various MOS logic circuits or buffers.

For example, average power consumption data PI for input signals of a specific period of a CMOS inverter, average power consumption data PC for each voltage of output signals of each input and output buffer, power consumption of resistive elements used as pull amplifier circuits and pull-down circuits. Data PR, average power consumption during bus conflict in bus driver circuits and bidirectional buffers PB, C
Average power consumption PP due to steady through current rather than switching operation of MOS inverter and CMOS buffer
etc.

The power consumption data stored in the power consumption data 6 includes, for example, the following.

■ Average power consumption data PI per unit time for a CMOS inverter circuit when the human input signal is a clock with a predetermined frequency that swings between power supply voltages.

The average power consumption data Pi per specific frequency is based on the number of cycles M within a predetermined time TA and the “H” level of the output signal within one cycle.
Instantaneous power P during level period and “H” level output time T
When H, P i=P*TH*M/TA... (1
).

Assuming that the input if signal is the number of cycles within a predetermined time TB when the output time TH is the same but the frequency is different, the average power consumption data PI is P I = P i * (
TA/M)*(N/TB)...(2) is expressed and stored.

(2) Average power consumption data PC for a CMOS inverter circuit used as an input or output buffer when the human input signal does not have periodicity at a predetermined bias voltage without making a full swing between power supply voltages.

The average power consumption PC per unit time is the output voltage “H”
Power consumption at level PH1 Output voltage “H” level sending time within predetermined time TA (THl, TH2, =-, T
Hm) total time TH1 Power consumption PL when the output voltage is "L" level (bias voltage applied state), output voltage "H" level sending time within a predetermined time TA (TLI, TL2.
..., TLm), then it is expressed as 'PC=PH*(ΣTHm/TA)+PL*(ΣTLm/TA)-(3) and is stored.

■ Power consumption data r when the input voltage is input to one end of the resistor for pull amplifier and pull down.

As shown in FIGS. 3(a) and 4(b), in the input buffer with pull-up and pull-down circuits, the voltage VIN applied to the input terminal 10, the power supply voltage VDD, and the ground voltage G
If there is a voltage difference between N and D, currents IPU and IPD flow through resistor r, consuming power. Since the power consumption at this time is a function of the input voltage IN and the resistance value r, this resistance value r is stored as power consumption data.

■ Average power consumption data PB for bus driver circuits and bidirectional buffers when the output voltage is in a state where a bus conflict occurs.

In the bus driver circuit of FIG. 4(a), VDD→bus driver circuit→output terminal 13→
A lotus conflict occurs between the bus driver circuit and GND.
Current IB flows and consumes power. Also, Fig. 4(b)
In the bidirectional buffer, a bus conflict occurs due to the external output voltage state from the output inverter circuit, and a current of 1 B flows externally, consuming power. At this time, the power consumption value per unit time (average power consumption value) PB is stored for each bus driver circuit and bidirectional buffer.

■ Power consumption data PP for a CMOS inverter and CMOS Pamphlet 7 circuit where a through current occurs between VDD and GND.

In a CMOS inverter or CMOS buffer as shown in Fig. 5(a), the input voltage is the P-channel MOS transistor 1.
1. When the voltage exceeds the threshold value of the N-channel MOS transistor 12, the transistor becomes conductive and a through current II flows, consuming power.

Regarding the through current, when viewed as a steady through current rather than a switching operation, this power consumption is as shown in Figure 5 (b).
The input voltage occurs within a predetermined voltage range as shown in FIG.

Therefore, the power consumption is as shown in FIG. 5(C).
The power consumption waveform shown in FIG. 5(b) is obtained using a plurality of straight lines proximal to each other, and at this time, the input voltages Vl, V2, . ..., the slope PI of the straight line with respect to Vn.

P2. ..., Pn-1 are stored as power consumption data PP.

■ Power consumption data when MO5 logic circuit operation changes due to waveform rounding of human signal It is assumed that the falling transition periods TR and TF are constant. However, as shown in FIG. 6(b), when the transition periods TR and TF are longer than the input signal waveform of FIG. 6(a), the operating state of the MOS logic circuit receiving the input signal also changes. , power consumption also changes. Figure 6 (C
), while the operating frequency of the input signal remains constant, the transition period T between the rising and falling edges of the input signal
The slope PTH of the power consumption value when R and TF are changed is stored as power consumption data.

External setting condition data 8 includes the input/output voltage state due to circuits added outside the MOS logic circuit, that is, the input voltage of the pull-up circuit or pull-down circuit added to the input terminal of the large-power buffer, the CMOS inverter, and the CMOS converter. It stores data indicating the transition period state of the input voltage, which has the accent of the rising and falling edges of the human input terminal and the human input signal.

Specifically, the input voltage VIN input to the pull amplifier pull-down circuit included cover sofa shown in FIGS.
Store L. In a CMOS inverter and a CMOS buffer as shown in Fig. 5(a), the input voltage is H°“
Level voltage VIH1 "L" level voltage VIL is stored. As shown in FIG. 6(C), the transition state period Trf in the rising period TR2 and the falling period TF of the input signal is stored.

The logic simulator execution result 9 stores the execution result of the logic simulator 3, which will be described later.

The logic simulator 3, which has two iA Simini Relays 36, reads out the connection data of the MOS logic circuit to be obtained from the connection data 5 of various MOS logic circuits, and also reads the human input signal input to the iBMos logic circuit from the signal data 6. The data is read out, and based on the read connection data and signal data, the corresponding MOS
The logic circuit is operated in a simulated manner for a predetermined period of time, and basic data necessary for calculating the voltage levels of input and output signals, the number of changes in the output signal, etc. is output to the logic simulator execution result 9.

For example, if the connection data is a CMOS inverter circuit used for an internal circuit, and the input signal in signal data 6 is a CM
If it is a clock with a predetermined period that fully swings between the power supply voltages applied to the OS inverter circuit, the CMO
The voltage level of the output signal of the S inverter circuit and the number of changes thereof are output as the execution results. Also, if the connection data is a CMOS inverter circuit used as an input or output buffer, and the input signal in signal data 6 does not have periodicity at a predetermined bias voltage without making a full swing between the power supply voltages, then For example, the voltage levels of the input and output signals,
The temporal change is output as the execution result.

Regarding a4, the power consumption calculation unit 4 calculates the specific time of the MOS logic circuit based on the number of changes in the output signal level Z and the simulation time TT, etc., which are the execution results by the logic simulator 3, and the data from the power consumption data 6. Further, the power consumption calculation unit 4 calculates the power consumption that the MOS logic circuit consumes according to the external setting conditions from the external setting condition data 8 and the power consumption data 6. The power consumption of the entire MO5LSI at a specific time is calculated from the power consumption of the logic circuit.

The principle of calculating the average power consumption performed by the power consumption calculating section 4 will be described below with reference to FIG. Step 3
Steps 1 to 34 calculate the power consumption of each MOS logic circuit, and steps 35 to 36 calculate the power consumption of all MOS logic circuits.

In step 31, power consumption data is input and analyzed.
Allows use in power consumption calculations.

In step 32, connection data, simulation results, average power data in a specific period, etc. are matched for each MOS logic circuit.

In step 33, connection data for each MOS logic circuit is expanded. In step 34, the simulation execution results are input, and the simulation time TT, the number of inversions Z of the output signal, etc. are expanded into the connection data developed in step 33. In step 35, power consumption in the simulation time TT is calculated for the MO5 logic circuit. Further, in a specific MOS logic circuit, power consumption is calculated based on power consumption data and external setting condition data.

The calculation of this power consumption will be specifically explained next.

First, a case will be described in which average power consumption is calculated from the results of the logic simulator 3.

(A) For example, when the power consumption data is as described above, it shows the power consumption PAO limit in the simulation time TT. This power consumption PA is calculated from the simulation time TT and the number of inversions Z of the output signal based on the above-mentioned formula (2): PA=P i * (Z/2)/TT . . .
(4) (The reason why Z/2 is used in the above equation (4) is that the output signal is inverted twice within one period). Therefore, MOSLS regarding this circuit! O3LSI
The overall power consumption is calculated by the sum of the power consumption PA of equation (4) for each MOS logic circuit.

(B) Similarly, the power consumption PD when the power consumption data is the above ■ is calculated based on the formula (3) above, PD = (PH
*ΣTHm +pL*ΣTLm)/TT-(5) Calculated as follows. Therefore, for the entire MOSLSI, the power consumption of this circuit is equal to the power consumption PD of the MOS in equation (5).
Calculated as a summation for each logic circuit.

Next, a case in which power consumption is calculated based on external setting condition data and power consumption data will be described.

(C) For example, the pull-up shown in FIGS. 3(a) and (b).

In the input Hano core with pull-down circuit, the average power consumption per unit time PPU (pull amplifier), PPD (pull-down) is the power consumption between ゛H゛ level TH1 ``L°゛ level TL, power consumption within the specified time TT according to the simulation result. Data r, input voltage VIH of external setting condition data
, VIL, then PPU= ((VDD-VH)/r
) *VDD* (TL/TT)... (6) PPD=
((VL-GND)/r) neVDD* (TI(/TT)... Calculated using (7). Therefore, the power consumption for the entire MO5LSI regarding this circuit is calculated using equations (6) and (7). Each power consumption P
It is calculated by the total number of MOS logic circuits of PU and PPD.

(D) In the bus driver circuits and bidirectional buffer circuits of FIGS. 4(a) and (b), the bus conflict state time within the predetermined time TT according to the simulation results is as shown in FIG. 4(c). (TBCI, TBC2, -, TBCn)
Assuming that the total time TBC1 is the power consumption data PB, the power consumption PBC due to bus conflict is: PBC=PB*TBC/TT... (8)
It is calculated by Therefore, the MOSLSI for this circuit is
The overall power consumption is the power consumption PBC of equation (8)
It is calculated by the total number of MOS logic circuits.

(E) CMOS inverter and CM as shown in Figure 5(a)
In the OS buffer, as shown in FIG. 5(d), during the period during which the through current flows within the simulation time TT, that is, when the input voltage is at the input voltage VA-VB of FIG. 5(b),
Dry period TH1 of "H" level voltage period (THl, TH2, -, THn) "L level voltage period (TLI, TL2..
..., TLn), power consumption data PP, input voltages VIH and VIL of external setting condition data,
Its power consumption PX is: PX=PPk*VH* (TIH/TT)+pp j
*VL* (TI L/TT)... Calculated as follows (9) (PPk is input voltage VI) 1 o'clock, P
Pj corresponds to power consumption data PP at input voltage VrL). Therefore, the power consumption of the entire MOSLSI regarding this circuit is calculated by the sum of the number of MOS logic circuits of power consumption PX in equation (9).

(F) As shown in FIG. 6(a), the operating frequency (f/ TT), power consumption data PTH1 and external setting condition data Trf, the power consumption Prf is P r f = PTH * Tr f * (f/TT)...
・Calculated using (10). Therefore, the MOSLSI for this circuit is
The overall power consumption is the power consumption Pr of equation (1o)
It is calculated by the sum of the number of MOS logic circuits of f.

After step 35, in step 36, the calculation result of the power consumption of each MOS logic circuit or all MOS logic circuits at a specific time is outputted to a printer or the like, and the process ends.

As described above, in this embodiment, for each MOS logic circuit, the simulation execution results during operation at a specific time are obtained from the wiring data and signal data, and the power consumption is calculated from the power consumption data based on the results. Furthermore, power consumption is calculated in a specific MOS logic circuit using external setting condition data. As a result, MOSLS
At the time of design, power consumption can be estimated more closely to actual operation, and since the operating state of the MOS logic circuit exists as data, it can be applied to CAD and logic simulation equipment, and power consumption can be estimated at an earlier stage. can be estimated.

In this embodiment, the power consumption calculation unit 4 and the logic simulator 3 are controlled by software, but they may be configured by hardware.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to estimate the power consumption of MOSLSI at an earlier stage of manufacturing.
It is possible to estimate the power consumption of a semiconductor integrated circuit in accordance with the actual operation, and there is an effect that the delivery time and cost of the semiconductor integrated circuit can be shortened.

[Brief explanation of drawings]

Fig. 1 is a schematic configuration diagram of a device for carrying out the present invention, Fig. 2 is a flowchart of the operation of the power consumption calculation section, Fig. 3 is a circuit diagram of a pull amplifier and an input circuit with a pull-down circuit, and Fig. 4 is a consumption due to lot conflict. FIG. 5 is a diagram for explaining power consumption due to through current of a CMOS inverter circuit. FIG. 6 is a diagram for explaining power consumption due to waveform rounding due to human input signals. In the figure, ■ is a power consumption estimation device, 2 is a data storage unit, 3 is a logic simulator, 4 is a power consumption calculation unit, 5 is connection data, 6 is power consumption data, 7 is signal data, 8
9 is the external setting condition data, 9 is the logic simulator execution result, IO is the input terminal, 11 is the P-channel MOS transistor, 12 is the N-channel MOSI-transistor, 13.3
0 is an output terminal, 14.15 is a transmission gate, r is a resistor, VDD is an electric voltage, and GND is a ground voltage. (α) (b) 3rd Meichen) shi) lv score 7 rict 1sJ Rishi Tei 17 scolding tm Ming 1 soup meme trouble'J! b4121 (Good) (!, MO'S4-8-II!] '-Even 1 stroke tj?
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Claims (1)

[Scope of Claims] Wiring data of various MOS logic circuits; Power consumption data including average power consumption of the various MOS logic circuits operating in specific cycles and power consumption for each output signal voltage; various input signal data input to the MOS logic circuit; and external setting condition data indicating an input voltage input from a circuit added outside the MOS logic circuit and/or a transition period of the input voltage; the M based on the input signal data;
After determining the temporal change in the output signal voltage of the OS logic circuit,
The temporal change in the output signal voltage and the power consumption data are calculated to calculate the power consumption of the MOS logic circuit itself at a predetermined time, and the power consumption at a predetermined time is calculated based on the power consumption data and the external setting condition data. A method for estimating power consumption of a semiconductor integrated circuit, characterized by calculating power consumption.