JP2003308357A - Logic circuit simulation method, logic circuit simulation program, and logic circuit simulation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the simulation of a circuit operation based on a precise delay time to fluctuation of power source voltage. <P>SOLUTION: A fluctuating power source voltage calculation part 101 calculates power source voltages VDD and VSS supplied to each cell of a logic circuit to be simulated. A power source voltage difference calculation part 202 determines, with respect to each cell, reference delay time Tdl0 and reference transition time Ttr0 until output voltage becomes equal to the threshold of input voltage from the time when the input voltage reaches the threshold or from the build up of output voltage. A threshold voltage calculation part 102 determines the threshold voltage Vth of each cell, and determines delay time Tdl until the output voltage reaches the threshold voltage Vthn of the next stage based on each above-mentioned value. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an ASIC (Applic
ration specific integrated circuit) and a semi-custom LSI (Large Scale Integration).

[0002]

2. Description of the Related Art In recent years, in the manufacture of semiconductor integrated circuits, technology for miniaturizing elements such as transistors and wiring has been rapidly advancing. As the number of transistors increases and the operating frequency increases due to such miniaturization, not only the current consumption increases, but also the fluctuation of the current flowing through the power supply wiring becomes large, and each circuit (element) The fluctuation of the power supply voltage applied to the power supply tends to be large.

The fluctuations in the power supply voltage cause fluctuations in signal propagation time between circuits, that is, delay times. Therefore, in order to prevent the malfunction of the circuit due to the fluctuation of the power supply voltage, a method of simulating the logic circuit in consideration of the delay time fluctuation due to the fluctuation of the power supply voltage is an important technique.

As a simulation technique in consideration of the fluctuation of the power source voltage as described above, for example, Japanese Patent Laid-Open No. 2000-1
A technique disclosed in Japanese Patent No. 94732 is known. In this technique, delay information corresponding to a plurality of power supply voltages is created in advance as a library, and the above-mentioned delay information corresponding to the power supply voltage applied to each circuit element is selected and used to change the power supply voltage. The delay simulation with high accuracy is performed. More specifically, as shown in FIG. 6, for example, a delay from the output of the driving element in the preceding stage reaching the threshold voltage of the driven element until the output of the driven element reaches the same voltage as the threshold voltage. Time is the power supply voltage difference (VDD-VS
S), the delay time corresponding to various power supply voltage differences is held and selected to estimate the delay variation due to the influence of the power supply voltage variation caused by the power supply wiring resistance inside the LSI. Is possible.

[0005]

However, the above-mentioned conventional simulation method has a problem that an accurate delay time cannot always be obtained.

That is, in the conventional method, the time from when the output of the driving element in the preceding stage reaches the threshold voltage of the driven element to when the output of the driven element reaches the same voltage as the threshold voltage as described above. Is calculated as the delay time, and this is when the threshold voltage of the element driven by the driven element is also equal to the threshold voltage of the driven element, that is, when the threshold voltages of all the elements are equal. If so, the delay time is required.

However, in practice, when the power supply voltage applied to each circuit element fluctuates, normally both the high-voltage side power supply voltage VDD and the low-voltage side power supply voltage VSS as shown in FIG. Element 902 and element 903 due to fluctuations
And the threshold voltage is different. That is, the element 90
In No. 2, the internal state starts to transition when the voltage input from the element 901 reaches the threshold voltage of the element 902, whereas in element 903, the voltage input from the element 902 reaches the threshold voltage of the element 903. After that, the internal state begins to transition, and the time difference between the two becomes the true delay time. therefore,
In the conventional method for obtaining the delay time, an error will occur.

In view of the above problems, it is an object of the present invention to enable more accurate simulation of circuit operation based on delay time with respect to fluctuations in power supply voltage.

[0009]

In order to solve the above-mentioned problems, the solution means taken by the invention of claim 1 is a logic circuit simulation method for simulating the operation of a logic circuit including a plurality of circuit elements. A threshold voltage calculating step of obtaining a threshold voltage of an input signal in a second circuit element driven by a first circuit element of the plurality of circuit elements, and the first circuit element based on the threshold voltage. And a delay time calculating step for obtaining the delay time of the output signal in.

According to the first aspect of the present invention, even when the threshold voltage varies due to the variation of the power supply voltage, the accurate delay time according to the variation of the threshold voltage can be obtained.

According to a second aspect of the present invention, there is provided the logic circuit simulation method according to the first aspect, further comprising the second aspect.
A power supply voltage calculation step for obtaining a first power supply voltage and a second power supply voltage to be supplied to the circuit element, and the threshold voltage calculation step is performed by using the first power supply voltage and the second power supply voltage. The threshold voltage is obtained based on

According to a third aspect of the present invention, in the logic circuit simulation method according to the second aspect, the threshold voltage calculating step calculates the average value of the first power supply voltage and the second power supply voltage. It is characterized in that it is obtained as a threshold voltage.

According to the invention of claim 2 or 3,
The threshold voltage can be easily obtained.

According to a fourth aspect of the present invention, in the logic circuit simulation method according to the second aspect, the threshold voltage calculating step includes the first power supply voltage and the second power supply voltage, and the threshold voltage. It is characterized in that the threshold voltage is obtained based on the data indicating the relationship.

According to the fourth aspect of the present invention, it is possible to obtain a more accurate threshold voltage and further improve the accuracy of the delay time.

According to a fifth aspect of the present invention, in the logic circuit simulation method according to the first aspect, the delay time calculating step outputs after the input voltage in the first circuit element reaches a predetermined input voltage. Reference delay time until the voltage reaches a predetermined output voltage, the difference between the predetermined output voltage of the first circuit element and the threshold voltage of the second circuit element, and the output of the first circuit element The delay time is obtained based on the relationship between the output voltage change amount and the change time when the voltage changes.

The invention of claim 6 is the logic circuit simulation method of claim 5, wherein the predetermined output voltage of the first circuit element is a threshold voltage of an input signal in the first circuit element. The voltage is equal to.

According to a seventh aspect of the present invention, there is provided the logic circuit simulation method according to the fifth aspect, further comprising the first aspect.
A voltage difference calculation step for obtaining a voltage difference between the third power supply voltage and the fourth power supply voltage supplied to the circuit element, the delay time calculation step based on the voltage difference. It is characterized in that the reference delay time in the circuit element is obtained.

According to the inventions of claims 5 to 7, it is possible to easily obtain an accurate delay time based on the reference delay time which is relatively easily obtained.

The invention according to claim 8 is a logic circuit simulation program for simulating the operation of a logic circuit including a plurality of circuit elements, wherein the logic circuit simulation program is driven by a first circuit element of the plurality of circuit elements. The computer executes a threshold voltage calculation step of obtaining a threshold voltage of the input signal in the second circuit element, and a delay time calculation step of obtaining a delay time of the output signal in the first circuit element based on the threshold voltage. It is characterized by

According to a tenth aspect of the present invention, there is provided a logic circuit simulation device for simulating the operation of a logic circuit including a plurality of circuit elements, which is driven by a first circuit element of the plurality of circuit elements. Threshold voltage calculating means for calculating the threshold voltage of the input signal in the second circuit element, and delay time calculating means for calculating the delay time of the output signal in the first circuit element based on the threshold voltage. Is characterized by.

According to the eighth or tenth aspect of the present invention, even when the threshold voltage fluctuates due to the fluctuation of the power supply voltage, an accurate delay time corresponding to the fluctuation of the threshold voltage can be obtained.

According to a ninth aspect of the present invention, in the logic circuit simulation program according to the eighth aspect, the delay time calculating step outputs after the input voltage in the first circuit element reaches a predetermined input voltage. Reference delay time until the voltage reaches a predetermined output voltage, the difference between the predetermined output voltage of the first circuit element and the threshold voltage of the second circuit element, and the output of the first circuit element The delay time is obtained based on the relationship between the output voltage change amount and the change time when the voltage changes.

The invention according to claim 11 is the logic circuit simulation apparatus according to claim 10, wherein the delay time calculation means outputs the delay time after the input voltage in the first circuit element reaches a predetermined input voltage. Reference delay time until the voltage reaches a predetermined output voltage, the difference between the predetermined output voltage of the first circuit element and the threshold voltage of the second circuit element, and the output of the first circuit element The delay time is obtained based on the relationship between the output voltage change amount and the change time when the voltage changes.

According to the ninth or eleventh aspect of the present invention, the accurate delay time can be easily obtained based on the reference delay time that is relatively easily obtained.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A logic circuit simulation apparatus according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the functional configuration of the logic circuit simulation apparatus. In the figure, solid arrows indicate the flow of processing, and broken arrows indicate the flow of data.

The variable power supply voltage calculation unit 101 (power supply voltage calculation means) is a circuit element of a logic circuit that simulates an operation based on the data stored in the layout graphic data storage unit 121 and the power library storage unit 122. The power supply voltage supplied to the cell (power supply voltage VDD on the high voltage side and power supply voltage VSS on the low voltage side) is calculated and stored in the variable power supply voltage storage unit 123. The layout graphic data storage unit 121 stores data indicating types of cells included in the logic circuit, connection relationships, and the like. In addition, the power library storage unit 122
Stores data for calculating the current consumption of each cell. More specifically, for example, the current consumption defined as a function of the transition time of the input signal and the load capacitance of the output signal is stored for each cell type and the combination of the input signals.

The threshold voltage calculation unit 102 (threshold voltage calculation means) calculates the threshold voltage (Vt) of each cell based on the power supply voltage calculated by the variable power supply voltage calculation unit 101.
h), that is, the input voltage at which the internal state of the cell starts to change in accordance with the change in the input voltage is calculated, and the threshold voltage storage unit 12 is calculated.
It is designed to be stored in 4.

The delay / transition time calculation unit 103 (delay time calculation means, voltage difference calculation means) is stored in the variable power supply voltage storage unit 123, the threshold voltage storage unit 124, and the delay / transition time library storage unit 125. Based on the data, first, each cell included in the logic circuit (for example, FIG.
Cell 131), the reference transition time (Ttr
0) and the reference delay time (Tdl0), the delay time (Tdl) considering the threshold voltage (Vthn) of the cell 132 in the next stage is calculated, and the reference transition time (Ttr0).
Along with this, the delay / transition time storage unit 126 is configured to store the data.

Here, the reference transition time (Ttr0)
Is a threshold voltage (V) of the cell 131 after the output voltage of the cell 131 starts to rise from the power supply voltage (VSS) (or starts to fall from the power supply voltage (VDD)).
th), the delay / transition time library storage unit 125 stores, for example, various power supply voltage differences (Vd).
The reference transition time (Ttr0) for each cell type and each combination of input signal and output signal is stored in association with if = VDD−VSS).

The reference delay time (Tdl0) is
The time from when the voltage of the input signal of the cell 131 reaches the threshold voltage (Vth) to when the voltage of the output signal reaches the same threshold voltage (Vth), for example, the reference transition time (Ttr).
0), the power supply voltage difference (Vdif), and the load capacitance of the output signal. The delay / transition time library storage unit 125 stores the above information for each cell type and each combination of the input signal and the output signal. Data indicating a function is stored.

Further, the timing verification unit 104 has the reference transition time (Ttr0) and the delay time (Tdl) obtained by the delay / transition time calculation unit 103, the data stored in the layout graphic data storage unit 121, and the necessary data. Accordingly, the operation of the logic circuit is simulated based on the data indicating the signal input from the outside, and the timing of each part is verified.

The logic circuit simulation apparatus as described above is specifically realized by, for example, a program that causes a computer to have the functions of the above units.

Next, the operation of the logic circuit simulation device configured as described above will be described.

First, the variable power supply voltage calculation unit 101 calculates the power supply voltage (VDD, VSS) supplied to each cell of the logic circuit for simulating the operation, and stores it in the variable power supply voltage storage unit 123 (power supply voltage calculation). Step). More specifically, the voltage drop (variation amount) due to the current flowing from the power supply to each cell is calculated based on the data stored in the layout graphic data storage unit 121 and the power library storage unit 122, so that each cell is supplied with the voltage. Power supply voltage (after fluctuation) is calculated, and the fluctuation power supply voltage storage unit 1
23.

The threshold voltage calculation unit 102 calculates the threshold voltage (V) of each cell based on the power supply voltage (VDD, VSS).
th) is calculated and stored in the threshold voltage storage unit 124.
Specifically, for example, the threshold voltage Vth = (VDD + VS
S) / 2 is calculated (threshold voltage calculation step).

The delay / transition time calculation unit 103, based on the data stored in the variable power supply voltage storage unit 123, the threshold voltage storage unit 124, and the delay / transition time library storage unit 125, the delay time of each cell ( Tdl) is calculated and stored in the delay / transition time storage unit 126. Specifically, for example, the following calculation is performed for each cell (for example, for the cell 131 in FIG. 2) (delay time calculation step, voltage difference calculation step).

(1) First, the variable power supply voltage storage unit 123
Based on the power supply voltage (VDD, VSS) stored in
The power supply voltage difference (Vdif = VDD-VSS) is calculated.

(2) From the delay / transition time library storage unit 125, the cell type and the power supply voltage difference (Vdif)
The reference transition time (Ttr0) corresponding to and is read.

(3) By the function stored in the delay / transition time library storage unit 125 corresponding to the cell type,
The reference transition time (Ttr0) and the power supply voltage difference (Vdi
f) and the load capacitance of the output signal (the load capacitance of the circuit connected to the cell, which is indicated by the stored contents of the layout graphic data storage unit 121, more specifically, the wiring capacitance and the input terminal capacitance). , Reference delay time (Tdl0)
Is required. The reference transition time (Ttr0) and the reference delay time (Tdl0) are the same as those obtained by the conventional logic circuit simulation device.
For example, it may be obtained using the method described in Japanese Patent Laid-Open No. 2000-194732.

(4) Based on the respective values obtained as described above and the threshold voltage (Vthn) similarly obtained for the cell 132 at the next stage shown in FIG.
The delay time (Tdl) of 1 is obtained as follows.

Tdl = Tdl0 + (Vthn-Vth)
× Ttr0 / (Vdif / 2) The reference transition time (Ttr0) and the delay time (Tdl) obtained for each cell in the above (2) and (4) are stored in the delay / transition time storage unit 126.

Then, by using the reference transition time (Ttr0) and delay time (Tdl), the timing verification unit 1
The operation of the logic circuit is simulated by 04, and the timing of each part is verified. Specifically, for example, FIG.
Power supply voltage (VDD1 to VDD3, VSS1
~ Vss3) are supplied to the AND circuits 141 and 142 and the flip-flop 143, the respective ANs are simulated when the operation is simulated and verified.
The input signal to the D circuits 141 and 142 is a threshold voltage (Vth
If the delay time Tdl1 · Tdl2 from when the output signal reaches the threshold voltage (Vth3) of the flip-flop 143 after the output signal reaches the threshold voltage (Vth2) of the flip-flop 143 is accurately obtained as described above,
The output signals of the D circuits 141 and 142 are flip-flops 1.
By determining the timing to reach the threshold voltage (Vth3) of 43, it is surely verified whether the timing difference satisfies the setup constraint or the hold constraint of the flip-flop 143.

(Second Embodiment) A logic circuit simulation apparatus according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram showing the functional structure of the logic circuit simulation apparatus. In the figure, solid arrows indicate the flow of processing, and broken arrows indicate the flow of data.

The variable power supply voltage calculation unit 101 (power supply voltage calculation means) is a circuit element of a logic circuit that simulates an operation based on the data stored in the layout graphic data storage unit 121 and the power library storage unit 122. The power supply voltage supplied to the cell (power supply voltage VDD on the high voltage side and power supply voltage VSS on the low voltage side) is calculated and stored in the variable power supply voltage storage unit 123. The layout graphic data storage unit 121 stores data indicating types of cells included in the logic circuit, connection relationships, and the like. In addition, the power library storage unit 122
Stores data for calculating the current consumption of each cell. More specifically, for example, the current consumption defined as a function of the transition time of the input signal and the load capacitance of the output signal is stored for each cell type and the combination of the input signals.

The power supply voltage difference calculation unit 201 (voltage difference calculation means) supplies the power supply voltage difference (Vdif = VDD-VSS) to each cell based on the power supply voltage calculated by the variable power supply voltage calculation unit 101. Is calculated and stored in the power supply voltage difference storage unit 221.

The reference delay / transition time calculation unit 202 (delay time calculation means) is included in the logic circuit based on the data stored in the power supply voltage difference storage unit 221 and the delay / transition time library storage unit 125. For each cell (eg, cell 131 shown in FIG. 2), the reference transition time (Ttr
0) and the reference delay time (Tdl0) are obtained and stored in the reference delay / transition time storage unit 222.

Here, the reference transition time (Ttr0)
Is a threshold voltage (V) of the cell 131 after the output voltage of the cell 131 starts to rise from the power supply voltage (VSS) (or starts to fall from the power supply voltage (VDD)).
th), the delay / transition time library storage unit 125 stores, for example, various power supply voltage differences (Vd).
The reference transition time (Ttr0) for each cell type and each combination of input signal and output signal is stored in association with if = VDD−VSS).

The reference delay time (Tdl0) is
The time from when the voltage of the input signal of the cell 131 reaches the threshold voltage (Vth) to when the voltage of the output signal reaches the same threshold voltage (Vth), for example, the reference transition time (Ttr).
0), the power supply voltage difference (Vdif), and the load capacitance of the output signal. The delay / transition time library storage unit 125 stores the above information for each cell type and each combination of the input signal and the output signal. Data indicating a function is stored.

The threshold voltage calculation unit 102 (threshold voltage calculation unit) calculates the threshold voltage (Vt) of each cell based on the power supply voltage obtained by the variable power supply voltage calculation unit 101.
h), that is, the input voltage at which the internal state of the cell starts to change according to the change of the input voltage is calculated, and the threshold voltage storage unit 12
It is designed to be stored in 4.

Further, the delay / transition time correction unit 203 uses the data stored in the power supply voltage difference storage unit 221, the threshold voltage storage unit 124, and the reference delay / transition time storage unit 222 as the cell of the next stage. 132 threshold voltage (Vth
n), the delay time (Tdl) is calculated, and the delay / transition time storage unit 126 is added together with the reference transition time (Ttr0).
It is designed to be stored in.

Further, the timing verification unit 104 has the reference transition time (Ttr0) and the delay time (Tdl) obtained by the delay / transition time correction unit 203, the data stored in the layout graphic data storage unit 121, and the necessary data. Accordingly, the operation of the logic circuit is simulated based on the data indicating the signal input from the outside, and the timing of each part is verified.

Next, the operation of the logic circuit simulation device configured as described above will be described.

First, the variable power supply voltage calculation unit 101 calculates the power supply voltage (VDD, VSS) supplied to each cell of the logic circuit that simulates the operation, and stores it in the variable power supply voltage storage unit 123 (power supply voltage calculation). Step). More specifically, the voltage drop (variation amount) due to the current flowing from the power supply to each cell is calculated based on the data stored in the layout graphic data storage unit 121 and the power library storage unit 122, so that each cell is supplied with the voltage. Power supply voltage (after fluctuation) is calculated, and the fluctuation power supply voltage storage unit 1
23.

The power supply voltage difference calculation unit 201 uses the power supply voltages (VDD, VSS) stored in the variable power supply voltage storage unit 123.
Based on the power supply voltage difference (Vdif = VDD-VSS)
Is calculated and stored in the power supply voltage difference storage unit 221 (voltage difference calculation step).

The reference delay / transition time calculation unit 202 reads the power supply voltage difference (Vdif) from the power supply voltage difference storage unit 221, and further, the delay / transition time library storage unit 125.
From, the reference transition time (Ttr0) corresponding to the cell type and the power supply voltage difference (Vdif) is read. In addition, the delay / transition time library storage unit 1 corresponds to the type of cell.
25, the reference transition time (Tt
r0), the power supply voltage difference (Vdif), the load capacitance of the output signal (the load capacitance of the circuit connected to the cell, which is indicated by the storage content of the layout graphic data storage unit 121, more specifically, the wiring capacitance). The reference delay time (Tdl0) is calculated based on the input terminal capacitance). The reference transition time (Ttr0) and the reference delay time (Tdl0) obtained as described above are stored in the reference delay / transition time storage unit 222.
Memorized in. The reference transition time (Ttr0) and the reference delay time (Tdl0) are the same as those obtained by the conventional logic circuit simulation device.
For example, it may be obtained using the method described in Japanese Patent Laid-Open No. 2000-194732.

The threshold voltage calculation unit 102 calculates the threshold voltage (V) of each cell based on the power supply voltage (VDD, VSS).
th) is calculated and stored in the threshold voltage storage unit 124.
Specifically, for example, the threshold voltage Vth = (VDD + VS
S) / 2 is calculated (threshold voltage calculation step).

The delay / transition time correction unit 203 delays each cell based on the data stored in the power supply voltage difference storage unit 221, the threshold voltage storage unit 124, and the reference delay / transition time storage unit 222. Calculate the time (Tdl),
It is stored in the delay / transition time storage unit 126 together with the reference transition time (Ttr0) (delay time calculation step). Specifically, for example, the reference transition time (Ttr0) and the reference delay time (Tdl) obtained for the cell 131 of FIG.
0), threshold voltage (Vth), power supply voltage difference (Vdif),
And the delay time (Tdl) of the cell 131 is calculated as follows based on the threshold voltage (Vthn) similarly calculated for the cell 132 of the next stage.

Tdl = Tdl0 + (Vthn-Vth)
× Ttr0 / (Vdif / 2) The reference transition time (Ttr0) and the delay time (Tdl) obtained for each cell as described above are stored in the delay / transition time storage unit 126.

Then, the timing verification unit 1 uses the reference transition time (Ttr0) and the delay time (Tdl).
The operation of the logic circuit is simulated by 04, and the timing of each part is verified. Specifically, for example, FIG.
Power supply voltage (VDD1 to VDD3, VSS1
~ Vss3) are supplied to the AND circuits 141 and 142 and the flip-flop 143, the respective ANs are simulated when the operation is simulated and verified.
The input signal to the D circuits 141 and 142 is a threshold voltage (Vth
If the delay time Tdl1 · Tdl2 from when the output signal reaches the threshold voltage (Vth3) of the flip-flop 143 after the output signal reaches the threshold voltage (Vth2) of the flip-flop 143 is accurately obtained as described above,
The output signals of the D circuits 141 and 142 are flip-flops 1.
By determining the timing at which the threshold voltage (Vth3) of 43 is reached, it is surely verified whether the timing difference satisfies the setup constraint or the hold constraint of the flip-flop 143.

In the above example, after the reference delay / transition time calculation unit 202 obtains the reference delay time and the like,
Although the example in which the threshold voltage calculation unit 102 calculates the threshold voltage has been shown, the order may be reversed, or the threshold voltages may be calculated in parallel.

(Third Embodiment) A logic circuit simulation apparatus according to a third embodiment of the present invention will be described with reference to the drawings.

In the third embodiment, constituent elements having the same functions as those in the first embodiment and the like are designated by the same reference numerals and the description thereof will be omitted.

The logic circuit simulation apparatus according to the third embodiment is different from the apparatus according to the first embodiment in that it includes a threshold value fluctuation library creating section 301 and a threshold value fluctuation library storage section 302, and a threshold voltage calculation. The difference is that a threshold voltage calculation unit 303 is provided instead of the unit 102.

The threshold fluctuation library creating section 301
The threshold voltage according to various power supply voltages (VDD, VSS) supplied to each cell of the logic circuit for simulating the operation is obtained in advance, and the threshold voltage is stored in the threshold variation library storage unit 302 in association with the power supply voltage. ing. That is, the threshold voltage is approximately (VDD +
It is calculated as VSS / 2, but CMOS (Compleme
Strictly speaking, in the case of an LSI or the like configured by an ntary metal-oxide semiconductor) circuit, the ratio of the driving capabilities of the P-type transistor and the N-type transistor fluctuates according to the fluctuation of the power supply voltage, and the threshold voltage fluctuates. Therefore, the threshold voltage is stored in association with the power supply voltage as described above,
By the threshold voltage calculation unit 303, the variable power supply voltage calculation unit 1
By reading the threshold voltage corresponding to the power supply voltage obtained in 01, a more accurate delay time can be obtained. The threshold voltage according to the power supply voltage as described above is
It is not always necessary to obtain the result each time the simulation is performed, and the one that is obtained once and stored in the threshold value variation library storage unit 302 may be used.

The structure for obtaining the threshold value as described above may be applied to the logic circuit simulation apparatus of the second embodiment.

In each of the above-described embodiments, when the reference delay time (Tdl0) is obtained, the reference transition time (Ttr0) and the power supply are calculated using the function stored in the delay / transition time library storage unit 125. Voltage difference (Vdif),
Although an example was found based on the output signal load capacitance,
The present invention is not limited to this, and various methods may be used, such as using a coefficient indicating a delay time change with respect to a change in power supply voltage or using a table holding sampled values.

Further, the method for obtaining the delay time (Tdl) and the reference transition time (Ttr0) is not limited to the above, and for example, the time until the output voltage reaches from VSS to VDD (or VDD to VSS) is used as the reference transition time. Even if it is used, it is easy to obtain the same delay time. Furthermore, the relationship between the output voltage change amount and the change time when the output voltage changes, such as the voltage change amount per reference transition time (Ttr0), may be used, and substantially the same value is obtained. Various modifications are possible.

[0071]

As described above, according to the present invention, even when the threshold voltage fluctuates due to the fluctuation of the power supply voltage, the delay time corresponding to the fluctuation of the threshold voltage, that is, after the input voltage reaches the threshold, the output Since the delay time until the voltage reaches the threshold voltage of the cell of the next stage is obtained, it is possible to simulate the circuit operation based on the accurate delay time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a functional configuration of a logic circuit simulation device according to a first embodiment.

FIG. 2 is an explanatory diagram showing an operation of the logic circuit simulation device of the same.

FIG. 3 is an explanatory diagram showing an example of simulation of circuit operation.

FIG. 4 is a block diagram showing a functional configuration of a logic circuit simulation device according to a second embodiment.

FIG. 5 is a block diagram showing a functional configuration of a logic circuit simulation device according to a third embodiment.

FIG. 6 is an explanatory diagram showing a relationship between a power supply voltage difference and a delay time.

FIG. 7 is an explanatory diagram showing a delay time and an error obtained by a conventional device.

[Explanation of symbols]

101 Fluctuating power supply voltage calculation unit 102 threshold voltage calculation unit 103 Delay / transition time calculator 104 Timing verification unit 121 Layout graphic data storage unit 122 Power Library Storage Unit 123 Fluctuating power supply voltage storage unit 124 threshold voltage storage unit 125 Delay / transition time library storage 126 Delay / transition time storage unit 131 cells 132 cells 141 ・ 142 AND circuit 143 flip flops 201 Power supply voltage difference calculator 202 Reference delay / transition time calculator 203 Delay / transition time correction unit 221 Power supply voltage difference storage unit 222 Reference delay / transition time storage unit 301 Threshold fluctuation library creation unit 302 threshold fluctuation library storage unit 303 Threshold voltage calculator

Claims (11)

[Claims] 1. A logic circuit simulation method for simulating an operation of a logic circuit including a plurality of circuit elements, wherein an input in a second circuit element driven by a first circuit element of the plurality of circuit elements. A logic circuit simulation method comprising: a threshold voltage calculation step of obtaining a threshold voltage of a signal; and a delay time calculation step of obtaining a delay time of an output signal in the first circuit element based on the threshold voltage. . 2. The logic circuit simulation method according to claim 1, further comprising a power supply voltage calculating step for obtaining a first power supply voltage and a second power supply voltage supplied to the second circuit element. The logic circuit simulation method, wherein the threshold voltage calculation step calculates the threshold voltage based on the first power supply voltage and the second power supply voltage. 3. The logic circuit simulation method according to claim 2, wherein in the threshold voltage calculating step, an average value of the first power supply voltage and the second power supply voltage is obtained as the threshold voltage. And a logic circuit simulation method. 4. The logic circuit simulation method according to claim 2, wherein the threshold voltage calculation step is based on data indicating a relationship between the first power supply voltage and the second power supply voltage and the threshold voltage. Then, the logic circuit simulation method is characterized in that the threshold voltage is obtained. 5. The logic circuit simulation method according to claim 1, wherein in the delay time calculating step, the output voltage becomes a predetermined output voltage after the input voltage in the first circuit element becomes a predetermined input voltage. And the difference between the predetermined output voltage of the first circuit element and the threshold voltage of the second circuit element, and the output when the output voltage of the first circuit element changes. A method of simulating a logic circuit, characterized in that the delay time is obtained based on the relationship between the voltage change amount and the change time. 6. The logic circuit simulation method according to claim 5, wherein the predetermined output voltage of the first circuit element is the first circuit element.
A logic circuit simulation method characterized in that the voltage is equal to a threshold voltage of an input signal in the circuit element. 7. The logic circuit simulation method according to claim 5, further comprising a voltage difference calculation step for obtaining a voltage difference between the third power supply voltage and the fourth power supply voltage supplied to the first circuit element. And the delay time calculation step is based on the voltage difference,
A method for simulating a logic circuit, characterized in that the reference delay time in the first circuit element is obtained. 8. A logic circuit simulation program for simulating the operation of a logic circuit including a plurality of circuit elements, the input in a second circuit element driven by a first circuit element of the plurality of circuit elements. A threshold voltage calculating step of calculating a threshold voltage of a signal; and a delay time calculating step of calculating a delay time of the output signal in the first circuit element based on the threshold voltage. Circuit simulation program. 9. The logic circuit simulation program according to claim 8, wherein in the delay time calculating step, the output voltage becomes a predetermined output voltage after the input voltage in the first circuit element becomes a predetermined input voltage. And the difference between the predetermined output voltage of the first circuit element and the threshold voltage of the second circuit element, and the output when the output voltage of the first circuit element changes. A logic circuit simulation program, wherein the delay time is obtained based on the relationship between the voltage change amount and the change time. 10. A logic circuit simulation device for simulating the operation of a logic circuit including a plurality of circuit elements, wherein an input in a second circuit element driven by a first circuit element of the plurality of circuit elements. A logic circuit simulation, comprising: a threshold voltage calculation unit that obtains a threshold voltage of a signal; and a delay time calculation unit that obtains a delay time of the output signal in the first circuit element based on the threshold voltage. apparatus. 11. The logic circuit simulation device according to claim 10, wherein the delay time calculating means sets the output voltage to a predetermined output voltage after the input voltage of the first circuit element becomes a predetermined input voltage. And the difference between the predetermined output voltage of the first circuit element and the threshold voltage of the second circuit element, and the output when the output voltage of the first circuit element changes. A logic circuit simulation device, wherein the delay time is obtained based on a relationship between a voltage change amount and a change time.