JPH04130626A - Semiconductor element manufacturing equipment - Google Patents

Semiconductor element manufacturing equipment

Info

Publication number
JPH04130626A
JPH04130626A JP25252390A JP25252390A JPH04130626A JP H04130626 A JPH04130626 A JP H04130626A JP 25252390 A JP25252390 A JP 25252390A JP 25252390 A JP25252390 A JP 25252390A JP H04130626 A JPH04130626 A JP H04130626A
Authority
JP
Japan
Prior art keywords
wafer
potential
substrate
semiconductor device
front surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25252390A
Other languages
Japanese (ja)
Inventor
Hideo Kurihara
栗原 英男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25252390A priority Critical patent/JPH04130626A/en
Publication of JPH04130626A publication Critical patent/JPH04130626A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To alleviate a field which is generated on a substrate for a semiconductor element for preventing an insulated film from being damaged by the field by controlling the potential by a potential control device so that the front surface and rear surface of the semiconductor which is brought into contact with a conductor may be at the same potential. CONSTITUTION:When the ion beam is cast on a wafer 1 which is secured by a clamper 3 on a wafer support rest 2 which is placed on a turn table 5, the potential at the front surface of the wafer 1 rises in a moment and there appears a difference in potential between the front surface and rear surface of the wafer 1 because the support rest 2 is connected directly to the earth potential through the turn table. However, since the support rest 2 is connected to the earth potential through a resistance 4, the rear surface of the wafer 1 immediately gets electrified like the front surface and thus a difference in potential between the front and rear surfaces of the wafer 1 is reduced. Consequently, a field which is generated on the wafer 1 can be alleviated and an insulated film is prevented from being damaged.

Description

【発明の詳細な説明】 [概要〕 半導体素子製造装置に関し、 半導体素子の基板上に発生する電界を緩和し、絶縁膜の
損傷を防止する半導体素子製造装置を提供することを目
的とし、 半導体素子の基板を支持する基板支持手段によって支持
される半導体素子の基板に荷電粒子を照射する半導体素
子製造装置において、前記基板支持手段は少なくとも前
記基板に接する部分を導体で形成し、前記基板の表面、
および裏面の電位が同電位となるように該導体の電位を
制御する電位制御手段を設けるように構成する。
[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a semiconductor device manufacturing device that alleviates an electric field generated on a substrate of a semiconductor device and prevents damage to an insulating film. In a semiconductor device manufacturing apparatus that irradiates charged particles onto a substrate of a semiconductor element supported by a substrate supporting means that supports a substrate, the substrate supporting means has at least a portion in contact with the substrate formed of a conductor, and the surface of the substrate,
A potential control means is provided for controlling the potential of the conductor so that the potential of the conductor and the back surface thereof are the same potential.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体素子製造装置に係り、詳しくは、例え
ば、LSI等の製造の分野に用いて好適な、半導体素子
を製造する半導体素子製造装置に関する。
The present invention relates to a semiconductor element manufacturing apparatus, and more particularly, to a semiconductor element manufacturing apparatus for manufacturing semiconductor elements, which is suitable for use in the field of manufacturing LSIs and the like.

近年、半導体素子の高密度化、および高精細化に伴って
、半導体素子の製造においては、例えば、イオン、プラ
ズマ等の荷電粒子を照射することにより微細な加工を行
なうことのできる半導体装置製造装置が数多く開発され
ている。
In recent years, with the increase in density and definition of semiconductor devices, semiconductor device manufacturing equipment that can perform fine processing by irradiating charged particles such as ions and plasma has become popular in the manufacturing of semiconductor devices. Many have been developed.

これは、例えば、イオン注入により不純物ドーピング量
をコントロールする闇値電圧制御や、プラズマにより基
板となるウェハ上に薄膜を形成したりするために、ウェ
ハに荷電粒子を照射するものであり、このようなプロセ
スにおいては低温化、およびドライ化が進んでおり、ウ
ェハの帯電が起こり易い。
For example, this involves irradiating a wafer with charged particles in order to control the amount of impurity doping through ion implantation, or to form a thin film on the wafer as a substrate using plasma. In recent processes, the temperature and dryness are progressing, making it easy for wafers to become electrically charged.

ウェハの帯電は素子の信転性に悪影響を与えるため、帯
電を防止することが必要となる。
Since electrification of the wafer adversely affects the reliability of the element, it is necessary to prevent electrification.

〔従来の技術〕[Conventional technology]

従来のこの種の半導体素子製造装置としては、例えば、
第4図に示すようなものがある。
Conventional semiconductor device manufacturing equipment of this type includes, for example,
There is something like the one shown in Figure 4.

半導体素子製造装置は、大別して、半導体素子の基板で
あるウェハ1を支持する基板支持手段としてのウェハ支
持台2、およびクランパ3とから構成されている。
The semiconductor device manufacturing apparatus is roughly composed of a wafer support stand 2 as a substrate support means for supporting a wafer 1, which is a substrate of a semiconductor device, and a clamper 3.

ウェハ1は、例えば、シリコンSi等の結晶を薄く切断
して、酸化処理や拡散処理を行なったものであり、ウェ
ハ1上にLSI等の回路が焼き付けられる。
The wafer 1 is, for example, a crystal of silicon Si or the like cut into thin pieces and subjected to an oxidation treatment or a diffusion treatment, and a circuit such as an LSI is printed onto the wafer 1.

ウェハ支持台2は、ウェハ1を水平に保持するものであ
り、クランパ3によってウェハlはウェハ支持台2上に
固定される。
The wafer support 2 holds the wafer 1 horizontally, and the wafer 1 is fixed on the wafer support 2 by the clamper 3.

以上の構成において、ウェハlに、例えば、イオン注入
によるドーピング等を行なう場合、この工程は一般に、
ドーパン)1度分布の制御等のため低温化、およびドラ
イ化された状態で、ウェハ支持台2、およびクランパ3
によりしっかりと固定されたウェハ1の上方から荷電粒
子であるイオンを所定の加速エネルギーで照射し、イオ
ン注入を行なうものである。
In the above configuration, when doping the wafer l by, for example, ion implantation, this step is generally performed as follows.
Dopan) The wafer support table 2 and the clamper 3 are placed in a low temperature and dry state to control the 1 degree distribution, etc.
Ion implantation is performed by irradiating ions, which are charged particles, with a predetermined acceleration energy from above the wafer 1, which is firmly fixed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、このような従来の半導体素子製造装置に
あっては、低温化、およびドライ化された状態において
、ウェハl上に荷電粒子を照射するという構成となって
いたため、第5図に示すように、ウェハ1の表面の電位
と裏面の電位とが異なる電位となり、ウェハ1の表面の
絶縁膜に電界が生じ、酸化膜等の絶縁膜が照射損傷を受
けるという問題点があった。
However, in such conventional semiconductor device manufacturing equipment, charged particles are irradiated onto the wafer l in a low temperature and dry state, so as shown in FIG. There was a problem in that the potential on the front surface and the potential on the back surface of the wafer 1 were different, an electric field was generated in the insulating film on the front surface of the wafer 1, and the insulating film such as an oxide film was damaged by radiation.

これは、半導体素子の長期的な信幀性上、問題となる。This poses a problem in terms of long-term reliability of semiconductor devices.

そこで本発明は、半導体素子の基板上に発生する電界を
緩和し、絶縁膜の損傷を防止する半導体素子製造装置を
提供することを目的としている。
SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor device manufacturing apparatus that alleviates the electric field generated on the substrate of a semiconductor device and prevents damage to an insulating film.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による半導体素子製造装置は上記目的達成のため
、その原理図を第1図に示すように、半導体素子の基板
1を支持する基板支持手段2.3によって支持される半
導体素子の基板lに荷電粒子を照射する半導体素子製造
装置において、前記基板支持手段2,3は少な(とも前
記基板1に接する部分を導体で形成し、前記基板lの表
面、および裏面の電位が同電位となるように該導体の電
位を制御する電位制御手段4を設けるように構成してい
る。
In order to achieve the above object, the semiconductor device manufacturing apparatus according to the present invention, as shown in the principle diagram in FIG. In a semiconductor device manufacturing apparatus that irradiates charged particles, the substrate supporting means 2 and 3 are small (both have portions in contact with the substrate 1 made of a conductor so that the front and back surfaces of the substrate 1 have the same potential). A potential control means 4 for controlling the potential of the conductor is provided in the conductor.

〔作用〕[Effect]

本発明では、電位制御手段によって導体の電位が制御さ
れ、導体に接する基板の表面、および裏面の電位が同電
位となるように制御される。
In the present invention, the potential of the conductor is controlled by the potential control means so that the potentials of the front and back surfaces of the substrate that are in contact with the conductor are at the same potential.

すなわち、半導体素子の基板上に発生する電界が緩和さ
れ、電界による絶縁膜の損傷が防止される。
That is, the electric field generated on the substrate of the semiconductor element is relaxed, and damage to the insulating film due to the electric field is prevented.

〔実施例〕〔Example〕

以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.

第3図は本発明に係る半導体素子製造装置をイオン注入
装置に適用した一実施例を示す概略断面図である。
FIG. 3 is a schematic cross-sectional view showing an embodiment in which the semiconductor device manufacturing apparatus according to the present invention is applied to an ion implantation apparatus.

まず、構成を説明する。First, the configuration will be explained.

第3図において、第1図に示した原理図に付された番号
と同一番号は同一部分を示す。
In FIG. 3, the same numbers as those attached to the principle diagram shown in FIG. 1 indicate the same parts.

本実施例の半導体素子製造装置であるイオン注入装置は
、大別して、基板支持手段であるウェハ支持台2、およ
びクランパ3と、電位制御手段である抵抗4と、ターン
テーブル5とがら構成されている。
The ion implantation apparatus, which is the semiconductor device manufacturing apparatus of this embodiment, can be roughly divided into a wafer support stand 2 and a clamper 3, which are substrate support means, a resistor 4, which is a potential control means, and a turntable 5. .

半導体素子の基板であるウェハ1を支持する基板支持手
段としてのウェハ支持台2、およびクランパ3と、電位
制御手段としての抵抗4と、ウェハ支持台2、およびク
ランパ3を配置するターンテーブル5とから構成されて
いる。
A wafer support stand 2 as a substrate support means for supporting a wafer 1 which is a substrate of a semiconductor element, a clamper 3, a resistor 4 as a potential control means, a turntable 5 on which the wafer support stand 2 and the clamper 3 are arranged. It consists of

本実施例のウェハ支持台2は、金属製の導体で形成され
ており、半導体素子の基板であるウェハ1を水平に保持
した状態で、クランパ3によってウェハ支持台2上にし
っかりと固定している。
The wafer support 2 of this embodiment is made of a metal conductor, and is firmly fixed onto the wafer support 2 by a clamper 3 while holding the wafer 1, which is a substrate of a semiconductor element, horizontally. There is.

抵抗4は、その一端を導体であるウェハ支持台2に接続
し、他端をターンテーブル5を介して接地電位と接続し
ている。
The resistor 4 has one end connected to the wafer support 2 which is a conductor, and the other end connected to the ground potential via the turntable 5.

なお、抵抗4の値は、ウェハ支持台2とターンテーブル
5との時定数τがイオンビームのパルス周期よりも十分
に小さな値となるように考慮して設定する。すなわち、
本実施例のイオンビームによるパルス幅は1 tase
cであり、パルスの周期は60m5ecであるので、ウ
ェハ支持台2とターンテーブル5との時定数τを、例え
ば、lQmsecとなるように抵抗4の値を設定する。
Note that the value of the resistor 4 is set in consideration so that the time constant τ between the wafer support stand 2 and the turntable 5 will be a value sufficiently smaller than the pulse period of the ion beam. That is,
The pulse width of the ion beam in this example is 1 tase
c, and the pulse period is 60 m5 ec, so the value of the resistor 4 is set so that the time constant τ between the wafer support stand 2 and the turntable 5 is, for example, lQmsec.

次に、作用を説明する。Next, the effect will be explained.

まず、ターンテーブル4上のウェハ支持台2にクランパ
によってしっかりと固定されたウェハ1に対して、イオ
ン注入のためにイオンビームが照射されると、ウェハ支
持台2がターンテーブルを介して直接接地電位に接続さ
れているため、瞬間的にウェハ1の表面が高電位になり
、ウェハ1の表面の電位と裏面の電位との間に電位差が
生じる。
First, when the wafer 1, which is firmly fixed to the wafer support 2 on the turntable 4 by a clamper, is irradiated with an ion beam for ion implantation, the wafer support 2 is directly grounded via the turntable. Since the wafer 1 is connected to a potential, the front surface of the wafer 1 becomes a high potential instantaneously, and a potential difference is generated between the front surface potential and the back surface potential of the wafer 1.

しかし、第5図に示した従来例と異なり、ウェハ支持台
2が抵抗4を介して接地電位と接続されているため、す
ぐにウェハlの裏面は表面と同様に帯電し、ウェハ1の
表面と裏面との電位差が低減される。
However, unlike the conventional example shown in FIG. The potential difference between the surface and the back surface is reduced.

したがって、ウェハ1上に発生する電界を緩和でき、絶
縁膜の損傷を防止できる。
Therefore, the electric field generated on the wafer 1 can be relaxed, and damage to the insulating film can be prevented.

また、本実施例のように、ウェハ支持台2とターンテー
ブル5との時定数τをイオンビームのパルス周期(60
msec)よりも十分に小さな値である10m5ecに
抵抗4の値を設定することにより、1つのパルスがウェ
ハ1を通過する間ではウェハ支持台2の電荷が放出され
ないので、ウェハ1の表面と裏面との間に電位差が生じ
ず、次のパルスが来るまでには放電されるため、電荷の
繰り返し蓄積を防止できる。
In addition, as in this embodiment, the time constant τ between the wafer support stand 2 and the turntable 5 is set to the pulse period of the ion beam (60
By setting the value of the resistor 4 to 10 m5ec, which is a sufficiently smaller value than Since there is no potential difference between the two and the two pulses are discharged before the next pulse arrives, repeated accumulation of charge can be prevented.

このように本実施例では、電位制御手段によってウェハ
支持台の電位を制御することにより半導体素子のウェハ
の表面、および裏面の電位を同電位となるように制御で
きる。
As described above, in this embodiment, by controlling the potential of the wafer support by the potential control means, the potentials of the front and back surfaces of the wafer of the semiconductor element can be controlled to be the same potential.

すなわち、半導体素子の基板上に発生する電界を緩和で
き、この電界による絶縁膜の損傷を防止できる。
That is, the electric field generated on the substrate of the semiconductor element can be relaxed, and damage to the insulating film caused by this electric field can be prevented.

したがって、半導体素子の信鱈性を長期にわたって保持
できる。
Therefore, reliability of the semiconductor device can be maintained for a long period of time.

なお、上記実施例はイオン注入装置に適用した場合を例
にとって説明したが、これに限らず、荷電粒子を照射す
る工程を有する装置、例えば、プラズマ照射を行なう半
導体素子製造装置にも適用可能であるこというまでもな
い。
Although the above embodiment has been described with reference to the case where it is applied to an ion implantation device, the present invention is not limited to this, and can also be applied to a device that has a step of irradiating charged particles, for example, a semiconductor device manufacturing device that performs plasma irradiation. Needless to say, there is.

〔発明の効果〕〔Effect of the invention〕

本発明では、電位制御手段により基板支持手段の導体の
電位を制御することにより、半導体素子の基板の表面、
および裏面の電位を同電位となるように制御できる。
In the present invention, by controlling the potential of the conductor of the substrate support means by the potential control means, the surface of the substrate of the semiconductor element,
It is possible to control the potentials of the two surfaces and the back surface to be at the same potential.

したがって、半導体素子の基板上に発生する電界を緩和
でき、電界による絶縁膜の損傷を防止できる。
Therefore, the electric field generated on the substrate of the semiconductor element can be alleviated, and damage to the insulating film due to the electric field can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理図、 第2図は本発明をイオン注入装置に適用した一実施例を
示す概略断面図、 第3図は第2図のウェハに電界が作用した場合の電荷の
分布を示す図、 第4図は従来例の構成を示す断面図、 第5図は第4図のウェハに電界が作用した場合の電荷の
分布を示す図である。 1・・・・・・ウェハ(基板)、 2・・・・・・ウェハ支持台(基板支持手段)3・・・
・・・クランパ(基板支持手段)、4・・・・・・抵抗
(電位制御手段)、5・・・・・・ターンテーブル。 第 ■ 図 42図のウェハに電界が作用した場合の電荷の分布を示
す図第 図 従来例の構成を示す断面図 第4図のウェハに電界が作用した場合の電荷の分布を示
す図第5図
Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a schematic sectional view showing an embodiment in which the present invention is applied to an ion implantation device, and Fig. 3 is a diagram of the charge when an electric field acts on the wafer shown in Fig. 2. FIG. 4 is a cross-sectional view showing the configuration of a conventional example, and FIG. 5 is a diagram showing the distribution of charges when an electric field is applied to the wafer of FIG. 4. 1...Wafer (substrate), 2...Wafer support stand (substrate support means) 3...
... Clamper (substrate support means), 4 ... Resistor (potential control means), 5 ... Turntable. 42 A diagram showing the charge distribution when an electric field is applied to the wafer. 2. A cross-sectional view showing the configuration of the conventional example. figure

Claims (1)

【特許請求の範囲】  半導体素子の基板を支持する基板支持手段によって支
持される半導体素子の基板に荷電粒子を照射する半導体
素子製造装置において、 前記基板支持手段は少なくとも前記基板に接する部分を
導体で形成し、 前記基板の表面、および裏面の電位が同電位となるよう
に該導体の電位を制御する電位制御手段を設けることを
特徴とする半導体素子製造装置。
[Scope of Claims] In a semiconductor device manufacturing apparatus that irradiates charged particles onto a substrate of a semiconductor device supported by a substrate support means for supporting a substrate of a semiconductor device, the substrate support means has at least a portion in contact with the substrate made of a conductor. 1. A semiconductor device manufacturing apparatus, comprising: a potential control means for controlling the potential of the conductor so that the front surface and the back surface of the substrate have the same potential.
JP25252390A 1990-09-20 1990-09-20 Semiconductor element manufacturing equipment Pending JPH04130626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25252390A JPH04130626A (en) 1990-09-20 1990-09-20 Semiconductor element manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25252390A JPH04130626A (en) 1990-09-20 1990-09-20 Semiconductor element manufacturing equipment

Publications (1)

Publication Number Publication Date
JPH04130626A true JPH04130626A (en) 1992-05-01

Family

ID=17238556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25252390A Pending JPH04130626A (en) 1990-09-20 1990-09-20 Semiconductor element manufacturing equipment

Country Status (1)

Country Link
JP (1) JPH04130626A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013531950A (en) * 2010-07-06 2013-08-08 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ Method of embedding piezoelectric material

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013531950A (en) * 2010-07-06 2013-08-08 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ Method of embedding piezoelectric material
US9991439B2 (en) 2010-07-06 2018-06-05 Commissariat à l'énergie atomique et aux énergies alternatives Method for implanting a piezoelectric material
KR101856797B1 (en) * 2010-07-06 2018-06-19 꼼미사리아 아 레네르지 아토미끄 에뜨 옥스 에너지스 앨터네이티브즈 Method for implanting a piezoelectric material

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