JPH04130555A - Transfer rate measuring device for multidata bus tester - Google Patents

Transfer rate measuring device for multidata bus tester

Info

Publication number
JPH04130555A
JPH04130555A JP2251553A JP25155390A JPH04130555A JP H04130555 A JPH04130555 A JP H04130555A JP 2251553 A JP2251553 A JP 2251553A JP 25155390 A JP25155390 A JP 25155390A JP H04130555 A JPH04130555 A JP H04130555A
Authority
JP
Japan
Prior art keywords
multidata
bus
data
transfer rate
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2251553A
Other languages
Japanese (ja)
Inventor
Yoshiro Aoshima
芳郎 青島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP2251553A priority Critical patent/JPH04130555A/en
Publication of JPH04130555A publication Critical patent/JPH04130555A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To automatically measure the transfer rate of a message to be transferred on a multidata bus by providing a means detecting a specific command word in the message to be transferred on the multidata bus and a means measuring the detection space of this specific command word. CONSTITUTION:The setting of a C/W (command word) is performed against a host computer 5. This set data is transferred through a CPU part 4 and a communication memory part 3 to a mu program control part 2. The mu program control part 2 performs the check of the designated C/W when monitoring the data on the multidata bus. In the case of the designated C/W, a counter 6 is read, the result is stored in the communication memory part 3, and the counter 6 is reset. This data is transferred through the CPU part 4 to the host computer 5 (personal computer) and displayed on a CRT after converted into real-time data. Thus, since the designation of the C/W and the comparison of the data on the multidata bus is performed like a software, the transfer rate on the arbitrary C/W can be measured.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多重データバスに連接されるリモートターミ
ナル及びバスコント田−ラの機能確認に適用されるパス
モニタ機能の丸めの転送レート計測装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a rounding transfer rate measuring device for a path monitor function applied to confirming the functions of remote terminals and bus controllers connected to a multiplex data bus.

〔従来の技術〕[Conventional technology]

従来の計測装置(以下パステスタという)のパスモニタ
機能は、全てのコマンドワード(c、’w )間のギャ
ップタイムを計測していた。(第2図参照)。
The path monitor function of a conventional measuring device (hereinafter referred to as a path tester) measures the gap time between all command words (c, 'w). (See Figure 2).

なお第2図でt #′i1 C/Wの転送レートを示す
時間、 D/Wはデータワード、5/Wはステータスワ
ード、MSGはメツセージを示す。
In FIG. 2, t#'i1 is a time indicating the transfer rate of C/W, D/W is a data word, 5/W is a status word, and MSG is a message.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従って、ある特定のC/W間のギャップタイム(すなわ
ち転送レート)を知るためには、計測したギャップの和
を求めなければならなかった。
Therefore, in order to know the gap time (ie, transfer rate) between a specific C/W, it was necessary to find the sum of the measured gaps.

しかしながら、上記の様な手計算による方法では転送レ
ートが多種で、各レートのメツセージが多量にあり九場
合、非常に時間がかかるだけでなく、計算ミス等の弊害
が発生する可能性(欠点)かめりた。
However, in cases where there are many different transfer rates and a large number of messages for each rate, the manual calculation method described above not only takes a lot of time, but also has the possibility of causing problems such as calculation errors (disadvantages). Camelita.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、パスモニタ実行時、予め指定したυ實を検知
し1次に同じC/Wを検知するまでのギャップタイムを
1μ−〇c単位で計測し、CRTに表示するまでの処理
を自動的に行うことを特徴とするものである。
The present invention automatically measures the gap time between detecting a pre-specified υ truth and detecting the same C/W in units of 1μ-〇c when executing the path monitor, and automatically performs the process of displaying it on the CRT. It is characterized by the fact that it is carried out in

〔作用〕[Effect]

上記の様に構成される本発明のバステスタにあっては、
多重データバス上を伝送する各メツセージの転送レート
が自動的に計測(検証)可能となる。
In the bus tester of the present invention configured as described above,
The transfer rate of each message transmitted on the multiplex data bus can be automatically measured (verified).

〔実施例〕〔Example〕

以下、第1図を用いて本発明の詳細な説明する。Jは多
重データバスインタフェース部でろシデータパスの信号
変換を行う、2はμプログラム制御部で1及び3のハー
ドウェアをマイクロプログラミング方式で制御する。3
はデュアルポートメモリを内蔵し、2とCPU部4との
データのやり取りな行うコミユニケージ曹ンメモリ部で
ある。
Hereinafter, the present invention will be explained in detail using FIG. 1. J is a multiplex data bus interface unit that performs signal conversion of the data path, and 2 is a μ program control unit that controls the hardware 1 and 3 using a microprogramming method. 3
2 is a memory section that has a built-in dual port memory and exchanges data between the CPU section 2 and the CPU section 4.

−qイコンのCPU部4はホストコンピュータ5から送
られたデータのコミユニケージ璽ンメモリs3への格納
及びμプログラム制御部2から送られたデータのホスト
コンビエータへの転送を行う。ホストコンピュータ5は
オペレータとのマンマシンインタフェースを行う。上記
の構成において、まず、オ被レータがホストコンビエー
タ5に対し。
The CPU section 4 of the -q icon stores data sent from the host computer 5 in the computer memory s3 and transfers the data sent from the μ program control section 2 to the host combiator. The host computer 5 provides a man-machine interface with the operator. In the above configuration, first, the operator is connected to the host combiator 5.

C/Wの設定を行う。Configure C/W.

この設定データa CPU部4およびコミュニケーシヲ
ンメモIJ i[l 3を経て、μプログラム制御部2
に転送される。μプログラム制御部2Fi多重データバ
ス上のデータをモニタする際、指定された岬か否かのチ
エツク本行う。指定されたC/Wの場合、カウンタ6を
リードし、結果をコミユニケージ1ンメモリ部JK格納
し、カウンタ6をリセットする。このデータはCPU部
4を経て図中ホストコンピュータ5に転送され、実時間
データに変換ばれた後CRTに表示される。又、 C/
Wの指定及び多重データバス上のデータとの比較はソフ
ト的に行われるため、任意のC/W Kついての転送レ
ートが計測可能とカつている。
This setting data a is transferred to the μ program control unit 2 via the CPU unit 4 and the communication memo IJi[l3.
will be forwarded to. When monitoring the data on the μ program control unit 2Fi multiplex data bus, a check is performed to see if it is a specified cape. In the case of the specified C/W, the counter 6 is read, the result is stored in the memory section JK of the community unit 1, and the counter 6 is reset. This data is transferred to the host computer 5 in the figure via the CPU section 4, converted into real-time data, and then displayed on the CRT. Also, C/
Since the designation of W and the comparison with the data on the multiplex data bus are performed by software, the transfer rate for any C/W K can be measured.

〔発明の効果〕〔Effect of the invention〕

以上の様に本発明忙よれば、多重データバス上を伝送す
る任意のメツセージ(C/W )の転送レートが自動的
に計測(検証)可能となる。
As described above, according to the present invention, the transfer rate of any message (C/W) transmitted on a multiplex data bus can be automatically measured (verified).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の1実施例を説明するための機能プロ ツク図である。 第2図は従来のバステスタ の計測していたプヤッグタイ ムの説明図である。 FIG. 1 shows a functional program for explaining one embodiment of the present invention. This is a diagram. Figure 2 shows a conventional bus tester Puyagtai was measuring FIG.

Claims (1)

【特許請求の範囲】[Claims] 多重データバス上を伝送するメッセージ中の特定のコマ
ンドワードを検知する手段と、この特定のコマンドワー
ドの検知間隔を計測する手段とを具備することを特徴と
する多重データバステスタにおける転送レート計測装置
A transfer rate measuring device for a multiplex data bus tester, comprising means for detecting a specific command word in a message transmitted on a multiplex data bus, and means for measuring a detection interval of the specific command word. .
JP2251553A 1990-09-20 1990-09-20 Transfer rate measuring device for multidata bus tester Pending JPH04130555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2251553A JPH04130555A (en) 1990-09-20 1990-09-20 Transfer rate measuring device for multidata bus tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2251553A JPH04130555A (en) 1990-09-20 1990-09-20 Transfer rate measuring device for multidata bus tester

Publications (1)

Publication Number Publication Date
JPH04130555A true JPH04130555A (en) 1992-05-01

Family

ID=17224540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2251553A Pending JPH04130555A (en) 1990-09-20 1990-09-20 Transfer rate measuring device for multidata bus tester

Country Status (1)

Country Link
JP (1) JPH04130555A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802302A (en) * 1995-06-29 1998-09-01 International Business Machines Corporation System and method for response time measurement in high speed data transmission networks

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802302A (en) * 1995-06-29 1998-09-01 International Business Machines Corporation System and method for response time measurement in high speed data transmission networks
US5946302A (en) * 1995-06-29 1999-08-31 International Business Machines Corporation System and method for response time measurement in high speed data transmission networks

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