JPH04127714A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an output transistor from being destroyed due to flow of an over current into the output transistor by making the output transistor to OFF state even when an external output terminal is erroneously short- circuited. CONSTITUTION:When an external output terminal OUT is erroneously short- circuited to a -2.0V, the over current apt to flow to a resistor R6. In such case, however, a voltage V is made lower than a reference voltage Vs by the current flowing to the resistor R6, and the output of a buffer gate 24 is turned to a high level. This high level is held in a flip-flop 26, a transistor T6 is turned to an ON state, the base potential of an output transistor T4 is lowered, and the output transistor T4 is turned to the OFF state. Thus, the output transistor is prevented from being destroyed by the short-circuit accident of the external output terminal OUT.

Description

[Detailed description of the invention] 【overview】

Regarding semiconductor integrated circuits equipped with open emitter type or open source type output transistors in their output buffer circuits, the voltage applied to the control terminals is An output transistor in which a corresponding current flows between one end and the other end, one end of which is connected to an external output terminal, and an overcurrent detection circuit that is connected between the other end of the output transistor and a power supply line. a resistor, a comparison circuit that compares the voltage V at the other end of the output transistor with a reference voltage Vs, a memory circuit that stores that the comparison circuit detects a voltage V<Vs; The control circuit lowers the base potential of the output transistor to turn off the output transistor only while the detection is stored.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit in which an output buffer circuit includes an output transistor of an oven emitter type or an oven source type.

[Conventional technology]

E CL (Emitter [:upled Lo
gic) and 5CFL (Source Couple
d FET Logic) is used as a high-speed logic gate. FIG. 3 shows a main part of a semiconductor integrated circuit 10 equipped with an ECL output buffer circuit 12. This output buffer circuit 12 has an oven emitter as an output transistor of a differential amplifier circuit, and connects the collectors of a pair of NPN transistors T1 and T2 to a power supply line VCC via resistors R1 and R2, respectively. By making the emitters of transistors T1 and T2 common, NPN
It is connected to power supply lines v, , through a current source 16 composed of a type transistor T3 and resistors R3 and R4. For example, the power supply line■. 0 is OV, power supply line V ee
is E, 2V. The collectors of transistors Tl5T2 are also connected to NPN output transistors 1'4 and T2, respectively.
The collectors of the output transistors T4 and T5 are connected to the power supply line V in common. , is connected to. The emitters of the output transistors T4 and T5 are connected to external output terminals OUT and 0UTX of the semiconductor integrated circuit 10, respectively. A reference voltage V9 and an input terminal 1 are applied to the bases of the transistors TI and T2, respectively, and the difference between them is amplified and taken out to external output terminals OUT and 0UTX. A resistor R5 is connected to the external output terminal UT for impedance matching with the next stage circuit. for example,
Resistor R5 is 50 ohms and -2 at one end of resistor R5.
, OV are applied, and in this case, a maximum current of about 40 mA flows through the resistor R5. Since both the output buffer circuit 12 and the resistor R5 have relatively large current consumption, in order to reduce the current consumption of the semiconductor integrated circuit 10, the resistor R5 is
5 is externally attached. Furthermore, in order to increase the output amplitude of the output buffer circuit 12, the resistor R5 is placed near the next stage circuit. In such a circuit, if the resistor R5 is accidentally short-circuited, an excessive current flows through the output transistor T4, destroying the output transistor T4 and causing the semiconductor integrated circuit 10 to become defective. . The same applies to the external output terminal 0UTX. FIG. 4 shows a main part of a semiconductor integrated circuit 101 equipped with a 5CFL output buffer circuit 121. This output buffer circuit 121 includes a resistor R1i and a transistor Tl i (i
=1 to 5) correspond to the resistor Ri and transistor Ti in FIG. Note that resistors R11 and R12 are diodes D
A common power supply line V. Connected to C. Further, the transistors T11, T12, T14, and 15 are enhancement type GaΔ5FETs, and the transistor T13 is a depletion type GaAsFET. In the case of this semiconductor integrated circuit 101, the output transistor T
14 is connected to the external output terminal OUT 1, and for the same reason as above, a resistor R15 is externally connected to the external output terminal OUT 1, and the resistor R15 is placed near the next stage circuit. A similar problem arises.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide a semiconductor integrated circuit that can prevent defects due to short circuits of external output terminals.

[Means to solve the problem]

FIG. 1 shows the principle configuration of a semiconductor integrated circuit l according to the present invention. This semiconductor integrated circuit 1 includes the following components 3 to 6.
The output buffer circuit 2 has an output buffer circuit 2 equipped with the following. In the figure, 3 is an output transistor, for example an NPN transistor or a depletion type GaAsFET, and a
A current corresponding to the voltage applied to the IJ terminal flows between one end and the other end, and the one end is connected to the external output terminal OUT. Reference numeral 4 denotes an overcurrent detection resistor, which is connected between the other end of the output transistor 3 and the power supply line vcC. A comparison circuit 5 compares the voltage V at the other end of the output transistor 3 with a reference voltage (2). Reference numeral 6 denotes a storage circuit, which stores the fact that V<VS has been detected by the comparison circuit 5. Reference numeral 7 denotes a control circuit, which lowers the base potential of the output transistor 3 to turn off the output transistor 3 only when the memory circuit 6 stores the detection.

[Effect]

Normally, V>Vs holds true, and a current flows through the output transistor 3 in accordance with the voltage applied to the control terminal, as in the conventional case. If you accidentally short-circuit the external output terminal OUT, connect resistor 4.
An excessive current is about to flow. However, in this case, resistance 4
The current flowing in causes the voltage V to be lower than the reference voltage Vs, and the control circuit 7 turns off the output transistor. Therefore, destruction of the output transistor 3 due to a short circuit of the external output terminal OUT is prevented, and the semiconductor integrated circuit is prevented from becoming defective.

【Example】

An embodiment of the semiconductor integrated circuit according to the present invention will be described below with reference to FIG. Components that are the same as those in FIG. 3 are given the same reference numerals and their explanations will be omitted. This semiconductor integrated circuit 10A has an output buffer circuit 12A.
This circuit differs from the circuit shown in FIG. 3 in that overcurrent protection circuits 18 and 20 are added to output transistors T4 and T5, respectively. The overcurrent protection circuits 18 and 20 have the same configuration, and the configuration of the overcurrent protection circuit 20 is not shown. In order to detect the current flowing between the collector and emitter of the output transistor T4, a resistor R6 is connected between the collector of the output transistor T4 and the power supply line Vcc. The resistor R6 is approximately 1/10 of the resistor R5 in order to prevent the output amplitude of the external output terminal OUT from becoming small.
For example, set it to 5Ω. The voltage V at the connection point between the collector of the output transistor T4 and the resistor R6 is supplied to the inverting input terminal of the differential amplifier 22, and is compared with the reference voltage Vs supplied to the non-inverting input terminal of the differential amplifier 22. Differential amplifier 2
The output terminal of 2 is connected to the input terminal of the flip 70 tube 26 via a buffer gate 24. The output terminal of the flip-flop 26 is connected to the base of the transistor T6 via a resistor R8. The collector of transistor T6 is connected to the base of output transistor T4 via resistor R9, and the emitter of transistor T6 is connected to power supply line V0. It is connected to the. Other points are the same as in FIG. Next, the operation of this embodiment configured as described above will be explained. Normally, regardless of the level change of the input terminal Vs, V>V
5 is established. Therefore, the outputs of the buffer gate 24 and the flip 70 tube 26 are at a low level, and the transistor T6 is turned off. Therefore, the operation of the output buffer circuit 12A is the same as that of the output buffer circuit 12 in FIG. 3. If the external output terminal 0LIT is accidentally short-circuited to -2, OV, an excessive current will flow through the resistor R6. However, at this time, the voltage V becomes lower than the reference voltage (2) due to the current flowing through the resistor R6, and the output of the buffer gate 24 becomes high level. This high level is held in the flip-flop 26, turning on the transistor T6, lowering the base potential of the output transistor T4, and turning the output transistor T4 off. Therefore, destruction of the output transistor T4 due to a short-circuit accident at the external output terminal OUT is prevented. The same applies to the output transistor T5, the overcurrent protection circuit 20, and the external output terminal 0UTX. Note that the provision of the overcurrent protection circuits 18 and 20 complicates the output buffer circuit 12A, but since the chip area occupation rate of the output buffer circuit 12A with respect to the entire semiconductor integrated circuit 10A is small, the complication of the semiconductor integrated circuit can be ignored. can. Further, in the above embodiment, the overcurrent protection circuits I8 and 20 are applied to an ECL circuit, but it goes without saying that they can be similarly applied to a 5CFL circuit as shown in FIG.

【Effect of the invention】

As explained above, in the semiconductor integrated circuit according to the present invention,
Even if the external output terminal is accidentally short-circuited, the output transistor is turned off, which prevents excessive current from flowing to the output transistor and destroying the output transistor. It has the effect of being able to prevent defects in semiconductor integrated circuits, and greatly contributes to improving the reliability of semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle configuration of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a main part circuit diagram of a semiconductor integrated circuit equipped with an ECL output buffer circuit according to an embodiment of the present invention. . 3 and 4 relate to conventional examples. FIG. 3 is a circuit diagram of a main part of a semiconductor integrated circuit equipped with an ECL output buffer circuit. FIG. 4 is a main part of a semiconductor integrated circuit equipped with a 5CFL output buffer circuit. It is a circuit diagram. In the figure, l01IOA and IOB are semiconductor integrated circuits 12.12A,
121 is the output buffer circuit 16 is the current source 18. 20 is the overcurrent protection circuit 22 is the differential amplifier 24 is the buffer gate 26 is the flip-flop OUT, ○UTISOOUTX, 0UTIX is the outside 1 Semiconductor integrated circuit 2: Output buffer circuit diagram UTX Figure 3

Claims (1)

[Claims] An output transistor (3) in which a current according to a voltage applied to a control terminal flows between one end and the other end, and one end of which is connected to an external output terminal (OUT), and the output transistor an overcurrent detection resistor (4) connected between the other end of the output transistor and the power supply line, and a comparison circuit (5) that compares the voltage V at the other end of the output transistor with a reference voltage V_s; a memory circuit (6) that stores that V<V_s has been detected in the comparison circuit; and a memory circuit (6) that lowers the base potential of the output transistor to reduce the output transistor only while the memory circuit stores the detection. 1. A semiconductor integrated circuit comprising: an output buffer circuit (2) having a control circuit (7) for turning off.