JPH04127568A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To enable a delay and an addition process to be executed inside a photodetective element even if the element has defects by a method wherein a delay means, a charge eliminating means, and a composing means are provided inside a device respectively. CONSTITUTION:Signal charges separately taken out of photodetective elements 1011-101n are delayed through delay means 1021-102n independently, then transferred through charge transfer elements 1001-100n separately, made to reach to a synthesis means 104, and added together and synthesized there, whereby the TDI processed image signals excellent in S/N can be obtained. The signal charge transmitted from the photodetective element of defect out of the photodetective elements 1011-101n is eliminated through the prescribed charge eliminating means out of charge eliminating means 1031-103n while it is transferred, so that it is prevented from being transferred to the synthesis means 104. Therefore, a TDI processing can be executed inside a device without deteriorating an image in S/N due to a photodetective element of defect.

Description

[Detailed Description of the Invention] [Summary] Regarding a solid-state imaging device having a means for delaying and adding signal charges from a plurality of arrayed light receiving elements inside the element, the present invention relates to a solid-state imaging device that has means for delaying and adding signal charges from a plurality of arranged light receiving elements within the element. In a solid-state imaging device in which signal charges obtained by photoelectric conversion by a plurality of light-receiving elements are input to a plurality of charge transfer elements for the purpose of performing addition processing, the signal charges are accumulated and transferred, and an imaging signal is extracted. For each output signal charge of the light receiving elements arranged in a direction perpendicular to the optical scanning direction of the light receiving elements, T
delay means for applying different delays for DI processing and inputting them to the corresponding charge transfer elements; and charges provided in the transfer paths of the plurality of charge transfer elements for erasing signal charges from defective light receiving elements. It has an erasing means, and a synthesizing means for adding and synthesizing each signal charge taken out from the plurality of charge transfer elements and extracting it as an imaging signal, and the delay means, the charge erasing means, and the synthesizing means are each provided inside the device. Configure it like this.

[Industrial application field]

The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having means for delaying and adding signal charges from a plurality of arrayed light receiving elements within the element.

Signal-to-noise ratio (S/N) of readout video signal of solid-state imaging device
) as a processing method to improve TDT (Time
Delay & Integration) is known.

This TDI performs optical scanning in the arrangement direction of a plurality of light receiving elements 1 arranged at a constant pitch as shown in Fig. 6, and each signal charge extracted from each of the plurality of light receiving elements 1 is amplified by a corresponding amplifier 2. After that, it is supplied to the delay and adder 3, where it is delayed in synchronization with optical scanning, and the signal charge from the previous stage light receiving element in the optical scanning direction is added to the input signal from the delay and adder 3. As a result, the signals from the plurality of light receiving elements 1 at the same scanning point of the subject are individually added and combined to become a large level, whereas noise changes randomly, so the above addition does not result in a large level. , a video signal with improved S/N as a whole can be taken out from the output terminal 4.

A solid-state imaging device employing such a TDI method is required to take advantage of the above-described features of the TDI method under any conditions.

[Conventional technology]

FIG. 7 shows a configuration diagram of an example of a conventional solid-state imaging device. In the figure, 6. -6N are photodiode arrays in which a plurality of photodiodes are arranged one-dimensionally in the vertical direction in the figure; 7. 7N is a shift register using a charge transfer device (COD), and is provided corresponding to the photodiode arrays 61 to 6N. In addition, the photodiode array 6L
6N and CCD shift registers 71 to 7N are arranged in N rows in a direction perpendicular to the element arrangement direction, and constitute a two-dimensional light receiving section and a multiplexer.

Optical scanning is performed from right to left in the figure, which causes the photodiode array 6. ~6N, the signal charges obtained by photoelectrically converting the light from the object are transferred to the adjacent CCD shift registers 7l~7N, and then each signal charge is transferred from top to bottom in the figure to the COD shift registers 71~7N. 7
, is transferred to the amplifier 8. ~8N in parallel. The signals from each CCD shift register 71-7N amplified by amplifiers 81-8N are sent to A/D converters 9. ~9N
are converted into digital signals respectively.

Output digital data of A/D converters 91 to 9□ among A/D converters 91 to 9N are respectively stored in memories 10. ~10s-+ via data selector 11. ~11.1, respectively, and A
The output digital data of the /D converter 9N is directly sent to the data selector 11. without going through the memory. is input. memory lO
i-th from 0 to 10.1 (where i=1.2.・
...N-1) memory stores and reads out (N-i) lines of input digital data.
) Delay the line period.

Memory 10. Each output delayed signal of ~10 s-+ is supplied to the adder 13 through the data selectors IIl-llN-+, where it is added to the output digital data of the A/D converter 9. As described above, optical scanning is performed from the photodiode arrays 6 to 6N, and adjacent photodiodes (pixels) in the optical scanning direction have a time difference of one line period. However, here, since the memories 10l to 10s-+ are used to delay the predetermined period, the adder 13 adds data from the same position of the subject, and therefore the level of the signal component becomes large. On the other hand, since the noise hardly increases,
The adder 13 takes out data based on the principle of TDI, which has an overall improved S/N ratio.

By the way, if any of the photodiodes constituting the photodiode arrays 7l to 7N is defective, the output signal charge of that photodiode will be different from that of a normal photodiode, so performing the above TDI operation will actually reduce the S/N. may decrease.

Therefore, in this conventional solid-state imaging device, the position of the defective photodiode is stored in advance in a programmable read-only memory (FROM) 12, and the position of the defective photodiode is stored in advance.
According to the output signal of the ROM 12, when the output data is from a normal photodiode, the memory 10. -10□1 and the A/D converter 9, and select data "0" in place of the output data from a defective photodiode if the data is output from a defective photodiode. ~11. I'm trying to control it.

As a result, the output of the defective photodiode is ignored, and the TDI operation described above can be performed without any problem.

[Problem to be solved by the invention]

However, in the solid-state imaging device described above, the TDI operation is performed by an external circuit of the solid-state imaging device, and the external circuit increases in accordance with the number of columns N of the photodiode arrays 6l to 6N. There is a problem in that miniaturization is a disadvantage.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a solid-state imaging device that can perform delay and addition processing within the light-receiving element even if the light-receiving element has a defect.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. The present invention includes delay means 102 l to 102 , charge erasing means 103 □
~103. and a composition means 104 inside the apparatus. Here, delay means 1021 to 102
．． are light receiving elements 1011 to 101. which are arranged in a direction orthogonal to the optical scanning direction among the plurality of light receiving elements. For each output signal charge, a different delay is applied for TDI processing to the corresponding charge transfer elements 1001 to 100. Enter.

Charge erasing means 1031-103. is a charge transfer element 100
l~100. are provided in the middle of the transfer path, respectively, to erase signal charges from defective light-receiving elements. In addition, the synthesis means 104
The signal charges taken out from the charge transfer elements 1001 to 100 are added and combined, respectively, and taken out as an imaging signal.

Note that the light receiving elements 101 l to 101 may be arranged in two or more rows in the optical scanning direction, and the delay means I02. The delay time may be zero.

[Effect]

The signal charges taken out from the light-receiving elements 1011-101, respectively are sent to delay means 1021-102. After being separately delayed by charge transfer elements 100 . .about.1001 are separately transferred to the synthesizing means 104, where they are added and synthesized, and are taken out as TDI-processed imaging signals with a good S/N ratio.

Moreover, the light receiving element 101. .about.101, when the signal charge is transferred, it is erased by a predetermined negative charge erasing means among the charge erasing means 1031 to 1031, and is not transferred to the combining means 104. Therefore, in the present invention, S/
TDI processing can be performed inside the device without the phenomenon that N decreases.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, N photodiodes PD are arranged one-dimensionally in the vertical direction.
, l to PDIN and N photodiodes PD, .

That is, in this embodiment, the light receiving elements 101l to 101
, photodiodes corresponding to PD+l~PD, and PD*l~PD! Two N are arranged in the optical scanning direction, and this is an example where n=2.

Further, each of the photodiodes PI)z to PD has a first storage electrode SG, 1. ~
S G IIN + first transfer electrode T G + + l
~TG81. Second storage electrode SG! II~SG! IN+
Second transfer electrode T G *+ I-T G *+s r
Transfer unit 201 using a charge transfer device (CCD). ~20
1 are arranged in sequence. Similarly, each of the photodiodes PD□ to PD□ has storage electrodes SG, □ to S G l! sequentially in the opposite direction to the optical scanning direction. N + transfer electrode TG
*t-, CCD transfer unit 20tl to 201N7! l
'It is arranged. The above storage electrodes SG,,l~SG2
．． N is provided for delaying one line period, and corresponds to the delay means 1021.

Note that the storage electrode corresponding to the delay means 102t is omitted because the delay time is zero in this embodiment.

Further, the transfer units 20+s and 20ts have a reset gate 21 for erasing defective pixels. ,．． 2L, and reset drains 21+o, 21ttl for erasing defective pixels are provided, respectively, and reset transistors 21+, 2 having these are provided.
Is is the charge erasing means 103.

103.

OG is an output gate, and transfer unit 201. ~20. N.

209. ~20. Signal charges from N are transferred. FD
is a floating diffusion layer and a field effect transistor (FET) 22
are connected to the gate of FET 23 and the drain of FET 23, respectively. The output gate OG and the floating diffusion layer FD are connected to the synthesis means 10.
4.

In this embodiment with such a configuration, the photodiode PD
z~PD,,,PD! l~PD! The signal charges obtained by photoelectric conversion at N are applied to the storage electrodes SG, 1 to SG, +-, S to which the pulse VSG shown in FIG. 4 is applied.
It is sent to the board directly below G 1tl~SG+*- and is accumulated there. The signal charges accumulated for one line period on the substrate immediately below the storage electrodes SG,, SG IIN are transferred to the transfer electrodes TG, to which a pulse shown as φTGI in FIG. 4 is applied.
+ storage electrode SG through the substrate directly under TGzH,
l~SG! It reaches the board directly below the IN and is accumulated.

Storage electrode SG,! l ~ SG, □ The signal charge from the photodiode PD, -PD, N accumulated on the substrate directly below and the storage electrode SG,, l ~ S G ! , - Photodiode P D + l ~ PD, N accumulated on the substrate directly below
The signal charges delayed by one line period from the transfer electrode T G to which the same pulse φTG2 shown in FIG.
! I l~TG! 1N, TG! ! It passes through the board immediately below I~TG*tN at the same timing, and transfers to the transfer section 20.1~
201N, 20!1~20! Transferred to H.

The transfer units 2011 to 20□ and 20*l to 20I are the fourth
This is a CCD driven by four-phase clocks, which are shown as φ1 to φ4 in the figure, and whose phases differ by 90 degrees from each other.
Signal charges are transferred from top to bottom and supplied to output gate OG. Two transfer units 20 and N enter the floating diffusion layer FD through this OG.

20, the signal charges related to the same object part from H are added and converted to voltage, and then output to terminal 24 as a high S/N imaging signal processed by TDI via FET 22 of the source follower amplifier. be done. FET23 is the fourth
It is turned on by the reset pulse φR shown in the figure, and the signal charge stored in the floating diffusion layer FD is swept out to the semiconductor substrate, and then it is turned off again to prepare for inputting the signal charge of the next bit.

The pulse φDl+ + φ, in FIG. 4 is the gate 21
,,． 21! . The signal applied to the FET 21. is set to high level only at the time of signal charge transfer of the defective photodiode (pixel), and is applied to the FET 21. .

21, is turned on.

Next, there is a reset gate 21 for erasing defective pixels, which is the main part of this embodiment. . , 21. . , reset drain 21 ,,,
21! D, the structure and operation of the output gate ○G and floating diffusion layer FD will be explained in more detail with reference to FIG. In FIG. 3, the same components as those in FIG. 2 are given the same reference numerals, and their explanations will be omitted.

In FIG. 3, 31. ~31. are transfer electrodes on the semiconductor substrate, which constitute the transfer section 201N;
324 is a transfer electrode also formed on the semiconductor substrate,
Transfer section 20. It constitutes N.

That is, a transfer section having four transfer electrodes is formed corresponding to one photodiode.

The above four transfer electrodes 31□~314, 321~324
The same four-phase clocks φ1 to φ4 are respectively applied to the same four-phase clocks φ1 to φ4. As a result, the potential of the substrate immediately below the transfer electrode to which the clock φ1°φ is applied and the clock φ3. Signal charges are transferred by alternately raising and lowering the potential of the substrate directly under the transfer electrode to which φ4 is applied.

In addition, defective pixel erasing reset FETs 21 + and 21 t are connected to the transfer units 20+s and 20tN, and FETs 21. ．． 2 The source region of It is the transfer electrode 31
, and 3L, 32. and 32. It consists of the board directly below it. These FETs 21+ and 212 are normally turned off.

Now, as shown in FIG. 3, the transfer electrodes 3i, 3
A potential well 33 is formed in the semiconductor substrate directly below the transfer electrodes 32 . .

It is assumed that a potential well 35 is formed in the semiconductor substrate directly under the semiconductor substrate 322. Does the amount of signal charge when the photodiode is normal change depending on the amount of light incident on the photodiode, or does it correspond to the signal charge 36 accumulated in the potential well 35 under normal usage conditions? If the diode has a defect such as a white spot, the amount of charge becomes considerably large, such as the signal charge 34 accumulated in the potential well 33.

Since it is known in advance whether the photodiode is defective or not, when the signal charge from the defective photodiode (pixel) is stored in the potential well 33,
A high level signal is applied to the gate of FET211 and F
ET21. or is turned on. As a result, the signal charge 34 of the defective pixel is transferred to the turned-on FET 21. Since it is swept out to the semiconductor substrate through the source and drain of the OG, it is not transferred to the output gate (OG).

Note that the signal charges 36 are then transferred to the transfer electrodes 32 . ．． 32! As shown by the broken line 37, the potential immediately below rises and the transfer electrodes 32z, 32
Since the potential directly below 4 falls as shown by the broken line 38, it is transferred to the potential well 38, and then the potential directly below the transfer electrodes 32°, 32*, 32s and 324 changes again as shown by the solid line 35.39. Therefore, a constant potential 4 lower than potential 39
floating diffusion layer FD through the substrate directly under the output gate OG of 0
The signal is input to the terminal 24, is converted into a voltage, and is then outputted to the terminal 24 through the gate and source of the FET 22.

Note that, before the signal charges of the next bit are input, the signal charges in the floating diffusion layer FD are swept out to the semiconductor substrate because the reset pulse φR lowers the potential to the position shown by the dashed line 41 and 42.

Of course, when signal charges from a normal photodiode are accumulated in the potential well 33, the signal charges are accumulated in the floating diffusion layer FD in the same manner as described above.

Next, the fifth section regarding the imaging device equipped with the above-described device of the present invention.
This will be explained with figures. In the figure, reference numeral 50 denotes the solid-state imaging device according to the present invention shown in FIG. 2, in which the four-phase clocks φ1 to φ, VS
G.

VSO4, φTG1. While various pulses and bias voltages such as φTG, .

On the other hand, the light from the object to be imaged passes through the lens 55, is totally reflected by the mirror 56, and enters the solid-state imaging device 50. This mirror 56 is rotated back and forth within a predetermined angle range by a scanner 57, and optically scans the light incident on the solid-state imaging device 50 from the object to be imaged in a direction perpendicular to the CCD transfer direction.

The imaging signal taken out from the solid-state imaging device 50 is supplied to the amplifier 58 via the terminal 24 described above, where it is amplified, and then subjected to signal processing in the signal processing circuit 59. The signal from the signal processing circuit 59 is converted into a signal form suitable for display by a display circuit 60 and then displayed by a cathode ray tube (CRT) 61.

In such an imaging device, the TDI operation described above is performed inside the solid-state imaging device 50, so the number of external circuits of the imaging device is reduced compared to a conventional imaging device in which the TDT operation is performed outside the solid-state imaging device. Miniaturization of imaging devices,
Higher performance is possible.

Note that the present invention is not limited to the above-described embodiments; for example, the number of photodiode columns in the optical scanning direction may be three or more, and in this case, the number of storage electrodes and transfer electrodes adjacent to the photodiode array is increased. This can be easily realized, and the increase in area of the solid-state imaging device itself can be made smaller compared to the increase in external circuit area in conventional devices.

〔Effect of the invention〕

As described above, according to the present invention, TDI can be achieved within the device without the phenomenon of S/N reduction due to defective light receiving elements.
Since the TDI processing can be performed, an external circuit for TDI processing can be eliminated, and it has the advantage of greatly contributing to the miniaturization and higher performance of imaging devices.

4,

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of the main part of an embodiment of the present invention, and Fig. 4 is a diagram similar to that of Fig. 2. FIG. 5 is a diagram illustrating the configuration of an imaging device equipped with the device of the present invention, FIG. 6 is a diagram illustrating the principle of TDI, and FIG. 7 is a configuration diagram of an example of a conventional device. In the figure, 2011~20+N, 20*l~20. N is the transfer unit, 2
1+, 21z are reset FETs for erasing defective pixels, 100
1-100. are charge transfer elements, 1011-101. is a light receiving element, 1021-102. 1031-103 is a delay means, 1031-103 is a charge erasing means, 104 is a combining means, OG is an output gate, FD is a floating diffusion layer, PDz-PD, FD2. ~PD! N indicates a photodiode. Fig. 2 A diagram illustrating the principle of TDI in the optical scanning direction Fig. 6

Claims (3)

[Claims] (1) Signal charges obtained by photoelectric conversion by multiple light receiving elements are transferred to multiple charge transfer elements (100_l to 100_m)
In a solid-state imaging device that inputs, accumulates and transfers, and extracts an image signal, a TDI is generated for each output signal charge of the light receiving elements (101_l to 101_m) arranged in a direction orthogonal to the optical scanning direction of the plurality of light receiving elements. Delay means (102_
charge erasing means (103_l to 103_m) that are provided in the middle of the transfer paths of the plurality of charge transfer elements (100_l to 100_m) and erase signal charges from the defective light receiving elements.
and a synthesizing means (104) for adding and synthesizing each signal charge extracted from the plurality of charge transfer elements (100_l to 100_m) and extracting it as an imaging signal, the delaying means (102_l to 102_m), the charge Eliminating means (103_l to 103_m) and combining means (1
04) respectively inside the device. (2) The charge erasing means (103_l to 103_m) are turned on by a pulse inputted in synchronization with the transfer timing of signal charges from the defective light receiving element, so that the charge erasing means (103_l to 103_m) are The solid-state imaging device according to claim 1, comprising transistors (21_1, 21_2) that sweep signal charges into a substrate on which the charge transfer elements (100_l to 100_m) are formed. (3) The synthesizing means (104) includes an output gate (OG) commonly provided on each output side of the plurality of charge transfer elements (100_l to 100_m), and an output gate (OG)
2. The solid-state imaging device according to claim 1, further comprising a single floating diffusion layer (FD) that adds and synthesizes each signal charge that has passed through the FD.