JP2000224492A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of preventing the fluctuation of the loads of a vertical shift register for read and the vertical shift register for an electronic shutter in the case of performing an electronic shutter operation and preventing the generation of image noise such as horizontal stripes on the display screen of output signals. SOLUTION: This device is provided with an image pickup area where a unit cell provided with a photodiode PD to be a pixel is two-dimensionally arranged, plural read lines 4 for driving the read transistor Td of each pixel row, plural vertical selection lines 6 for driving the vertical selection transistor Ta of each of the pixel rows, a vertical driving circuit 24 for selectively driving the plural read lines 4 and selectively driving the plural vertical selection lines 6, plural vertical signal lines VLIN for outputting signals from each unit cell of the successively driven pixel rows and row selection circuits 2, 21 and 22 for controlling the vertical driving circuit so as to successively drive the read transistor Td of each pixel two times at a desired signal storage timing and a signal read timing and to drive the vertical selection transistor Ta of the pixel row at the signal read timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a variable electronic shutter control circuit and a pixel signal readout control circuit of a solid-state imaging device, and is used for, for example, a video camera and an electronic still camera.

[0002]

2. Description of the Related Art FIG. 12 shows an equivalent circuit of a CMOS solid-state imaging device (amplification type CMOS image sensor) of a first conventional example having a readout circuit capable of reading out a pixel signal for each pixel.

In FIG. 12, unit cells of one pixel (one pixel) / one unit are arranged in a two-dimensional matrix in a cell area (imaging area).

Each unit cell includes, for example, four transistors Ta, Tb, Tc, Td and one photodiode P
D.

That is, a photodiode PD having a ground potential applied to the anode side, a readout transistor (shutter gate transistor) Td having one end connected to the cathode side of the photodiode PD, and a gate connected to the other end of the readout transistor Td. , A vertical selection transistor (row selection transistor) Ta having one end connected to one end of the amplification transistor Tb, and a reset transistor Tc having one end connected to the gate of the amplification transistor Tb. Is provided.

The readout transistors T of the unit cells in the same row are provided in the cell area corresponding to each pixel row.
d, a read line 4 commonly connected to the gate of the unit cell, a vertical select line 6 commonly connected to the gate of each vertical select transistor Ta of the unit cell in the same row, and a reset transistor Tc of the unit cell in the same row. A reset line 7 commonly connected to the gate is formed.

In the cell region, a vertical signal line VLIN commonly connected to the other end of each amplifying transistor Tb of a unit cell in the same column and a unit cell in the same column are provided corresponding to each pixel column. A power supply line 9 commonly connected to the other end of each reset transistor Tc and the other end of each vertical select transistor Ta is formed.

Further, a plurality of load transistors TL respectively connected between one end of the vertical signal line VLIN and a ground node are horizontally arranged outside one end of the cell region.

Further, outside the other end of the cell region, for example, two transistors TSH and TCLP and two capacitors C
A plurality of noise canceller circuits composed of c and Ct are arranged in the horizontal direction.

[0010] A plurality of horizontal selection transistors TH connected to the other ends of the vertical signal lines VLIN via the respective noise canceller circuits are arranged in the horizontal direction.

A horizontal signal line HLIN is commonly connected to the other ends of the horizontal selection transistors TH, and a horizontal reset transistor (not shown) and an output amplifier circuit AMP are connected to the horizontal signal line HLIN. .

Each of the noise canceller circuits has a sample and hold transistor TSH having one end connected to the other end of the vertical signal line VLIN, and one end connected to the other end of the sample and hold transistor TSH. A coupling capacitor Cc, a charge storage capacitor Ct connected between the other end of the coupling capacitor Cc and a ground node, and a potential clamping transistor TCLP connected to a connection node between the capacitors Cc and Ct. And one end of the horizontal selection transistor TH is connected to a connection node between the capacitors Cc and Ct.

Further, outside the cell region, a vertical shift register 2 for scanningly controlling a plurality of vertical selection lines 6 in the cell region, and a horizontal shift register for scanningly driving the horizontal selection transistor TH. A register 3, a timing generating circuit 10 for generating various timing signals to be supplied to the noise canceller circuit and the like, and a potential clamping transistor TCLP of the noise canceller circuit.
A bias generating circuit 11 for generating a predetermined bias potential at one end or the like, and a pulse for selectively controlling an output pulse of the vertical shift register 2 to drive the vertical selection line 6 in each row of the cell region in a scanning manner. The selectors 2a are arranged respectively.

FIG. 13 is a timing waveform chart showing an example of the operation of the solid-state image sensor shown in FIG.

Next, the operation of the solid-state image sensor of FIG. 12 will be described with reference to FIG.

Signal charges generated by photoelectrically converting incident light of each photodiode PD are accumulated in the photodiode PD.

In the horizontal blanking period, when reading out the signal charge of the photodiode PD from a unit cell of a certain row, first, in order to select each of the vertical signal lines VLIN, the signal of the vertical selection line 6 of the selected row is selected. Turning on the φADRES pulse) turns on the row selection transistors Ta for one row.

As a result, in the unit cells for one row, the source follower circuit including the amplifying transistor Tb supplied with the power supply potential VDD (for example, 3.3 V) via the row selection transistor Ta and the load transistor TL is operated.

Next, in the unit cells for one row, the signal (.phi.RESET pulse) of the reset line 7 is turned on, and the gate voltage of the amplification transistor Tb is reset to the reference voltage for a certain period of time. Output voltage.

However, there is a variation in the gate potential of the amplification transistor Tb reset as described above, and a variation also appears in the reset potential of the vertical signal line VLIN on the other end.

Therefore, in order to reset the variation of the reset potential of each vertical signal line VLIN, it is necessary to reset (for example, the φ
The drive signal (φSH pulse) of the sample and hold transistor TSH in the noise canceller circuit is turned on at the same time as the ADRES pulse is turned on, and the vertical signal line VLIN is turned on.
By turning on the drive signal (φCLP pulse) of the potential clamping transistor TCLP for a certain period of time after the reference voltage is output to the capacitor C of the noise canceller circuit,
A reference voltage is set to the connection node between c and Ct.

Next, after turning off the φRESET pulse,
By selecting the read line 4 of a predetermined row and turning on the signal (φREAD pulse), the read transistor Td
Is turned on, and the charge stored in the photodiode PD is read out to the gate of the amplification transistor Tb to change the gate potential. The amplification transistor Tb outputs a voltage signal corresponding to the amount of change in the gate potential to the corresponding vertical signal line VLIN and the noise canceller circuit.

Thereafter, φ in the noise canceller circuit
By turning off the SH pulse, a signal component (signal voltage from which noise has been removed) corresponding to the difference between the reference voltage and the signal voltage read as described above is applied to the charge storage capacitor Ct during the horizontal effective scanning period. Can also be accumulated.

That is, each vertical signal line caused by the cell region
Noise mixed into the previous stage from the noise canceller circuit, such as variation in the reset potential of VLIN, is removed.

Then, by turning off the φADRES pulse, the vertical selection transistor Ta is controlled to be turned off and the unit cell is set to the non-selected state, so that the cell region and each noise canceller circuit are electrically separated. .

By sequentially turning on the drive signal (φH pulse) of the horizontal selection transistor TH during the subsequent horizontal effective scanning period, the horizontal selection transistor TH is sequentially turned on, and the connection node (signal signal) of the capacitors Cc and Ct is turned on. The signal voltage of the storage node is sequentially read out to the horizontal signal line HLIN, amplified by the output amplifier circuit AMP, and output.

In the above operation, the voltage of the vertical signal line VLIN
VVLIN becomes the operating voltage Vm (approximately 1.5 V) of the source follower circuit during the horizontal flyback period. The above-described noise removal operation is performed for each horizontal line read operation.

FIG. 14 shows the timing generator 10, the vertical shift register 2, and the pulse selector 2a in FIG.
FIG. 6 is a timing waveform chart showing an operation example of FIG.

Here, a case is shown in which the solid-state imaging device of FIG. 12 is used in a system of 1 field = 1/30 Hz (30 frames / sec image where 1 field is 1 frame).

The timing generation circuit 10 shapes the external input pulse signals φVR and φHP by a buffer circuit, and outputs a pulse signal φVRR having a field cycle and a pulse signal φHPV having a horizontal cycle.
Is input to the vertical shift register 2.

The vertical shift register 2 has a pulse signal φVR
After the register output is all cleared to the “L” level while the R input is at the “L” level, the shift operation is performed by the pulse signal φHPV and the output pulse signal ROi (i =..., N, n + 1,
..) Are sequentially set to the “H” level, and the pulse selector 2 a
To enter.

The pulse selector 2a outputs a signal of the vertical selection line 6 (φADRES pulse), a signal of the reset line 7 (φRESET pulse), and a signal of the read line 4 (φ
READ pulse) is activated as shown in FIG. 13, and the selected row is scanned.

As described above, the solid-state imaging device of FIG. 12 outputs each output pulse signal ROi of the vertical shift register 2 for selectively controlling a specific selection target row only once in one field period. That is, the photodiode P
Since D performs signal readout only once in one field, an electronic shutter operation for equivalently controlling the light receiving time by controlling the signal accumulation time of the photodiode PD is impossible.

On the other hand, FIG. 15 schematically shows the structure of a CMOS solid-state imaging device according to Conventional Example 2 capable of performing an electronic shutter operation.

This solid-state imaging device has an imaging area (photoelectric conversion unit) 14 in which pixel cells 13 configured as shown in FIG. 12 are two-dimensionally arranged in a matrix, for example. Multiple vertical signal lines VLIN formed in the column direction
And a plurality of read control vertical selection lines formed in the pixel row direction of the imaging region 14 for controlling the photoelectric conversion signal of each pixel cell 13 to be read to the plurality of vertical signal lines VLIN in pixel row units. 6, a first vertical selection circuit (reading vertical shift register) 2 for scanningly controlling the plurality of read control vertical selection lines 6 at a read timing, and the vertical signal line VLIN. Select transistor TH, a horizontal select circuit (horizontal select shift register) 3 for selectively controlling the horizontal select transistor, and a signal for reading the vertical signal line VLIN selected by the horizontal select shift register 3. And an output amplifier circuit AMP for outputting a signal read out to the horizontal signal line HLIN.

Although not shown, a point that a load transistor and a noise canceller circuit as shown in FIG.
This is the same as the MOS solid-state imaging device.

Further, a second vertical selection circuit (vertical shift register for electronic shutter) 15 for scanningly controlling the plurality of read control vertical selection lines 6 at the timing of signal accumulation, and the first vertical selection circuit 15 A vertical drive circuit (not shown) for generating a drive signal for selectively driving the plurality of read control vertical select lines 6 based on the output of the vertical select circuit and the output of the second vertical select circuit. Have.

That is, the read vertical shift register 2
In addition, a vertical shift register 15 for an electronic shutter is provided, and the vertical shift register 15 for the electronic shutter is also configured to scan a selection target row at a predetermined timing similarly to the vertical shift register 2 for reading. I have.

Thus, the vertical shift register 2 for reading and the vertical shift register 15 for electronic shutter can selectively control a specific row to be selected at two timings within one field period.

Therefore, the read vertical shift register 2 controls the selection of the row to be selected and transmits the pixel signal to the vertical signal line.
Before the readout to the VLIN, the electronic shutter vertical shift register 15 controls the selection of the row to be selected and starts accumulating the pixel signals, thereby enabling an electronic shutter operation equivalently controlling the light receiving time.

By the way, the CMOS solid-state image pickup device shown in FIG. 15 having one vertical shift register 2 for reading and one vertical shift register 15 for electronic shutter as described above automatically operates according to the output level of the light receiving sensor, for example. When performing a variable electronic shutter operation in which the light receiving time is equivalently changed by changing the signal accumulation time, a difference in the signal accumulation time may occur between pixel rows depending on the length of the signal accumulation time, Vertical shift registers 2, 1
5 has a problem that the load fluctuates.

This problem will be described below.

FIG. 16 shows an example in which the row selection timing of the two vertical shift registers 2 and 15 in FIG. 15 is fixed.

As shown in FIG. 16, the vertical shift register 15 for the electronic shutter is
The timing of selecting rows earlier than is fixed.
That is, the time difference between the two vertical shift registers 2 and 15 performing row selection is always constant.

As described above, the two vertical shift registers 2,
In the case where the row selection timing of the row 15 is fixed, the vertical shift register 2 for reading and the vertical shift register 15 for the electronic shutter start selecting a certain frame from the first stage to the last stage (that is, the vertical direction of the solid-state imaging device). When the shift operation of (number of pixels) ends, the process returns to the initial stage again and the selection of the next frame is started.

Therefore, the solid-state imaging device shown in FIG. 15 can be used, for example, to perform a variable electronic shutter operation in which the light receiving time is equivalently changed by automatically changing the signal accumulation time according to the output level of the light receiving sensor. In addition, there is a problem that a difference in signal accumulation time occurs between pixel rows depending on the length of the signal accumulation time and that the loads of the two vertical shift registers 2 and 15 fluctuate.

Here, as a specific method for changing the signal accumulation time, the timing at which the electronic shutter vertical shift register 15 selects a row before the read vertical shift register 2 (the timing of the electronic shutter) is set. The above problem will be described in detail with reference to FIG. 17 when changing the length of time for accumulating pixel signals by changing.

In FIG. 17, the read control pulse is a signal for starting the shift operation of the read vertical shift register 2, and the variable electronic shutter control pulse is a signal for starting the shift operation of the electronic shutter vertical shift register 15.

(1) When selecting the first frame, FIG.
After the shift operation of the electronic shutter vertical shift register 15 is started by the control pulse of the electronic shutter generated at the timing t1 in 7 and before the shift operation up to the final stage ends (before selecting all the pixel rows), It is assumed that an electronic shutter pulse has been generated to select the second frame at timing t3 in FIG. In this case, the electronic shutter vertical shift register 15 is reset at the timing t3 and the shift operation (row selection) starts again from the first stage.

Accordingly, when the shift operation of the read vertical shift register 2 is started by the read control pulse generated at the timing t2 in FIG. 17 and the first frame is read, the shift operation is performed at the timing t1. There is a difference in signal accumulation time between the pixel row selected and designated by the electronic shutter vertical shift register 15 started and the pixel row not selected and designated.

When a difference in signal accumulation time occurs as described above,
The read output level fluctuates depending on the position of the pixel row,
When the output signal of the solid-state imaging device is displayed on the screen of the image display device, it causes image noise such as horizontal stripes.

(2) At timing t4 in FIG. 17, the selected row of the electronic shutter vertical shift register 15 whose shift operation has started at the timing t3 and the read vertical shift register 2 whose shift operation has started at the timing t2. Since a total of two selected pixel rows are selected, these two pixel rows load the two vertical shift registers 2 and 15.

On the other hand, at the timing t6 in FIG. 17, the row selected by the electronic shutter vertical shift register 15 whose shift operation has started at the timing t3 does not already exist, and the shift operation at the timing t5 in FIG. Is started, one pixel row is selected by the read vertical shift register 2, and this one pixel row becomes a load on the two vertical shift registers 2 and 15.

As described above, the two vertical shift registers 2,
When the load of No. 15 fluctuates depending on the electronic shutter timing, it causes voltage fluctuation of the power supply line of the solid-state imaging device,
When the output signal of the solid-state imaging device is displayed on the screen of the image display device, a horizontal streak occurs, which significantly deteriorates the image quality.

The above-mentioned problems that the signal accumulation time differs between the pixel rows depending on the length of the signal accumulation time and that the load of the two vertical shift registers 2 and 15 fluctuates are of the CMOS type. Not only the imaging device but also a case where the variable electronic shutter operation is performed by a CCD type solid-state imaging device.

[0056]

As described above, in the conventional solid-state imaging device, when the variable electronic shutter operation is performed by changing the signal accumulation time, the signal accumulation time between pixel rows depends on the length of the signal accumulation time. And the load on the vertical shift register for reading and the vertical shift register for the electronic shutter fluctuates, causing image noise such as horizontal stripes on the display screen of the output signal.

The present invention has been made in order to solve the above-mentioned problems. When the electronic shutter operation is performed, fluctuations in the load of the read vertical shift register and the electronic shutter vertical shift register can be prevented, and the output signal of the electronic shutter can be prevented. An object of the present invention is to provide a solid-state imaging device capable of preventing occurrence of image noise such as horizontal stripes on a display screen.

Further, according to the present invention, when a variable electronic shutter operation (continuous electronic shutter operation) for changing a signal accumulation time of a pixel in a field unit is performed, a load of a read vertical shift register and a load of a vertical shift register for an electronic shutter are reduced. It is an object of the present invention to provide a solid-state imaging device capable of preventing fluctuation and preventing occurrence of image noise such as horizontal stripes on a display screen of an output signal.

It is another object of the present invention to provide a solid-state imaging device capable of preventing a difference in signal accumulation time between pixel rows depending on the length of signal accumulation time when a continuous electronic shutter operation is performed. And

Another object of the present invention is to provide a solid-state imaging device capable of preventing occurrence of image noise such as horizontal stripes on a display screen of an output signal when a continuous electronic shutter operation is performed.

Another object of the present invention is to provide a solid-state imaging device capable of preventing noise from jumping in from wiring around the pixel due to capacitive coupling when reading out a signal photoelectrically converted and stored in the pixel. .

[0062]

A first solid-state imaging device according to the present invention comprises: photoelectric conversion means for photoelectrically converting incident light to a pixel to accumulate charges; reading means for reading the accumulated charges to a detection unit; A unit cell having amplification means for amplifying the applied charge, reset means for resetting the charge of the detection section, and vertical selection means for outputting a signal from the amplification means, is two-dimensionally arranged on a semiconductor substrate. , A plurality of signal reading pixel rows and at least two pixel rows.
An imaging region having two dummy pixel rows, and a read driving signal for driving each reading unit of the unit cell of the corresponding pixel row are provided in a horizontal direction corresponding to each pixel row in the imaging region. A plurality of read lines for transmitting a row selection drive signal for driving each vertical selection means of a unit cell of a corresponding pixel row, provided in a horizontal direction corresponding to each pixel row in the imaging area. A plurality of vertical selection lines for selectively reading and driving the read means by selectively supplying a read drive signal to the plurality of read lines, and selecting a row selection drive signal for the plurality of vertical select lines. A vertical driving means for supplying the data and driving the vertical selection means, and a reading means for each pixel row in the image pickup area with a desired signal accumulation timing and signal reading time. Row selection means for controlling the vertical driving means so as to be sequentially driven twice by scanning, and each unit of a pixel row provided in correspondence with each pixel column in the imaging region and sequentially driven by the vertical driving means A plurality of vertical signal lines for transmitting signals output from the cells in the vertical direction, and the row selecting means, from the unit cells of the plurality of signal read pixel rows by the vertical driving means. After controlling the signal reading, selection control is performed so as to drive the first dummy pixel row of the two dummy pixel rows, and the vertical driving means controls the signals in the unit cells of the plurality of signal reading pixel rows. After controlling the accumulation, selection control is performed so as to drive a second dummy pixel row of the two dummy pixel rows.

The second solid-state imaging device according to the present invention is a photoelectric conversion means for photoelectrically converting incident light to a pixel to accumulate charges, a reading means for reading the accumulated charges to a detection unit, and amplifying the read charges. Amplifying means, unit cells having reset means for resetting the charge of the detection unit and vertical selection means for outputting a signal from the amplifying means are two-dimensionally arranged on a semiconductor substrate, and a plurality of pixel rows are arranged. A plurality of imaging regions provided in a horizontal direction corresponding to each pixel row in the imaging region, and for transmitting a read driving signal for driving each reading unit of a unit cell of the corresponding pixel row. A read line and a horizontal line corresponding to each pixel row in the imaging region are provided for driving each vertical selection unit of the unit cell of the corresponding pixel row. A plurality of vertical selection lines for transmitting a selection drive signal; and a read drive signal selectively supplied to the plurality of read lines to drive the read means, and a row is supplied to the plurality of vertical selection lines. Vertical driving means for selectively supplying a selection driving signal to drive the vertical selection means, and sequentially driving the reading means of each pixel row in the imaging region twice at desired signal accumulation timing and signal reading timing. Row selection means for controlling the vertical driving means so as to cause the signal to be output from each unit cell of a pixel row provided in correspondence with each pixel column in the imaging region and sequentially driven by the vertical driving means. And a plurality of vertical signal lines for transmitting the signal in the vertical direction. A first means for driving a readout means of a raw row, and at least two second means for driving a readout means of each pixel row at the signal accumulation timing by the vertical drive means. .

The third solid-state imaging device according to the present invention includes the second solid-state imaging device.
In the solid-state imaging device, the imaging region may further include at least three dummy pixel rows in addition to the plurality of pixel rows for signal readout, and the row selection unit may include the first pixel row.
Means for driving one of the dummy pixel rows among the dummy pixel rows, and driving the other two of the dummy pixel rows by the two second means. .

The fourth solid-state imaging device according to the present invention is characterized in that:
Alternatively, in the third solid-state imaging device, the row selection unit changes a signal accumulation timing within a period of one field cycle in units of one field corresponding to a cycle of a signal read timing of each pixel row.

The fifth solid-state imaging device according to the present invention is characterized in that:
In the solid-state imaging device, the at least two second units drive the read unit by relatively different signal accumulation timings with respect to the signal read timing, and drive the read unit. The control operation of the vertical driving means is alternately switched every field.

The sixth solid-state imaging device according to the present invention is characterized in that
In any one of the solid-state imaging devices according to any one of the fifth to fifth aspects, when the row selection unit drives the reading unit of each pixel row in the imaging region twice, the row selection unit may be adjacent to the reading line around the photoelectric conversion unit. The vertical driving means is controlled so that the voltage of the wiring is substantially the same during the two driving operations.

According to the seventh solid-state imaging device of the present invention, when reading out the accumulated charges from the photoelectric conversion elements of the unit cells two-dimensionally arranged in the imaging region on the semiconductor substrate, a wiring for controlling the reading is provided with a desired wiring. In a solid-state imaging device that performs an electronic shutter operation of sequentially driving twice at a signal accumulation timing and a signal reading timing and outputting a signal read at the signal reading timing, the solid-state imaging device is adjacent to a wiring for controlling the reading, The voltage of another wiring existing around the conversion element is made substantially the same at the signal accumulation timing and the signal read timing.

The eighth solid-state imaging device according to the present invention has two pixels /
In a solid-state imaging device having an imaging region in which one unit cell is two-dimensionally arranged on a semiconductor substrate, when reading out stored charges from photoelectric conversion elements of two pixels in the unit cell of the imaging region, And the voltage of another wiring adjacent to the photoelectric conversion element and present around the photoelectric conversion element is made substantially the same when each pixel is read.

[0070]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows an equivalent circuit of an amplification type CMOS solid-state imaging device according to a first embodiment.

The CMOS solid-state image pickup device shown in FIG. 1 is almost the same as the CMOS solid-state image pickup device of the conventional example 2 described above with reference to FIG. 15, but has a vertical shift register 2a for reading and an electronic shutter. The vertical shift register 15a is different from that of FIG.
The same reference numerals as in the figure are used.

That is, the CMOS solid-state imaging device of FIG. 1 has an imaging area (photoelectric conversion unit) in which pixel cells 13 configured as shown in, for example, the conventional example 1 of FIG. 12 are two-dimensionally arranged in a matrix. 14, a plurality of vertical signal lines VLIN formed in the pixel column direction of the imaging region 14, and the plurality of vertical signal lines VLIN formed in the pixel row direction of the imaging region 14. A plurality of read control vertical selection lines 6 for controlling readout to the vertical signal line VLIN
A first vertical selection circuit (read vertical shift register) 2a for scanningly controlling the plurality of read control vertical selection lines 6 at a read timing; and the plurality of read control vertical selection lines. Vertical selection circuit (a vertical shift register for an electronic shutter) 15a for scanningly controlling the selection of the pixel 6 at the signal accumulation timing, the output of the first vertical selection circuit 2a and the second vertical selection circuit 15a And a vertical drive circuit (pulse selector) 16 for generating a drive signal for selectively driving the plurality of read control vertical selection lines 6 based on the output of the read control signal, and a horizontal selection circuit for selecting the vertical signal line VLIN. Transistor TH
A horizontal selection circuit (horizontal selection shift register) 3 for selectively controlling the horizontal selection transistor TH; and a horizontal signal line HLIN for reading the signal of the vertical signal line VLIN selected by the horizontal selection shift register 3. And an output amplifier circuit AMP for outputting a signal read to the horizontal signal line HLIN.

As in the CMOS solid-state imaging device of the second conventional example shown in FIG. 15, although not specifically shown here, a load transistor and a noise canceller circuit as shown in FIG. ing.

Further, (1) Two dummy pixel rows (a first dummy pixel row 141 and a second dummy pixel row 142) are added to the imaging region 14 separately from the original pixel rows. . (2) The vertical shift register for reading (first vertical shift register) 2a has the number of shift stages equal to the number of original pixel rows in the imaging area 14 + 1, and the vertical shift register for electronic shutter (second vertical shift register). The vertical shift register 15a also has the number of shift stages of the original number of pixel rows of the imaging area 14 + 1.
(3) The vertical drive circuit 16 selects the last stage output signal of the vertical shift register 2a for reading and supplies it to the first dummy pixel row 141, and outputs the last stage output signal of the vertical shift register 15a for electronic shutter. Is selected and supplied to the second dummy pixel row 142.

The two dummy pixel rows 141 and 142
Has the same configuration as the original pixel row, but the vertical drive circuit 1
6 has been added to act as a load when selected.

In the solid-state imaging device shown in FIG. 1, the same vertical selection line can be selectively controlled twice within one field period by the vertical shift register 15a for electronic shutter and the vertical shift register 2a for reading. ,
A shutter operation for controlling a signal accumulation time of a pixel (photodiode) can be performed.

In this case, the vertical shift register 15a for the electronic shutter performs a shift operation based on a shift clock signal for controlling the start timing of signal accumulation, and selectively controls each corresponding pixel row during the shutter operation period. Control is performed so that pixel signal accumulation is performed (readout is not performed). During the period other than the shutter operation period (the period from the end of the selection of the pixel row to the start of the next selection), the second dummy pixel row 14 is controlled.
2 is selected and controlled.

The vertical shift register 2 for reading is
a performs a shift operation based on a shift clock signal that controls a signal read start timing, selectively controls each corresponding pixel row in each horizontal period in a vertical effective scanning period within a vertical period, and performs a vertical flyback period. , The selection control of the first dummy pixel row 141 is performed.

That is, according to the solid-state imaging device of the first embodiment, the vertical drive circuit 16 corresponds to each output of the vertical shift register 2a for reading and the vertical shift register 15a for electronic shutter. Since one pixel row (two pixels in total) is always selected and driven and the selection load is always equal, it is possible to prevent the occurrence of horizontal stripes on the display screen due to the change in the readout level due to the magnitude of the selection load. .

<Second Embodiment> FIG. 2 shows an equivalent circuit of an amplification type CMOS solid-state imaging device according to a second embodiment.

The CMOS solid-state imaging device of FIG. 2 is different from the CMOS solid-state imaging device of the first embodiment described with reference to FIG. (Third dummy pixel row 143) is added. (2) Further, one electronic shutter vertical shift register 15b having the same number of shift stages as the electronic shutter vertical shift register 15a is added. The output of each stage is the vertical shift register 15 for the electronic shutter.
a, which is selected by switching the output of each stage and the field unit and used by the vertical drive circuit (pulse selector) 16a;
(3) The vertical drive circuit 16a generates a drive signal for selectively driving the plurality of read control vertical selection lines 6 based on the outputs of the three vertical shift registers 2a, 15a, and 15b. (4) The vertical drive circuit 16a selects the final output signal of the added vertical shift register 15b for the electronic shutter, and selects the third dummy pixel row 14
3 is slightly different, and the other components are the same.

FIG. 3 is a timing chart showing how the two electronic shutter vertical shift registers 15a and 15b alternately control the electronic shutter operation in field units in the solid-state imaging device of FIG.

As can be seen from the timing chart shown in FIG. 3, in the solid-state imaging device shown in FIG. 2, the shift operations of the two vertical shift registers 15a and 15b dedicated to the electronic shutter are started alternately on a field basis. By alternately selecting the output on a field basis, the electronic shutter operation is alternately distributed on a field basis to the two vertical shift registers 15a and 15b dedicated to the electronic shutter.

In this case, the selected vertical shift registers 15a and 15b dedicated to the electronic shutter perform row selection before the readout vertical shift register 2a, and change the timing to store pixel signals. Can be changed in the length of time to perform.

Accordingly, the variable electronic shutter operation of selecting the same vertical line twice in one field period by the vertical shift registers 15a and 15b for electronic shutter and the vertical shift register 2 for reading and controlling the signal accumulation time of the selected pixel. It can be performed.

Even if the electronic shutter control signal is input at a time interval shorter than the field period, the shift operation of one of the vertical shift registers 15a or 15b dedicated to the electronic shutter, which has already started the shift operation, becomes the last stage. Before reaching (before the selection of all the pixel rows for reading is not completed), the signal accumulation time of the selected pixel is controlled by sequentially selecting up to the last pixel row without being reset halfway.

The period from the end of the selection of the last read pixel row to the start of the selection of the first read pixel row in the next field period is the second dummy pixel row 142 or the third dummy pixel row. Row 143 is selected and controlled.

The vertical shift register 2 for reading is
“a” selectively controls each corresponding pixel row during each horizontal period in the vertical effective scanning period, and selectively controls the first dummy pixel row 141 during the vertical blanking period.

That is, each vertical shift register 2a, 15
A and 15b continue selecting dummy pixel rows even after selecting all readout pixel rows, respectively, and wait for selection start in a later field period.

That is, according to the solid-state imaging device according to the second embodiment, the electronic shutter operation is alternately allocated to the two vertical shift registers dedicated to the electronic shutter in units of fields, so that the signal accumulation time between fields is increased. Can be changed.

In this case, it is possible to realize an electronic shutter function of continuously changing the signal accumulation time on a field-by-field basis while the scanning time for reading remains constant. In the same field, the signal accumulation time is the same for all the selected pixel rows.

When the variable electronic shutter operation is performed by changing the signal accumulation time in this manner, it is possible to prevent a difference in signal accumulation time between pixel rows depending on the length of the signal accumulation time, and to display an output signal. It is possible to prevent the occurrence of image noise such as horizontal stripes on the screen.

The vertical drive circuit 16a has one pixel (total of three) corresponding to each output of the vertical shift register 2a for reading and the vertical shift registers 15a and 15b for two electronic shutters. Since the rows are always selectively driven and the selection loads are always equal, it is possible to prevent the occurrence of horizontal stripes on the display screen due to the change in the read level due to the magnitude of the selection loads.

The solid-state imaging device shown in FIGS. 1 and 2 is not limited to a CMOS type solid-state imaging device having a readout circuit capable of reading out pixel signals for each pixel, but may be read out in units of horizontal signal lines. (Charge-Coupled Device) type solid-state imaging device that performs the above.

<Third Embodiment> FIG. 4 shows an equivalent circuit of an amplification type CMOS solid-state imaging device according to a third embodiment.

The CMOS solid-state imaging device of FIG. 4 automatically changes the signal accumulation time in accordance with, for example, the output level of the light-receiving sensor as compared with the CMOS solid-state imaging device of the first conventional example described above with reference to FIG. Thus, the variable electronic shutter operation for equivalently changing the light receiving time can be continuously changed on a field basis.

That is, the CMOS solid-state imaging device of FIG. 4 is almost the same as the CMOS solid-state imaging device of the first conventional example described above with reference to FIG. 12, but (1) the vertical shift for readout In addition to the register 2, two vertical shift registers 21 and 22 for an electronic shutter are added.
(3) Vertical shift register 2 for two electronic shutters
A register switching control circuit (SEL) 23 for alternately controlling the operations 1 and 22 (output operation of the control pulse of the signal accumulation time) in units of fields is added. (4) The timing generation circuit 10a and Since the configuration of the pulse selector circuit 24 is different and the other components are the same, they are denoted by the same reference numerals in FIG.

That is, in FIG. 4, for example, four transistors Ta, Tb, T
Unit cells of 1 pixel (1 pixel) / 1 unit composed of c and Td and one photodiode PD are arranged in a two-dimensional matrix. In this case, each unit cell includes a photodiode PD to which a ground potential is applied to the anode side, a readout transistor (shutter gate transistor) Td having one end connected to the cathode side of the photodiode PD, and the other end of the readout transistor Td. Transistor Tb whose gate is connected to its side, a vertical selection transistor (row selection transistor) Ta whose one end is connected to one end of the amplification transistor Tb, and reset whose one end is connected to the gate of the amplification transistor Tb. And a transistor Tc.

Then, in the cell region, each read transistor T of the unit cell in the same row corresponds to each pixel row.
d, a plurality of read lines 4 connected in common to the gates, a vertical select line 6 connected in common to the gates of the vertical select transistors Ta in the unit cells in the same row, and reset transistors in the unit cells in the same row. A reset line 7 commonly connected to the gate of Tc is formed.

In the cell region, a vertical signal line VLIN commonly connected to the other end of each amplifying transistor Tb of the unit cell in the same column and a unit cell in the same column corresponding to each pixel column are provided. A power supply line 9 commonly connected to the other end of each reset transistor Tc and the other end of each vertical select transistor Ta is formed.

Further, a plurality of load transistors TL respectively connected between one end of the vertical signal line VLIN and a ground node are horizontally arranged outside one end of the cell region.

Further, outside the other end of the cell region, for example, two transistors TSH and TCLP and two capacitors C
A plurality of noise canceller circuits composed of c and Ct are arranged in the horizontal direction.

A plurality of horizontal selection transistors TH connected to the other ends of the vertical signal lines VLIN via the respective noise canceller circuits are arranged in the horizontal direction.

A horizontal signal line HLIN is commonly connected to the other ends of the horizontal selection transistors TH. A horizontal reset transistor (not shown) and an output amplifier circuit AMP are connected to the horizontal signal line HLIN. .

In each of the noise canceller circuits, a sample and hold transistor TSH having one end connected to the other end of the vertical signal line VLIN, and one end is connected to the other end of the sample and hold transistor TSH. A coupling capacitor Cc, a charge storage capacitor Ct connected between the other end of the coupling capacitor Cc and a ground node, and a potential clamping transistor TCLP connected to a connection node between the capacitors Cc and Ct. And one end of the horizontal selection transistor TH is connected to a connection node between the capacitors Cc and Ct.

Further, outside the cell area, a vertical shift register 2 for reading and a vertical shift register (ES1) for two electronic shutters for scanningly controlling a plurality of vertical selection lines 6 in the cell area. ) 21 and (ES2)
22, a pulse selector 24 for selectively controlling output pulses of the three vertical shift registers 2, 21, and 22 to drive the vertical selection lines 6 in each row of the cell region in a scanning manner, and the plurality of horizontal selection transistors TH. In order to alternately control the operation (output operation of the control pulse of the signal accumulation time) of the horizontal shift register 3 for scanning and driving the vertical shift registers 21 and 22 for the two electronic shutters in units of fields. Register switching control circuit 23, timing generation circuit 10 for generating various timing signals
a, a bias generation circuit 11 for generating a predetermined bias potential is disposed at one end of a potential clamping transistor TCLP of the noise canceller circuit, for example.

The timing generation circuit 10a includes a timing signal φVR of a field cycle, a timing signal φES for accumulation time control variably set in a field cycle,
A pulse signal φHP and a clock pulse signal φCK corresponding to the horizontal retrace period are input.

Then, the timing signal φVR input is buffer-shaped to generate a timing signal φVRR for supply to the read vertical shift register, and the pulse signal φHP input is buffer-shaped to read the vertical shift register and A timing signal φHPV to be supplied to the two vertical shift registers 21 and 22 for the electronic shutter is generated.

Further, timing signals φROREAD, φESREA for supplying to the pulse selector 24 are provided.
D, φRESET, and a pulse signal φCLP for generating φADRES and supplying the same to the noise canceller circuit.
Generate φSH. Further, it generates a pulse signal φH to be supplied to the horizontal shift register 3.

The timing signal φ of the field cycle
Pulse signal φF for field switching control based on VR
I to generate a timing signal φE for controlling the signal accumulation time.
The signal is supplied to the register switching control circuit 23 together with the SR.

The register switching control circuit 23 provides a timing signal φES for accumulation time control for each field unit based on the input of the pulse signal φFI for field switching control.
The supply destination of R is alternately switched. In this case, a timing signal for controlling the signal accumulation time supplied to the vertical shift register 21 for the electronic shutter is represented by φESR1, and a timing signal for controlling the signal accumulation time supplied to the vertical shift register 22 for the electronic shutter is represented by φESR2. ing.

FIG. 5 is a circuit diagram showing an example of the pulse selector 24 in FIG.

The pulse selector shown in FIG. 5 receives the output signal ROn of the vertical shift register for reading, the output signals ES1n and ES2n of the two vertical shift registers 21 and 22 for the electronic shutter, and generates the timing signal. Timing signal φRO supplied from circuit 10a
READ, φESREAD, φRESET, φADRE
S, and performs logical processing on these input signals to generate various drive signals φREADn, φRESET, φADRES.
It is constituted by a logic gate so as to output n and supply it to the cell area.

That is, when the output signal ROn of the read vertical shift register is in the active state, the timing signal φR
OREAD is selected and output as a read line drive signal φREADn. When one of the output signals ES1n and ES2n of the two vertical shift registers 21 and 22 for the electronic shutter is active, the timing signal φESREAD is selected and read. Output as a line drive signal φREADn.

When one of the output signals RO1 of the read vertical shift register and the output signals ES1n and ES2n of the two vertical shift registers 21 and 22 for the electronic shutter is active, the timing signal φRE
SET is selected and output as a reset line drive signal φRESETn.

When output signal ROn of the vertical shift register for reading is active, timing signal φA
DRES to select the vertical select line drive signal φADRESn
Output as

FIG. 6 is a timing chart for explaining a variable electronic shutter operation which can be continuously changed in units of fields in the solid-state imaging device of FIG. Registers 2, 21, 2
2 is a timing waveform chart showing an operation example of the pulse selector 2 and the pulse selector 24. FIG.

Here, a case is shown in which the solid-state imaging device of FIG. 4 is used in an imaging system of one field = 1/30 Hz (an image of 30 frames / sec where one field is one frame).

In FIG. 6, φVR is a timing signal input for the field cycle, φES is a timing signal input for accumulation time control variably set in the field cycle, and φVR
R is a timing signal of a field period supplied to a vertical shift register for reading, φFI is a pulse signal for field switching control, and φESR1 is an accumulation time supplied to one vertical shift register 21 for one electronic shutter every other field. A control timing signal φESR2 is a timing signal for storage time control supplied to the other electronic shutter vertical shift register 22 at one-field intervals, and R0 (i) is a read vertical shift register R0.
, ES1 (i) is the output of the vertical shift register 21 for one electronic shutter, and ES2 (i) is the output of the vertical shift register 22 for the other electronic shutter.

FIG. 7 is a timing waveform chart showing an example of the electronic shutter operation within one field period in FIG.

In FIG. 7, ESn is the output signal of the nth stage of the vertical shift register 21 or 22 for the electronic shutter, and ROn is the output signal of the nth stage of the vertical shift register 2 for reading.

THES indicates one horizontal period in which the output signal ESn of the n-th stage of the vertical shift register 21 or 22 for the electronic shutter becomes active (“H” level).

THRO indicates one horizontal period in which the output signal ROn of the n-th stage of the read vertical shift register 2 is in the active state ("H" level).

HBLK is a control pulse signal for dividing one horizontal period into a horizontal blanking period and a horizontal effective scanning period.

ΦCLP and φSH are pulse signals supplied to the noise canceller circuit, and are generated for each horizontal blanking period.

ΦH is a pulse signal supplied to the horizontal selection transistor TH, and is generated so that the horizontal selection transistors TH arranged in the horizontal direction are sequentially turned on within the horizontal effective scanning line period.

ΦADRES, φRESET and φRE
AD is a pulse signal supplied from the pulse selector 24 to the selected pixel row.
READ is activated during the horizontal retrace period during the signal accumulation operation and the signal read operation, respectively.
ES is not generated during the signal accumulation operation, and is activated during the horizontal retrace period during the signal read operation.

In this case, the pulse signal φADRES
Are generated so as to be intermittently activated twice so as to select and control the vertical selection line 6 of the same row twice during the horizontal retrace period in the signal read operation for the reason described later. You.

Next, the operation of the solid-state imaging device of FIG. 4 will be described with reference to FIGS.

The operation of the solid-state imaging device of FIG. 4 is basically the same as the operation of the solid-state imaging device of the conventional example 1 (FIG. 12) (FIG. 13), and therefore the description of the same operation is omitted. Hereinafter, different operations will be mainly described.

That is, in the solid-state imaging device shown in FIG. 4, when the electronic shutter operation is performed, the shift operation of the two vertical shift registers 21 and 22 for the electronic shutter is alternately started by the register switching control circuit 23 in field units. , By alternately selecting each output on a field-by-field basis,
The electronic shutter operation is alternately distributed to two vertical shift registers 21 and 22 dedicated to the electronic shutter in a field unit.

Thus, the field period tF in FIG.
As shown by a and tFb, even if the timing signal φES for controlling the signal accumulation time is input at a time interval shorter than the field period, the vertical shift registers 21 and 22 dedicated to the electronic shutter can operate simultaneously. .

In this case, the shift operation of one of the vertical shift registers 21 or 22 dedicated to the electronic shutter which has already started the shift operation by the timing signal φESR1 or φESR2 generated first controls the selection of all the pixel rows for reading. , The signal accumulation time of the selected pixel can be controlled by sequentially selecting the pixel row until the end of the pixel row for reading without being reset halfway.

In other words, it is possible to realize an electronic shutter function (continuous electronic shutter operation) for continuously changing the signal accumulation time in units of fields while keeping the read scanning time constant. In the same field, the signal accumulation time is the same for all the selected pixel rows.

As shown in FIG. 7, the horizontal period t
Pulse signals φRESET and φREAD are supplied to the HES to the nth pixel row selectively controlled by the output signal ESn of the nth shift stage of the vertical shift register for the electronic shutter, and the photodiodes in the nth pixel row The signal charge of the photodiode is reduced to zero by reading out the signal charge previously accumulated by the PD to the gate of the amplifying transistor.

In this case, since the pulse signal φADRES remains “L” and the vertical selection transistor remains off, the signal charges read to the gate of the amplification transistor are transmitted to the vertical signal line VLIN. No output.

Thereafter, during the signal read operation from the pixel row, φRESET is temporarily activated during the horizontal retrace period in the horizontal period tHRO, and then φADRES
Are activated, and φREAD is temporarily activated.

In this case, when φREAD is in an active state (“H” level), noise does not enter due to the influence of capacitive coupling between the photodiode and its peripheral wiring (φADRES wiring described later in this example). As described above, the φADRES pulse is temporarily deactivated (“L” level) so as to be in the same state as during the signal accumulation operation,
During the period when φADRES is inactive, the φREAS
D is temporarily activated.

The operation at the time of signal reading during the horizontal retrace period in the horizontal period tHRO will be described in detail. First, after resetting the gate electrode of the amplification transistor Tb to the reference potential by φRESET, φ
ADRES is activated (first time) to turn on the vertical selection transistors Ta of the n-th pixel row, and during this activation period, the pulse signal φCLP supplied to the noise canceller circuit is activated to clamp the black level.

The signal charge previously stored in the photodiode PD is read out to the gate of the amplification transistor Tb by activating φREAD during the period in which φADRES is inactive.

Then, φADRES is activated again (2
The vertical selection transistor Ta of the n-th pixel row is turned on again, and the amplification transistor Tb
The signal charge read to the gate of the vertical signal line VLIN
Output to

By the above operation, the horizontal period tHES
From the end of the active state ("H" level) of the read line drive signal φREAD in the horizontal period tHRO.
Is the signal accumulation time until the read line drive signal φREAD is activated.

FIG. 8A is a plan view showing a part of the unit cell in the image pickup area in order to explain the noise jump.

FIG. 8B is a cross-sectional view taken along the line aa ′ in FIG.

FIGS. 8 (c) and 8 (d) respectively show when φADRES in FIG. 8 (a) is at “L” level.
It indicates the potential in the substrate when φREAD is activated and the signal charge is read at the “H” level. Here, a case where the power supply potential is, for example, 3.3 V is shown.

8A and 8B, reference numeral 81 denotes a P-type well region formed in the surface layer of the silicon substrate, and reference numeral 82 denotes an element isolation region (for example, a LOCOS region) selectively formed in the surface layer of the substrate. It is. In the element area on the surface layer of the substrate,
An n-type region also serving as a cathode region of the photodiode and a source region of the read transistor Td and an n-type region (detection node DN) serving as a drain region of the read transistor Td are selectively formed.

A gate electrode (a part of the read line 4) made of polysilicon wiring is formed on the channel region of the read transistor Td with an insulating gate film interposed therebetween, and is located near the n-type region of the photodiode PD. A vertical selection line 5 made of polysilicon wiring is formed on the element isolation region 82.
And the reset line 7 are formed substantially in parallel.

In the reading operation of the present embodiment,
As shown in FIG. 8C, when the φADRES wiring adjacent to the photodiode PD is at the “L” level,
Is activated and the signal charge is read out, so that the coupling capacitance C existing between the photodiode PD and the φADRES wiring is
By a, the potential in the substrate below the photodiode PD is reduced by -VCa, and the accumulated charge QCa of the photodiode PD is read.

On the other hand, as shown in FIG.
When φREAD is activated and the signal charge is read when the φADRES wiring adjacent to the photodiode PD is at “H” level, the coupling capacitance Ca existing between the photodiode PD and φADRES wiring causes Since the potential is raised by + VCa (the noise jumps in), the accumulated charge QCa of the photodiode PD is not read out, and when the output signal of the solid-state imaging device is displayed on the screen of the image display device, a black signal is generated. Crushed and unsightly images.

In the solid-state imaging device according to the third embodiment, as in the solid-state imaging device according to the second embodiment, (1) the first to third dummy pixel rows are provided in the imaging region. And (2) three vertical selection circuits 2, 21, and 22
(3) Select a plurality of horizontal control line groups (4, 6, 7) based on the outputs of the vertical selection circuits 2, 21, and 22. When the pulse selector 24 generates the drive signal for the selective drive, during the activation period of the final stage output signal of the vertical selection circuit 2, the first dummy pixel row is selected and driven, and the second vertical selection circuit is driven. In the activation period of the final stage output signal 21, the second dummy pixel row is selected and driven, and in the activation period of the final stage output signal of the third vertical selection circuit 22, the third dummy pixel row is selected. It may be configured to be driven.

With such a configuration, the pulse selector 2
Reference numeral 4 designates one pixel row (three in total) corresponding to each output of the vertical shift register 2 for reading and the vertical shift registers 21 and 22 for two electronic shutters, so as to always select and drive the pixel rows. That is, since the selection load is always equal, it is possible to prevent the occurrence of horizontal stripes on the display screen due to the change in the readout level due to the magnitude of the selection load.

In the third embodiment, the description has been given of the case where the φADRES wiring is present as the peripheral wiring which causes the problem of blackout due to the capacitive coupling with the photodiode PD. However, the φRESET wiring or other wiring is used as the peripheral wiring. In the case where these wirings exist, there is a possibility that a problem of black signal collapse (black loss) due to capacitive coupling between these wirings and the photodiode PD may occur. Therefore, these wirings are also used in the third embodiment. φAD
What is necessary is just to control a level similarly to RES wiring.

That is, as described above, the photodiode P
The same voltage is applied to the peripheral wiring of the photodiode PD other than the read gate wiring adjacent to D during the activation period of the signal read pulse φREAD during the signal read operation and the activation period of the read pulse φREAD during the electronic shutter operation. By applying the voltage, control can be performed so that extra charge is not read out from the photodiode PD due to capacitive coupling between the photodiode PD and the peripheral wiring, and a reproduced image without so-called blackout can be obtained.

The present invention can be applied to a solid-state imaging device having an array of unit cells of 2 pixels / 1 unit as described in the following fourth embodiment in accordance with each of the above embodiments. .

<Fourth Embodiment> FIG. 9 shows two pixels / amplified CMOS solid-state imaging device according to a fourth embodiment.
3 shows an equivalent circuit of one unit cell. This C
Since the MOS solid-state imaging device can be configured in the same manner as the above-described embodiments except for the configuration of the unit cell, the configuration of the unit cell of 2 pixels / 1 unit will be mainly described below.

The unit cell 30 shown in FIG. 9 has two photodiodes 31a and 31b. The two photodiodes 31a and 31b are provided with a ground potential on each anode side and each cathode side on each anode side. Correspondingly, readout transistors (shutter gate transistors) 32a, 3
It is commonly connected to the gate of one amplification transistor 33 via 2b. The above two read transistors 32
read lines 4a, 4b
Is connected.

The amplification transistor 33 has one end connected to the vertical signal line VLIN, and the other end connected to the power supply line 9 via the vertical selection transistor 34 (that is, the amplification transistor 33 is connected to the source follower). The vertical selection line (address line) 6 is connected to the gate of the vertical selection transistor 34.

Further, one reset transistor 35 is connected between the gate of the amplification transistor 33 and the power supply line 9.
Are connected, and the reset line 7 is connected to the gate of the reset transistor 35.

The unit cells of 2 pixels / 1 unit having the above configuration are arranged in a two-dimensional matrix in the imaging area. The two read lines (the first read line 4a and the second read line 4b), the vertical selection line (address line) 6, and the reset line 7 are formed in a horizontal direction on the imaging area.
The vertical signal line VLIN and the power supply line 9 are formed vertically on the imaging area.

FIG. 10A shows an example of a plane pattern of a unit cell of 2 pixels / 1 unit shown in FIG.
FIG. 10B schematically shows a cross-sectional structure along the line.

In FIGS. 10A and 10B, 90 is N
P-well 91 is formed on the surface of the silicon substrate. An element isolation region (for example, a LOCOS region) 92, a cathode region of one photodiode 31a, and an N-type impurity region 9 serving as a source region of one read transistor 32a are provided in a surface layer portion of the P well 91.
31, an N-type impurity region 932 serving as a cathode region of the other photodiode 31b and a source region of the other read transistor 32b, and an SDG region of the NMOS transistor (the read transistors 32a, 3a in FIG.
Only the N-type impurity region 94 serving as a common drain of 2b is selectively formed.

Then, a silicon oxide film (gate insulating film) 95 is formed on the substrate surface, and the LOCOS region 92 is formed.
A field ion implantation region 96 is formed below the bottom surface of the substrate.

Reference numeral 97 denotes a polysilicon gate wiring partially including the gate electrode of the amplification transistor 33; 98, an N-type impurity region serving as a drain region of the amplification transistor 33 and a source region of the vertical selection transistor 34; This is an N-type impurity region serving as a source region.

Reference numeral 100 denotes a wiring connecting the source region 99 of the reset transistor 35, the gate wiring 97 of the amplification transistor 33, and the common drain region of the two read transistors 32a and 32b.

The read line 4a is connected to the read transistor 32
a polysilicon gate wiring partially including the gate electrode of a.
The read line 4b is formed of a polysilicon gate wiring partially including the gate electrode of the read transistor 32b.

The vertical selection line (address line) 6 is a polysilicon gate wiring partially including the gate electrode of the vertical selection transistor 34, and the reset line 7 is a reset transistor 35
Of polysilicon gate wiring including a part of the gate electrode.

Reference numeral 33a denotes a contact portion between the source region of the amplification transistor 33 and the vertical signal line VLIN, and reference numeral 34a denotes a drain region of the vertical selection transistor 34 and the power supply line 9.
Contact part. 97a is an amplification transistor 3
A contact portion between the gate wiring 97 and the wiring 100 of No. 3;
9a is a contact portion between the source region 99 of the reset transistor 35 and the wiring 100, 99b is a contact portion between the drain region of the reset transistor 35 and the power supply line 9,
100a is a contact portion between the wiring 100 and a common drain region of the two read transistors 32a and 32b.

The operation of the unit cell of 2 pixels / 1 unit having the above configuration is different from the operation of the unit cell of 1 pixel / 1 unit in that the five transistors are operated in a predetermined order and the signal charge is transferred from the photodiode. Is basically the same as that of the first embodiment, except that signal charges are read from the two photodiodes 31a and 31b at different timings.
That is, when reading out signal charges from one of the photodiodes 31a, an "H" level read signal is applied to the first read line 4a, and an "L" level read signal is applied to the second read line 4b. , The other photodiode 3
1b, an "H" level read signal is applied to the second read line 4b to read the signal charge from the first read line 4a.
Is kept at the "L" level read signal.

<Fifth Embodiment> In a CMOS solid-state imaging device having an array of unit cells of 2 pixels / 1 unit as described above, even if the above-mentioned electronic shutter function is not provided, When the signal charges are read from the two photodiodes 31a and 31b at different timings, the address line drive signal is intermittently driven twice as described above, so that the output signal is displayed on the screen of the image display device. It is possible to prevent the problem of occurrence of horizontal stripes on the display screen.

FIG. 11 is a timing waveform chart showing an example of a signal reading operation in a part of one field period in the CMOS solid-state imaging device according to the fifth embodiment.

In FIG. 11, φRESET, φADR
ES, φREAD1 or φREAD2 is a pulse signal supplied from the pulse selector to the selected pixel row,
Each of them is activated during the horizontal retrace period during the signal read operation, while φREAD1 and φREAD2 are supplied during different horizontal retrace periods.

Here, φREA is larger than the distance between the first read line 4a to which φREAD1 is supplied and the address line 6.
The distance between the second read line 4b to which D2 is supplied and the address line 6 is short, and the coupling between the second read line 4b and the address line 6 is larger than the coupling capacitance between the first read line 4a and the address line 6. Since the capacity is large, two photodiodes 31
A horizontal stripe on the display screen when the output signal is displayed on the screen of the image display device may be generated due to different influences on the signal charges read from the signals a and 31b.

However, φADRES is generated so as to be intermittently activated twice so as to select and control the address line 6 of the same row twice during the horizontal retrace period in the signal read operation. Since the signal φADRES is at the “L” level when the signal charges are read from the photodiodes 31a and 31b, respectively, the influence at the time of reading the signal charges is substantially equal, and the occurrence of the horizontal stripe on the display screen as described above. Problem can be prevented.

The present invention can be applied not only to the solid-state imaging devices of the above-described embodiments but also to a solid-state imaging device in which photoelectric conversion units are stacked.

[0176]

According to the solid-state imaging device according to the first aspect and the dependent claims, when the electronic shutter operation is performed, it is possible to prevent the load of the vertical shift register for reading and the vertical shift register for the electronic shutter from fluctuating. , Can suppress the horizontal line image noise generated on the output signal display screen,
A clear image with a high S / N can be obtained.

According to the solid-state imaging device of claim 3 and the dependent claims, the electronic shutter operation is alternately assigned in field units to two shift registers dedicated to the electronic shutter, so that the signal accumulation time in field units is obtained. , A variable electronic shutter operation (continuous electronic shutter operation) that changes the shutter speed. In this case, it is possible to prevent a difference in signal accumulation time between pixel rows according to the length of signal accumulation time, and to prevent image noise such as horizontal stripes on a display screen of an output signal.

In particular, according to the solid-state imaging device of the fourth aspect, a continuous electronic shutter operation can be realized similarly to the solid-state imaging device of the third aspect, and two solid-state imaging devices corresponding to two electronic shutter-dedicated vertical shift registers are provided. The dummy pixel row is provided and the three pixel rows selectively controlled by the shift register for reading and the two shift registers dedicated to the electronic shutter are always selected and driven, thereby eliminating the load fluctuation caused by the pixel row selection. In addition, it is possible to prevent the occurrence of horizontal streaks on the display screen.

According to the solid-state imaging device of the tenth aspect and the dependent claims, an electronic shutter operation can be realized, and the voltage applied to the peripheral wiring other than the read gate adjacent to the photodiode is reduced during the signal read operation. The same voltage is set in both the activation period of the read pulse signal and the activation period of the read pulse signal during the electronic shutter operation,
By suppressing the reading of the extra charges from the photodiode due to the capacitive coupling with the wiring, a reproduced image without blackening can be obtained.

According to the solid-state image pickup device of claim 12 and the dependent claims, when reading out the accumulated charges from the photoelectric conversion elements of two pixels in a unit cell of two pixels / one unit in the image pickup area, this reading is controlled. The voltage of another wiring adjacent to the wiring to be connected and present around the photoelectric conversion element is made substantially the same at the time of reading out each pixel. The influence of the wiring voltage is almost equal, and the problem of the occurrence of horizontal stripes on the display screen can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an equivalent circuit of a CMOS solid-state imaging device according to a second embodiment of the present invention;

3 is a timing chart showing how two electronic shutter vertical shift registers control the electronic shutter operation alternately in units of fields in the solid-state imaging device of FIG. 2;

FIG. 4 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a pulse selector in FIG. 4;

FIG. 6 is a timing waveform chart showing an operation example of the timing generation circuit, the first to third vertical shift registers, and the pulse selector in FIG. 4;

7 is a timing waveform chart showing an example of an electronic shutter operation within one field period in FIG.

8A and 8B are a plan view, a cross-sectional view, and a diagram showing a potential potential in a substrate, showing a part of a unit cell in an imaging region, for describing an operation of suppressing a noise jump in the electronic shutter operation shown in FIG.

FIG. 9 is a diagram illustrating an equivalent circuit of a unit cell of 2 pixels / 1 unit in the amplification type CMOS solid-state imaging device according to the fourth embodiment of the present invention.

10 is a diagram schematically illustrating an example of a planar pattern of a unit cell of 2 pixels / 1 unit in FIG. 9 and an example of a cross-sectional structure thereof.

FIG. 11 is a timing waveform chart showing an example of a signal reading operation within one field period in the CMOS solid-state imaging device according to the fifth embodiment of the present invention.

FIG. 12 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device of Conventional Example 1.

13 is a timing waveform chart illustrating an operation example of the CMOS solid-state imaging device in FIG.

14 is a timing waveform chart showing an operation example of the timing generation circuit, vertical shift register, and pulse selector in FIG.

FIG. 15 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device of Conventional Example 2.

16 is a diagram showing an example of row selection timing of two vertical shift registers in FIG.

17 changes the timing at which the electronic shutter vertical shift register performs row selection before the readout vertical shift register to change the signal accumulation time in the solid-state imaging device in FIG. FIG. 9 is a timing chart for explaining a problem in changing the length of time to be performed.

[Explanation of symbols]

 2 ... vertical shift register for reading, 3 ... horizontal shift register, 4 ... read line, 6 ... vertical selection line, 7 ... reset line, 9 ... power supply line, 10a ... timing generation circuit, 21, 22 ... for electronic shutter Vertical shift register, 23: switching control circuit, 24: vertical drive circuit (pulse selector), PD: photodiode, Ta: vertical selection transistor (row selection transistor), Tb: amplification transistor, Tc: reset transistor, Td: readout transistor , TH: horizontal selection transistor, VLIN: vertical signal line, HLIN: horizontal signal line.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yukio Endo 580-1 Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Semiconductor System Technology Center Co., Ltd. (72) Inventor Shinji Osawa Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa No. 580-1 Inside Toshiba Semiconductor System Technology Center (72) Inventor Yoriko Tanaka No. 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Semiconductor System Technology Center (72) Inventor Takeshi Arakawa Tokyo 3-3-9, Shimbashi, Minato-ku, Toshiba A-V E. Co., Ltd. (72) Inventor Yoshiyuki Tomizawa 3-3-1, Shimbashi, Minato-ku, Tokyo, Toshiba A-V E. Co., Ltd. (72) Inventor Makoto Hoshino 3-3-9, Shimbashi, Minato-ku, Tokyo Toshiba Abu E Co., Ltd. F-term (reference) 4M118 AA05 AB01 BA10 BA14 CA02 DD12 FA06 FA50 GA10 5C024 AA01 BA01 CA10 CA17 FA01 GA01 GA41 GA52 HA09 HA10 JA04

Claims (13)

[Claims] 1. A photoelectric conversion means for photoelectrically converting incident light to a pixel to accumulate charges, a reading means for reading the accumulated charges to a detection unit, an amplification means for amplifying the read charges, and a charge for the detection unit. A unit cell having reset means for resetting and vertical selection means for outputting a signal from the amplifying means is two-dimensionally arranged on a semiconductor substrate, and comprises a plurality of signal readout pixel rows and at least two dummy pixels. An imaging region having rows, a plurality of imaging regions provided in the horizontal direction corresponding to each pixel row in the imaging region, for transmitting a read driving signal for driving each reading unit of a unit cell of the corresponding pixel row. Read lines and horizontal lines corresponding to the respective pixel rows in the imaging area, and each vertical selection of the unit cells of the corresponding pixel rows. A plurality of vertical selection lines for transmitting a row selection drive signal for driving the means, and a read drive signal selectively supplied to the plurality of read lines to drive the read means; Vertical drive means for selectively supplying a row selection drive signal to the vertical selection lines to drive the vertical selection means, and reading means for each pixel row in the imaging region to obtain a desired signal accumulation timing and signal readout A row selecting means for controlling the vertical driving means so as to sequentially drive twice at a timing; and each unit of a pixel row provided corresponding to each pixel column in the imaging area and sequentially driven by the vertical driving means A plurality of vertical signal lines for transmitting signals output from the cells in a vertical direction, wherein the row selecting means includes a plurality of vertical signal lines. After controlling the signal readout from the unit cell of the pixel row for signal readout, selection control is performed to drive the first dummy pixel row of the two dummy pixel rows, and the plurality of the plurality of dummy pixel rows are controlled by the vertical drive unit. A solid-state imaging device comprising: controlling signal accumulation in a unit cell of a pixel row for signal reading; and selectively controlling a second dummy pixel row of the two dummy pixel rows to be driven. 2. The solid-state imaging device according to claim 1, wherein the row selection unit includes: a shift register for an electronic shutter for controlling a start period of signal accumulation in the unit cell; and a signal read from the unit cell. The first dummy pixel row is selectively controlled by the read shift register, and the second dummy pixel row is used for controlling the electronic shutter. The solid-state imaging device is selectively controlled by a shift register. 3. A photoelectric conversion means for photoelectrically converting incident light to a pixel to accumulate charges, a reading means for reading the accumulated charges to a detection unit, an amplification means for amplifying the read charges, and a charge for the detection unit. A unit cell having a reset unit for resetting and a vertical selection unit for outputting a signal from the amplification unit is two-dimensionally arranged on a semiconductor substrate, and an imaging region having a plurality of pixel rows; A plurality of read lines provided in the horizontal direction corresponding to each pixel row, for transmitting a read drive signal for driving each read unit of the unit cell of the corresponding pixel row, and a plurality of read lines in the imaging region. For transmitting a row selection drive signal provided in the horizontal direction corresponding to the pixel row and for driving each vertical selection unit of the unit cell of the corresponding pixel row. A plurality of vertical selection lines, and a read drive signal are selectively supplied to the plurality of read lines to drive the read unit, and a row selection drive signal is selectively supplied to the plurality of vertical selection lines. Vertical driving means for driving the vertical selection means, and the vertical driving means for sequentially driving the reading means of each pixel row in the imaging region twice at a desired signal accumulation timing and signal reading timing. A row selecting means for controlling, and a signal for outputting a signal output from each unit cell of a pixel row sequentially driven by the vertical driving means, the signal being provided in correspondence with each pixel column in the imaging region, in a vertical direction. A plurality of vertical signal lines, wherein the row selecting means drives the reading means of each pixel row at the signal reading timing by the vertical driving means. First means for causing the vertical drive means to drive the readout means of each pixel row at the signal accumulation timing.
A solid-state imaging device comprising: a plurality of second means. 4. The solid-state imaging device according to claim 3, wherein the imaging region further includes at least three dummy pixel rows in addition to the plurality of pixel rows for signal reading, and the row selection unit includes: Driving one dummy pixel row of the dummy pixel rows by the first means and driving the other two dummy pixel rows of the dummy pixel rows by the two second means; Characteristic solid-state imaging device. 5. The solid-state imaging device according to claim 3, wherein the row selection unit determines a signal accumulation timing within a period of one field cycle for each field corresponding to a cycle of a signal read timing of each pixel row. A solid-state imaging device characterized by changing. 6. The solid-state imaging device according to claim 5, wherein the at least two second units drive the read unit by relatively different signal accumulation timings with respect to the signal read timing. And a control operation of the vertical driving means by the second means is alternately switched every field. 7. The solid-state imaging device according to claim 5, wherein the first means of the row selecting means includes a read shift register for controlling a start period of signal reading from the unit cell, The second means of the row selecting means includes a shift register for a first electronic shutter for controlling a start period of signal accumulation in the unit cell in a first field period, and a shift register for the first field period. A solid-state imaging device, comprising: a second electronic shutter shift register for controlling a signal accumulation start period in the unit cell in a second field period repeated. 8. The solid-state imaging device according to claim 1, wherein the row selection unit is configured to drive the reading unit of each pixel row in the imaging region twice, and the photoelectric conversion unit is configured to perform the driving operation twice. A solid-state imaging device that controls the vertical driving unit so that the voltage of another wiring adjacent to the read line around the read line is substantially the same during the two driving operations. 9. The solid-state imaging device according to claim 8, wherein another wiring adjacent to the read line is the vertical selection line. 10. When reading stored charges from photoelectric conversion elements of a unit cell two-dimensionally arranged in an imaging region on a semiconductor substrate, wiring for controlling the reading is sequentially set at desired signal storage timing and signal read timing. A solid-state imaging device that performs an electronic shutter operation to output a signal read out at the signal read-out timing, wherein the other read-out control is performed adjacent to the wiring that controls the read-out and around the photoelectric conversion element. A solid-state imaging device, wherein a voltage of a wiring is made substantially the same at the signal accumulation timing and the signal readout timing. 11. The solid-state imaging device according to claim 1, wherein the unit cell includes one photodiode having a ground potential applied to an anode side, and one photodiode having a ground potential. One read transistor having one end connected to the cathode and a read line connected to the gate; and one amplifier having a gate connected to the other end of the read transistor and a vertical signal line connected to one end. A transistor, one vertical selection transistor having one end connected to the other end of the amplification transistor, and a gate connected to a vertical selection line; and one power supply connected to the other end of the vertical selection transistor. A reset transistor connected between a gate of the amplification transistor and the power supply line, and a reset line connected to the gate; Provided by the solid-state imaging device, characterized in that said one photodiode corresponds to one pixel. 12. A solid-state imaging device having an imaging region in which unit cells of 2 pixels / 1 unit are two-dimensionally arranged on a semiconductor substrate, wherein each of the photoelectric conversion elements of 2 pixels in the unit cell of the imaging region is A solid-state imaging device for reading out the stored charges, wherein the voltage of another wiring adjacent to the wiring for controlling the reading and present around the photoelectric conversion element is made substantially the same when reading out each pixel; apparatus. 13. The solid-state imaging device according to claim 1, wherein the unit cell includes two photodiodes each of which has a ground potential on each anode side, and the two photodiodes. Two read transistors each having one end connected to each of the cathode sides, and two read lines respectively connected to each gate, and two read transistors connected to the other end of the two read transistors, respectively. One amplifying transistor having a gate connected in common and one end connected to a vertical signal line, and one amplifying transistor having one end connected to the other end of the amplifying transistor and the gate connected to the vertical selection line A vertical selection transistor, one power supply line connected to the other end of the vertical selection transistor, and a power supply line connected between the gate of the amplification transistor and the power supply line. , The gate comprises a single reset transistor reset line is connected, the solid-state imaging device, characterized in that the two photodiodes corresponding to two pixels.