JPH04125960A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make the erroneous operation due to external noise to be hardly operated while cutting down the power consumption required for the maintenance of the normal state by a method wherein, during the normal operation time, the relative potentials similar to those of conventional semiconductor device are maintained while during the emergency operation time, the threshold value voltages of respective transistors are raised higher than those in the normal operation time by setting up the potentials of respective power supply lines. CONSTITUTION:During the normal operation time, the substrate potential of a P-channel MOS transistor 5 and the potential of a high potential power supply VDD are equalized while the substrate potential of an N-channel MOS transistor and the potential of low potential power supply are equalized. On the other hand, during the emergency operation time, the substrate potential of the P- channel MOS transistor 5, the potential of high potential power supply VDD, the potential of low potential power supply, the substrate potential of the N- channel MOS transistor 6 are made to be set up in this order. Through these procedures, the threshold values can be enhanced thereby enabling the power consumption to be cut down.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS digital semiconductor device, and particularly to a structure for applying a power supply and a substrate potential.

[Conventional technology]

In the conventional CMOS digital semiconductor device, as shown in FIG. 3, the substrate potential of the P-channel MOS transistor 23 is made equal to the potential (VDD) of the high potential power supply line 21, and
In addition, in order to make the substrate potential of the N-channel MOS transistor 24 equal to the potential (GND) of the low potential power supply line 22, these are always connected. Since a MOS transistor has a back bias characteristic in which the threshold voltage VT is determined by the potential difference between the source electrode and the substrate potential, in the structure of this conventional CMOS digital semiconductor device, the circuit operation is not performed during standby state etc. Even when the operating state was simply maintained, the threshold voltage VT of each MOS transistor was the same value as during operation.

[Problem to be solved by the invention]

In this way, conventional digital semiconductor devices are in a non-operating state in terms of their circuits, such as when in a standby state due to battery backup, etc., but there are cases in which they simply maintain an operating state and try to preserve the electrical circuit state during that period. Since the threshold voltage VT of the MOS transistor is the same value as in the operating state in terms of the circuit, the electrical state of the internal circuit is likely to change due to external noise, and the state of the electrical circuit that is intended to be maintained is likely to be destroyed. It had a structure. This has been a particular problem when using a backup voltage that is lower than the operating power supply voltage.

Also, the gate potential (VG
), the value of the drain current (ID) is determined by the difference between the threshold voltage VT of the MOS transistor, the drain voltage (VD), and the threshold voltage VT, so when saving the state, the power supply voltage is lowered to reduce current consumption. However, even if the drain voltage VD during state storage is lowered, unless the threshold voltage VT increases, the drain current ID cannot be reduced, and the current consumption during state storage cannot be reduced. This causes problems such as a shortened storage period, especially when a large number of MOS transistors are integrated in one device, and when a device with a finite amount of power such as a battery is used as a storage power source. .

[Means to solve the problem]

The digital semiconductor device of the present invention is a P-channel MOS
It has a structure that can independently supply the substrate potential of the transistor, the substrate potential of the N-channel MOS transistor, the potential of the high-potential power supply VDD, and the potential of the low-potential power supply. During normal operation, the substrate potential of the P-channel MOS transistor and the high-potential power supply are While making the potential of VDD equal to the potential of N
The substrate potential of the channel MOS transistor and the potential of the low potential power supply are made equal, and the P channel M
It has means for changing the substrate potential of the OS transistor, the potential of the high potential power supply VDD, the potential of the low potential power supply, and the substrate potential of the N-channel MOS transistor from high potential to low potential in this order.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a transistor-level equivalent circuit diagram of an embodiment of the present invention. Here, as part of the semiconductor device,
An inverter circuit is given as an example. 1 is a power supply line that supplies the substrate potential of the P-channel MOS transistor, 2 is a high-potential power supply (VDD) line of the semiconductor device, 3 is a low-potential power supply (GND, etc.) line of the semiconductor device, and 4 is the substrate of the N-channel MOS transistor. A power supply line that supplies potential, 5 is a P-channel MOS transistor, 6 is N
This is a channel MOS transistor.

The substrate terminal of the P-channel MOS transistor 5 is connected to the power supply line 1 that supplies the substrate potential of the P-channel MOS transistor, and the source terminal of the P-channel MOS transistor 5 is connected to the high-potential power supply line 2 of the semiconductor device. ing. The substrate terminal of the N-channel MOS transistor is connected to a power supply line 4 that supplies the substrate potential of the N-channel MOS transistor.
A source terminal of the transistor 6 is connected to the low potential power supply line 3 of the semiconductor device. As a result, this semiconductor device has a structure in which the potential of each power supply can be set independently.

FIG. 2 is a block diagram of an entire embodiment of the present invention.

10 is a semiconductor device, a part of which is shown in FIG. 1, 11 is an operational amplifier, 12 is an operational amplifier, 13 is a backup battery for preserving the electrical circuit state of the semiconductor device 10 when not in operation, 14 is a main power terminal, 15 is the main ground terminal. Main power terminal 14. The main ground terminal 15 and each terminal of the backup battery 13 and the semiconductor device IO
A diode for preventing backflow is connected between each power supply line VSP, VDD, GND, and VSN.

During normal operation, power is supplied to the main power supply terminal 14 and the main ground terminal 15 from the outside. A potential is applied to the VDD terminal of the semiconductor device IO from the main power supply terminal 14 through a diode. At this time, the same potential as the VDD terminal is applied to the VSP terminal of the semiconductor device 10 using the operational amplifier 11 as a voltage follower. A potential is applied to the GND terminal of the semiconductor device 10 from the main ground terminal 15 through a diode. At that time, the operational amplifier 12 is used as a voltage follower at the VSN terminal of the semiconductor device 10 to provide a G
The same potential as the ND terminal is applied.

During battery backup, the main power terminal 14 is open or has the same potential as the main ground terminal 15. At this time, the backup battery 13 is connected to the semiconductor device 10.
A potential is supplied to each power supply terminal. The backup battery 13 can supply four different potentials, starting from the highest: SP terminal, VDD terminal, GN terminal.
The potentials of the D terminal and the VSN terminal are set from high to low in that order. During this battery backup, the substrate potential of the P-channel MOS transistor (VSP
Since the potential of the terminal) becomes higher than the potential of the high potential power supply line (VDD terminal), the threshold voltage of the P-channel inter-channel O8 transistor becomes higher than during normal operation. Similarly, since the substrate potential (VSN terminal) of the N-channel MOS transistor becomes lower than the potential of the low-potential power supply line (GND terminal), the threshold voltage of the N-channel MOS transistor becomes higher than during normal operation. For this reason, the semiconductor device 1
The noise resistance of the internal circuit of 0 is increased, and the electrical circuit condition is maintained in good condition. At this time, the current consumption, which is thought to depend mainly on the leakage current leaking from the drain region to the semiconductor substrate, is a function of the difference between the potential of the high potential power supply VDD and the threshold voltage, so by increasing the threshold voltage, Current consumption can also be reduced.

〔Effect of the invention〕

As explained above, the present invention has a structure that can independently supply the substrate potential of the P-channel O8 transistor, the substrate potential of the N-channel MOS transistor, the VDD potential, and the GND potential, and in normal operation, the P-channel O8 transistor The substrate potential of the N-channel MOS transistor and the potential of the high-potential power supply VDD line are made the same, and the potential of the low-potential power supply line is made the same as the substrate potential of the N-channel MOS transistor and the potential of the low-potential power supply line is made the same.During non-operation, the electrical circuit state is simply maintained. Transistor substrate potential, high potential power supply V
By having a structure that supplies potentials such as the potential of the DD line, the low-potential power supply line potential, and the substrate potential of the N-channel MOS transistor, the electrical circuit can maintain the same potential relationship as conventional semiconductor devices during normal operation. When the state is simply saved during non-operation, the threshold voltage VT of each transistor is set higher than during operation by setting the potential of each power supply line to prevent malfunction due to external noise. Current value can be reduced.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram showing a part of an embodiment of the present invention at a transistor level, Fig. 2 is a block diagram showing an entire embodiment of the invention, and Fig. 3 shows a part of a conventional example at a transistor level. FIG. 1...Substrate power supply line of P-channel MOS transistor, 2...High potential power supply line of semiconductor device, 3...Low potential power supply line of semiconductor device,
4... N-channel MOS transistor substrate power supply line, 5... P-channel inter-channel O8 transistor, 6... N-channel MOS transistor, 10... semiconductor device , 11.12...
...Operational amplifier, 13...Backup batch') -14...Main power terminal, 15...
Main ground terminal. Agent Patent Attorney Shingi Uchihara

Claims (1)

[Claims] P-channel MOS transistor and N-channel MOS
a logic circuit formed on a semiconductor substrate using a transistor, a substrate potential of the P-channel MOS transistor, a substrate potential of the N-channel MOS transistor, a potential of a high potential power supply (VDD), and a potential of a low potential power supply (GND);
and, during normal operation, means for supplying a potential of
The substrate potential of the P-channel MOS transistor and the potential of the high-potential power supply are made equal, the substrate potential of the N-channel MOS transistor and the potential of the low-potential power supply are made equal, and the electrical circuit state of the logic circuit is means for storing the substrate potential of the P-channel MOS transistor, the potential of the high-potential power supply, the potential of the low-potential power supply, and the substrate potential of the N-channel MOS transistor from a higher potential to a lower potential in the order of non-operation; A semiconductor device characterized by having: