JPH0412574A - Manufacture of semiconductor pressure sensor - Google Patents

Abstract

PURPOSE:To stabilize element characteristics and improve yield, by determining the arrangement direction of a resistor by using crystal orientation shown by a reference pattern as a reference, and arranging and forming the resistor on a semiconductor substrate surface according to said arrangement direction. CONSTITUTION:The surface of a semiconductor substrate 1, on which a resistor is to be formed, is subjected to wet etching by using a mask 51 having a circular pattern 53, thereby forming a hexagonal pattern on the substrate 1 surface. Said pattern is used as the reference pattern. At least one strip type pattern 61 is formed at a part of the mask 51 on which a pattern of the resistor 19 is drawn. At least one side of the hexagon of the reference pattern formed on the substrate 1 and at least one side of the strip type pattern 61 are positioned in parallel, thereby aligning the masks. A resistor 19 is arranged and formed on the substrate 1 via the mask 51 wherein the pattern of the resistor 19 is drawn. Thereby the resistor 19 is formed in the desired crystallographic axis direction, element characteristics are stabilized, and yield can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor pressure sensor, and in particular,
Piezo resistance effect of a resistor when pressure is applied to the diaphragm
The present invention relates to a method of manufacturing a semiconductor pressure sensor that detects the pressure of a fluid such as blood or air by using t).

[Prior art] Pressure sensors are one of the basic sensors widely used in various industrial fields, and recently, diffusion-type semiconductor pressure sensors that apply semiconductor IC technology have been widely used. There is.

Semiconductor pressure sensors take advantage of the fact that when strain is applied to a semiconductor such as silicon, it causes a change in resistance that is approximately 100 times larger than that of a metal. It uses a resistor consisting of a diffusion type piezoresistance element (gauge resistor) made from 100% carbon dioxide, into which impurities are diffused by boron ion implantation, thermal diffusion, etc.

In order to improve the sensitivity to pressure, the back surface of the silicon single crystal plate on which the resistor is formed is hollowed out in a concave shape, and the thinned part is used as a diaphragm. This diaphragm acts as a strain body that converts applied pressure into strain according to the magnitude of the pressure, and works together with the resistor to convert pressure to strain and strain to electrical output.

That is, when pressure is applied, the diaphragm deforms and strain occurs in the resistor, which causes a stress change in the crystal of the resistor, which causes a change in the electron energy level. As a result, a large change in electrical resistance occurs in the resistor due to the piezoresistance effect, and a bridge output proportional to pressure is obtained.

Therefore, by connecting the signal output of this change in electrical resistance value to an external circuit, amplifying and measuring it, the applied pressure can be measured.

In the semiconductor pressure sensor described above, the resistor is connected in a bridge shape and converts the pressure into an electrical signal when pressure is applied to the diaphragm. However, the diaphragm is an n-type crystal parallel to the (110) plane of silicon. In the case of a plate, four p-type layers are usually used as a resistor so that the elongated direction is parallel to the (110) crystal axis direction with a large piezoresistance coefficient, and the impurity concentration is adjusted to the temperature of the piezoresistance coefficient. It is formed on a silicon single crystal plate while controlling the coefficient to be as small as possible.

Next, the relationship between the crystal direction and the substrate when a piezoresistive element is placed on a silicon substrate is shown in a table.

Note) Items marked with ○ can be used.

In this way, in order to obtain an excellent sensor, it is necessary to have an appropriate resistor arrangement that takes into account the crystal orientation dependence of the piezoresistance effect and the stress distribution within the diaphragm. It is determined by the plane orientation of the silicon substrate.

[Problems to be Solved by the Invention] As mentioned above, by using the crystal axis (110) of the p-type silicon substrate as the crystal plane orientation and maximizing the piezoresistance coefficient, it is possible to overcome pressure changes. Sensitivity can be improved.

However, in order to arrange a resistor pattern in a certain crystal orientation on a silicon substrate, conventionally this is done using an orientation flat previously provided on the silicon substrate as a reference; On the other hand, the accuracy is only within -1° to +1°.

For this reason, semiconductor pressure sensors obtained by forming resistors using this method have a problem in that the device characteristics vary widely and the yield of the device decreases.

Therefore, the present invention solves the above-mentioned problems, aligns the formation direction of a resistor on a silicon substrate with a desired crystal orientation with high accuracy, stabilizes the element characteristics of a semiconductor pressure sensor, and improves yield. The purpose is to

[Means for Solving the Problems] The present invention solves the above problems, in a method for manufacturing a semiconductor pressure sensor, when forming a resistor of a conductivity type opposite to that of the substrate on the surface of a semiconductor substrate of one conductivity type, a step of forming a reference pattern indicating a specific crystal orientation of the semiconductor substrate on the surface of the semiconductor substrate; a step of determining the arrangement direction of the resistor based on the crystal orientation indicated by the reference pattern; and the step of determining the direction in which the resistor is arranged. arranging and forming the resistor on the surface of the semiconductor substrate according to the determined arrangement direction;

The crystal orientation indicated by the formed reference pattern is -0.1° to +0° with respect to the actual crystal orientation of the semiconductor substrate.
．． Since it is within the range of 1°, the element characteristics can be stabilized compared to the conventional orientation flat (accuracy = 1° to +1°).

As the resistor, the aforementioned diffusion type piezoresistive element (gauge resistor) is used.

Specifically, the step of forming the reference pattern is performed by wet etching the semiconductor substrate using a mask having a circular pattern.

Further, it is preferable that the circular pattern is composed of a plurality of circular patterns arranged in rows and columns.

This is because it becomes easier to align the mask on which the resistor pattern is formed with respect to the silicon substrate.

Further, in the step of arranging and forming the resistor, at least one strip-shaped pattern is provided on a part of the mask on which the resistor pattern is drawn, and at least one side of the reference pattern formed on the semiconductor substrate and the strip at least one pattern of
A preferred method is to align the masks so that the sides are parallel to each other, and then arrange and form the resistor on the semiconductor substrate through a mask on which the pattern of the resistor is drawn.

This is because by performing mask alignment in this manner, the orientation can be accurately and quickly aligned, and the resistor can be placed at a desired position to form a film.

Further, the reference pattern shape specifically has a hexagonal shape.

[Function] During the manufacturing process of a semiconductor pressure sensor, when forming a resistor on the surface of a semiconductor substrate, first, the surface of the semiconductor substrate on which the resistor is to be formed is wet-etched using a mask having a circular pattern. A hexagonal pattern is formed.

This hexagonal pattern is used as a reference pattern.

Next, at least one strip pattern is provided on a part of the mask on which the pattern of the resistor is drawn, and at least one side of the hexagon of the reference pattern formed on the semiconductor substrate and at least one strip pattern Align the masks by positioning the sides parallel to each other.

Subsequently, when a resistor is formed on the semiconductor substrate through a mask on which the resistor pattern is drawn, the resistor is formed in a desired crystal axis direction.

[Example] Hereinafter, the manufacturing method of the present invention will be described in detail based on the illustrated example.

Note that FIGS. 1(a) to 1(w) show each manufacturing process when viewed from the cross-sectional direction of the silicon substrate l. Further, the thickness of the silicon substrate l is slightly omitted in the illustration.

(Step 1) First, as shown in Figure 1(a), n-type (1
10) Prepare a silicon substrate 1.

(Step 2) Next, as shown in the same figure (b),
Wet oxidation was carried out for 30 minutes at a temperature of
i02) Form 3.

(Step 3) Next, as shown in the same figure (C), a photoresist film 5 with a film thickness of 1.0 μm is formed on the surface of the silicon oxide film 3, and a circular shape is formed by ordinary photolithography for orientation alignment. A resist pattern having an open lower part is formed.

That is, after a glass mask on which a predetermined circular pattern has been drawn is aligned with the photoresist film 5, exposure and development are performed to transfer the circular pattern of the glass mask onto the photoresist film 5, and then in a nitrogen atmosphere for 90 seconds. Heat treatment (hard baking) is performed at 140±2°C.

An example of the above glass mask is shown in FIG.

In the figure, one glass mask 51 is formed with two circular pattern areas 53 indicated by diagonal lines.

Since this glass mask 51 is used only for forming a reference pattern indicating crystal orientation, the circular pattern area 53
No piezoresistance element pattern is formed in other areas.

Next, a corner part of the circular pattern area 53 is enlarged to form a third
As shown in the figure.

As shown in FIG. 3, in the circular pattern area 53, a plurality of circular patterns 55 are regularly arranged in rows and columns.

(Step 4) Next, as shown in FIG. 4(d), wet etching is performed using a buffered hydrofluoric acid (BHF) solution using the patterned photoresist film 5 as a mask, and the silicon oxide film 3 is etched with silicon. A circular opening 9 is formed that reaches the substrate l.

Subsequently, as shown in the same figure (e), the gas pressure was increased to 0.3To.
rr, and plasma ashing (ashing) is performed for 40 minutes under the conditions of high frequency power of 200 W, and the photoresist film 5 is removed.

Further, the silicon substrate 1 is washed with running ultrapure water five times for 5 minutes each time, and further dried by a spin drying method.

(Step 5) Next, as shown in FIG. 5(f), the silicon substrate 1 is wet-etched with hydrazine or KOH aqueous solution through the circular opening 9 using the silicon oxide film 3 as a mask to confirm the crystal orientation. A mark 11 is formed on the silicon substrate 1.

At this time, the reference pattern after etching formed on the silicon substrate 1, that is, the mark pattern 1 for confirming the crystal orientation.
1 becomes a hexagon as shown in FIG. 4 corresponding to each circular pattern.

In principle, each side of this hexagon is (11
0) and (111) planes, it is possible to determine the accurate crystal orientation on the silicon substrate.

In addition, if the circular patterns drawn on the glass mask are arranged in multiple rows and columns as described above, the hexagonal reference patterns formed on the silicon substrate 1 will also be arranged in multiple rows and columns, and each hexagonal When the sides in the same direction are connected, a straight line is formed, which makes it easier to align the mask for resistor formation later.

(Step 6) Subsequently, as shown in FIG. 6(g), wet etching is performed using a buffer fluoride (BHF) solution to completely remove the silicon oxide film 3.

Further, the silicon substrate 1 is washed with running ultrapure water five times for 5 minutes each time, and further dried by a spin dry method.

(Step 7) Next, as shown in the same figure (h), 1100
Wet oxidation was performed for 30 minutes at a temperature of
form 3.

In addition, in the drawings after FIG. 10H, the portion of the silicon substrate l where the resistor is formed is shown in an enlarged scale, so the formed crystal orientation confirmation mark 11 is not shown.

(Step 8) Subsequently, as shown in FIG. 4(i), a photoresist film 17 having a thickness of 1.0 μm and having the piezoresistive pattern 15 transferred thereto is formed on the upper surface of the silicon oxide film 13.

At this time, in this embodiment, the elongated direction of the piezoresistive pattern 15 transferred to the photoresist film 17 is parallel to each side in the (110) direction of the crystal orientation confirmation mark 11 formed on the silicon substrate 1. so that it becomes

A preferred method for doing so will be described below.

First, the upper surface of the silicon oxide film 13 is coated with a film thickness of 1.0 μm.
A photoresist film 17 is formed by coating.

Next, a photomask with a piezoresistive pattern drawn in advance is prepared.

An example is shown in FIG.

As shown in FIG. 5, the photomask 57 corresponds to the glass mask 51 described in FIG. 2, and has element regions arranged in 18 rows and 18 columns.

A piezoresistance pattern is drawn in each of these element areas, and each element area has a size of 2.7 x 2.7
It has an area of mm'.

Note that, for convenience, the piezoresistive pattern is not shown in FIG.

As shown by diagonal lines in FIG. 5, this photomask 57 has
Circular pattern area 53 formed on the glass mask 51
Two strip-shaped pattern areas 59 are formed at positions corresponding to .

Therefore, a piezoresistance pattern for ion implantation is formed in each region except for this strip pattern region 59.

Next, a corner portion of this strip-shaped pattern area 59 is partially enlarged and shown in FIG.

As shown in FIG. 6, in the strip pattern area 59,
A plurality of strip-shaped patterns 61 are regularly arranged.

The long side of each strip-like pattern 61 coincides with the direction of both opposing left and right sides of a hexagonal crystal orientation confirmation mark (reference pattern) formed on the silicon substrate l.

Therefore, in order to position the photomask 57 in a predetermined direction on the silicon substrate l, at least one side of the hexagonal crystal orientation confirmation mark 11 and at least one side of the strip pattern 61 must This is done by aligning it at .

By performing parallel alignment in this way, the photomask 5
The mask alignment with respect to the silicon substrate 1 of 7 becomes accurate, and as a result, the piezoresistive pattern is arranged in a desired crystal orientation with respect to the silicon substrate 1.

Although not shown, the piezoresistive pattern is arranged in a direction <110> that makes an angle of 180 degrees or a direction <111 that makes an angle of 35.3 degrees with respect to the longitudinal direction of the strip pattern 61.
＞ Formed.

The reason for arranging it like this is <110> or <11
This is because when the resistor is arranged in the 1> direction, the piezoresistance coefficient in the vertical direction becomes large.

Regarding the size, <111> is the largest, and <110> is the next largest.

A large longitudinal piezoresistance coefficient means that the longitudinal stress of the resistor becomes large. Therefore, the greater the stress, the greater the resistance change.

Next, the photoresist film 1
7 exposure and development, and further 90 degree exposure in a nitrogen atmosphere.
A heat treatment (hard baking) is performed at 140±2° C. for seconds to transfer the piezoresistive pattern of the photomask 57 onto the photoresist film 17.

In this way, the piezoresistive pattern transferred to the photoresist film 17 is arranged in the desired crystal orientation of the silicon substrate l.

(Step 9) Next, as shown in FIG. 6(j), using the patterned photoresist film 17 as a mask,
Wet etching is performed using a buffered hydrofluoric acid (BHF) solution to form a piezoresistive pattern 18 on the silicon oxide film 13 that reaches the silicon substrate 1.

Next, the gas pressure was 0.3 Torr, and the high frequency power was 200 W.
Plasma ashing (ashing) was performed for 40 minutes under the following conditions.
The photoresist film 17 is peeled off.

Further, the silicon substrate 1 is washed with running ultrapure water five times for 5 minutes each time, and further dried by a spin drying method.

(Step 10) Next, as shown in FIG. 5(k), using the silicon oxide film 13 on which the piezoresistive pattern 18 has been patterned as a mask, an acceleration voltage of 120 keV is applied.
Boron (B+ ions) are implanted at a dose of 1 x 10 ``''''/c rd to form a piezoresistance pattern 18 of the silicon oxide film 13 on the silicon substrate l.
A p-type diffusion layer having a conductivity type opposite to that of the silicon substrate 1 is formed in a portion corresponding to the p-type piezoresistor 19.

In addition to the above-mentioned ion implantation method, methods for implanting impurities include a thermal diffusion method and the like.

(Step 11) Subsequently, the silicon substrate 1 on which the piezoresistor 19 is formed is heated (annealed) for 30 minutes.

Furthermore, wet etching is performed using a buffered hydrofluoric acid (BHF) solution to remove the silicon oxide film 13.

Next, as shown in FIG.
form 1.

The piezoresistive pattern thus formed is shown in FIG.

In the figure, the blacked out portion is the piezoresistor 19.

FIG. 7 shows the state of the silicon substrate 1 viewed from above.

Further, the shaded portion is wiring 71 for electrically connecting the piezoresistor 19 to the outside.

This wiring 71 is connected to an acceleration voltage of 150 using a predetermined mask.
keV, dose 1xl 0181ona/
It is formed by implanting boron ions under C conditions.

Note that the following two methods can be considered for the outline of the process order of forming the piezoresistive portion and forming the wiring portion.

That is, in order: (1) forming an ion implantation pattern for the wiring section, (2) implanting ions for the wiring section, (2) annealing process, (2) removing the silicon oxide film, and (2) oxidizing again.

If the process consists of ■ forming a pattern for ion implantation of the piezoresistive part, ■ implanting ions for the piezoresistive part, ■ annealing process, and ■ re-oxidizing the process,
Alternatively, ■ a step of forming an ion implantation pattern for the wiring section; ■ a step of implanting ions for the wiring section; ■ a step of forming an ion implantation pattern for the piezoresistive section; ■ a step of implanting ions for the piezoresistive section 1) annealing process; 2) removing oxide film; and 2) oxidizing again.

On the other hand, in order to clarify the relationship between the piezoresistive portion 19 and the wiring 71, the rainbow resistance portion 19 located at the center of FIG. 7 is shown enlarged in FIG.

(Step 12) Furthermore, as shown in the same figure (m), silane (SiH,) = 6SCCM and nitrogen gas (
N2)=l 94SCCM was poured and a nitride film (S
iNx) 23.

Note that FIG. 7(m) is a sectional view taken along the line ■-■ in FIG. 7.

(Step 13) Next, as shown in the same figure (n), a photoresist film 25 with a film thickness of 1.0 μm is formed on the lower surface of the silicon substrate 1, and exposed and developed using a predetermined photomask. , and 140 sec for 90 seconds in a nitrogen atmosphere.
By performing heat treatment (hard baking) at ±2° C., a resist pattern for forming a diaphragm is formed.

(Step 14) Subsequently, as shown in FIG.
Using the pattern as a mask, apply buffered hydrofluoric acid (BHF).
Wet etching is performed using a liquid to selectively remove the silicon oxide film 21 formed on the lower surface of the silicon substrate 1. After that, the gas pressure is 0.3 Torr, and the high frequency power is 200 W.
Plasma ashing (ashing) was performed for 40 minutes under the following conditions.
Photoresist film 25 is removed.

(Step 15) Furthermore, as shown in the same figure (p'),
A photoresist film 27 with a film thickness of 1.0 μm is coated on the nitride film 23 formed on the upper surface of the silicon substrate l, and then exposed and developed using a predetermined photomask.
By performing heat treatment (hard baking) at 0±2° C. for 90 seconds, a contact hole pattern 29 for making electrical contact (ohmic contact) with the wiring 71 extending from the piezoresistor 19 is formed.

(Step 16) Next, as shown in FIG. 2(q), reactive ion etching (RIE) is performed using the photoresist film 27 as a mask to remove silicon oxide on the silicon substrate l on the nitride film 23. A contact hole opening 32 reaching the upper surface of the film 21 is formed.

Thereafter, plasma ashing (ashing) is performed for 40 minutes under the conditions of a gas pressure of 0.3 Torr and a high frequency power of 200 W, and the photoresist film 27 is peeled off.

Subsequently, it is washed with running ultrapure water five times for 5 minutes each time, and further dried by a spin dry method.

(Step 17) Next, as shown in the same figure (r), using the pattern of the silicon oxide film 21 formed on the lower surface of the silicon substrate l as a mask, the central part of the lower surface of the silicon substrate l is anisotropically etched using hydrazine. Etching (anisotropy: a phenomenon that occurs in materials that have been processed by rolling, drawing, extrusion, etc.)
This refers to a phenomenon in which mechanical properties, crystal orientation, etc. differ depending on the direction of the material. ), a cavity portion 30 is formed, and the film is thinned to form a diaphragm 31.

In FIG. 7, the outline of the cavity section 30 when seen through is shown by a broken line.

Further, in the upper part of FIG. 9, only the part indicated by the broken line in FIG. 7 is highlighted with a solid line, and in the lower part of FIG. The shape of the cavity portion 30 formed by etching will be clarified.

That is, the lowermost surface 301 of the cavity section has a hexagonal shape, while the upper surface 302 of the cavity section has a rectangular shape.

(Step 18) Subsequently, as shown in FIG. 5(S), wet etching is performed using a buffered hydrofluoric acid (BHF) solution using the patterned nitride film 23 as a mask.
A contact hole 33 is formed in the silicon oxide film 21 on the upper surface of the silicon substrate 1, and the diaphragm-forming silicon oxide film 21 remaining on the lower surface of the silicon substrate 1 is removed using a buffered hydrofluoric acid (BHF) solution.

Next, the silicon substrate 1 is washed with running ultrapure water five times for 5 minutes each time, and further dried by a spin drying method.

The contact hole 33 is indicated by diagonal lines in FIG.

The contact hole 33 functions as a portion that makes electrical contact (ohmic contact) between the aluminum pad 39 and the wiring 71, which will be formed in a later step.

(Step 19) Furthermore, as shown in (1) of the same figure, sputtering was performed for 10 minutes at a heating temperature of 230±30°C and 200W to form an aluminum (8β) film with a thickness of 1.5±0.1μm. 35 is formed by vapor deposition.

Subsequently, as shown in FIG. 3(u), a photoresist film 37 having a thickness of 1.0 μm is coated to form an electrode pattern.

Next, as shown in the same figure (V), after mask alignment,
After exposure and development, 140±
Heat treatment (hard baking) at 2° C. is performed for 90 seconds to form an electrode pattern.

(Step 20) Next, as shown in the same figure (W), an etching solution (H, PO4: HNO,: CH, C00H:
Aluminum pads 39 are formed by heating to about 40° C. and wet etching using the patterned photoresist film 37 as a mask.

Finally, plasma ashing (ashing) is performed for 40 minutes under the conditions of a pressure of 0.3 Torr and a high frequency power of 200 W to remove the photoresist film 37.

Next, in FIG. 11, the aluminum pad 39 is shown with diagonal lines.

The pressure sensor chip 81 created through the above steps is -
For example, as shown in FIG. 12, the outer peripheral portion 83 is fixed to a pedestal 85. At this time, the cavity part 30
functions as a reference pressure chamber and is maintained at a vacuum of, for example, 10 Torr or less.

The pedestal 85 is made of the same material as silicon, glass, etc. so as not to apply thermal strain to the pressure sensor chip 81, and is fixed to the stem 87 with a thickness sufficient to absorb the effects of thermal strain.

Further, the aluminum pad 39 on the surface of the pressure sensor chip 81 and the pin (terminal) 89 are connected with a gold wire 90.

Further, the cap 91 and the stem 87 are bonded together by electrical discharge machining, soldering, or the like.

A vibrator 93 is provided at the upper end of the cap 91, and the external pressure of the measurement medium is applied to the pressure sensor chip 8 through the vibrator 93.
It is applied from the top of 1.

When the diaphragm of the pressure sensor chip 81 changes in response to external pressure, the electrical resistance value of the piezoresistance formed on the diaphragm surface changes, so this change in electrical resistance value is output as an electrical signal and amplified and measured in an external circuit. As mentioned above, the external pressure can be measured by doing this.

Next, the principle of pressure measurement will be explained with reference to a circuit diagram.

First, a bridge circuit as shown in FIG. 14 is equimetrically formed between p-type piezoresistors A and C and p-type piezoresistors B and D of the silicon substrate shown in FIG. That will happen.

Therefore, by supplying a driving constant current i (generally several mA) to this bridge circuit, it is possible to detect the variable portion of the electrical resistance value generated in response to the pressure applied to the diaphragm as a voltage.

Note that resistors E and F are adjustment resistors for balancing the bridge circuit. When measuring voltage, short-circuit both.

Now, when current i is passed between terminals a and b of the circuit shown in FIG. 14, the output voltage V is expressed by the following equation.

The output voltage V is theoretically zero when there is no pressure difference between the two sides of the diaphragm, and when pressure is applied from the top side of the diaphragm and the diaphragm bends downward, the output voltage V is between the output terminals between resistors A and B. , a potential difference ΔV occurs between the output terminals of the resistors C and D.

This potential difference ΔV represents the variable amount of the electrical resistance value of the piezoresistor that occurs in response to pressure.

[Effects of the Invention] As detailed above, the present invention provides a method for manufacturing a semiconductor pressure sensor in which a resistor of a conductivity type opposite to that of the semiconductor substrate is formed on the surface of a semiconductor substrate of one conductivity type. a step of forming a reference pattern indicating a specific crystal orientation of the semiconductor substrate on the surface; a step of determining the arrangement direction of the resistor based on the crystal orientation indicated by the reference pattern; Since the resistor is arranged and formed on the surface of the semiconductor substrate according to the arrangement direction, the direction of arrangement and formation of the resistor on the silicon substrate is set in a desired crystal orientation. It has the excellent effect of stabilizing the element characteristics of the semiconductor pressure sensor and improving the yield.

Furthermore, the crystal orientation indicated by the formed reference pattern is -0.1° with respect to the actual crystal orientation of the semiconductor substrate.
Since it is within the range of ~ +0.16, the element characteristics can be stabilized compared to the conventional orientation flat (accuracy -1' to +1').

Furthermore, in the step of forming a resistor arrangement, at least one strip pattern is provided on a part of the mask on which the resistor pattern is drawn, and at least one side of the reference pattern formed on the semiconductor substrate is connected to the strip pattern. Few patterns (tomo 1)
After aligning the masks with the sides parallel to each other, the resistor is placed and formed on the semiconductor substrate through the mask on which the pattern of the resistor is drawn, thereby ensuring orientation alignment. Moreover, the resistor can be quickly disposed and formed at a desired position.

Moreover, since the reference pattern shape specifically has a hexagonal shape, alignment is easy.

Since a diffusion type piezoresistance element (gauge resistance) is used as the resistor, it has excellent responsiveness to pressure changes in the medium.

Further, the step of forming the reference pattern is performed by wet etching the semiconductor substrate using a mask having a circular pattern, thereby facilitating the step of forming the reference pattern.

Moreover, by making the circular pattern consist of a plurality of circular patterns arranged in rows and columns, it becomes easy to align the mask on which the resistor pattern is formed with respect to the silicon substrate.

[Brief explanation of the drawing]

FIGS. 1(a) to (w) are cross-sectional views showing each manufacturing process of a semiconductor pressure sensor according to the present invention, FIG. 2 is a view showing a glass mask used in an embodiment of the present invention, and FIG. is an enlarged view of a part of the circular pattern area of the glass mask shown in FIG. 2, FIG. FIG. 6 is an enlarged view of a part of the strip pattern area of the photomask shown in FIG. Figure 8 is an enlarged view of the piezoresistance pattern obtained in the example shown in Figure 7. Figure 9 is a diagram showing the cavity portion indicated by the broken line in Figure 7. Figure 1O. 11 is a diagram showing a contact hole obtained in an example of the present invention, FIG. 11 is a diagram showing an aluminum pad obtained in an example of the present invention, and FIG. 12 is a diagram showing a semiconductor pressure sensor according to the present invention. 13 is a sectional view, FIG. 13 is a layout diagram of a piezoresistor on a silicon substrate obtained in an example of the present invention, and FIG. 14 is an equivalent circuit diagram of a semiconductor pressure sensor of the present invention. (Explanation of symbols of main parts) 1...Silicon substrate 11...Crystal orientation confirmation mark 19...Piezo resistor 61...Strip pattern Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Figure 1 Figure rr-Ichigo], 4-1/57 "O-53 Odo-53" Figure 2 <110> 01 Figure 4 1111-<001> Figure 8 Figure 9 Figure 12

Claims (7)

[Claims] (1) In a method for manufacturing a semiconductor pressure sensor, when forming a resistor of a conductivity type opposite to that of the semiconductor substrate on the surface of a semiconductor substrate of one conductivity type, a specific crystal orientation of the semiconductor substrate is indicated on the surface of the semiconductor substrate. a step of forming a reference pattern, a step of determining the arrangement direction of the resistor based on the crystal orientation indicated by the reference pattern, and according to the determined arrangement direction,
1. A method of manufacturing a semiconductor pressure sensor, comprising the step of arranging and forming a resistor on a surface of a semiconductor substrate. (2) The crystal orientation indicated by the formed reference pattern is -0.1° with respect to the actual crystal orientation of the semiconductor substrate.
~+0. 2. The manufacturing method according to claim 1, wherein the angle is within a range of 1°. (3) The manufacturing method according to claim 1, wherein the resistor is a piezoresistor. (4) The manufacturing method according to claim 1, wherein the step of forming the reference pattern is performed by wet etching the semiconductor substrate using a mask having a circular pattern. (5) The manufacturing method according to claim 4, wherein the circular pattern is composed of a plurality of circular patterns arranged in rows and columns. (6) The step of arranging and forming the resistor includes providing at least one strip-shaped pattern on a part of the mask on which the resistor pattern is drawn, and forming at least one strip-shaped pattern on a part of the reference pattern formed on the semiconductor substrate.
A resistor is arranged and formed on a semiconductor substrate through a mask on which a pattern of the resistor is drawn, after mask alignment is performed by locating a side parallel to at least one side of the strip-shaped pattern. The manufacturing method according to item 1. (7) Claim 6, wherein the reference pattern has a hexagonal shape.
Manufacturing method described.