JPH0412560Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an automatic improvisational rhythm performance device that stores a plurality of rhythms with different beat numbers and randomly selects and plays the rhythms.

A device for automatically playing improvised rhythms has already been proposed by the inventor of the present application. FIG. 1 shows its configuration. N-bit shift registers 1, 1,
It is formed by exclusive OR circuits 1 and 2, and any two connection lines from each bit output terminal are connected to the exclusive OR circuits 1 and 2, and the output of the frequency dividing circuit 3 of the clock pulse generation circuit 2 is connected to the exclusive OR circuit 1 and 2. The random pulse generation circuit 1 is configured as a two-clock pulse. The generated random pulse is applied to the decoder 4 and specifies the address of the rhythm pattern generating circuit 5, so that the above constitutes a rhythm pattern specifying circuit. Since the pulses input to the decoder 4 are generated irregularly, the address specification is also irregular. Therefore, the selection of rhythms stored in the rhythm pattern generation circuit 5 becomes irregular, and an improvised rhythm is obtained via the sound source circuit 6, amplifier 7, and speaker 8.
Note that 9 is a sequential pulse generation circuit that sequentially generates pulses to the rhythm pattern generation circuit 5. In this device, the rhythm patterns to be selected are stored in equal length for each pattern, for example, in units of one measure, so it is possible to obtain rhythms that change little by little in units of one or two beats. It was not possible to play long bars with a specific rhythm and to select them randomly.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the above-mentioned drawbacks and to provide a device that can randomly select patterns of various lengths and automatically perform improvised rhythms. Embodiments of the present invention shown in the drawings will be described below. FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention, and is most different from FIG. 1 in that it includes a pulse counting circuit 10. Also, to simplify the explanation, the input to the decoder 4 is 1 bit, and the output is 2 terminals. The pulse counting circuit 10 operates to delay the clock pulse (second clock pulse) applied to the random pulse generating circuit 1 by the number of beats necessary for playing a predetermined rhythm pattern.
Therefore, shift register SR, AND circuit A1,
A2, OR circuits O1, O2, delay elements D1, D
2, D3, and a differentiating circuit DIF, and the first clock pulse from the frequency dividing circuit 3 is applied to the terminal Tc of the shift register SR. In order to maintain the operation of the rhythm pattern generation circuit 5 for, for example, 2 beats and 4 beats, 2 of the shift register SR is
Outputs are obtained from the bit-th terminal T2 and the fourth-bit terminal T4, and are applied to one terminal of each of the AND circuits A1 and A2. The outputs of the delay elements D1 and D2 are applied to the other terminals of the AND circuits A1 and A2, and the inputs of the delay elements are the output lines RS1 and RS1 of the decoder 4, respectively.
It has become RS2. And AND circuit A1,A
The outputs of 2 are combined in OR circuit O2, and one of the outputs of OR circuit O2 is sent to random pulse generation circuit 1.
, the other output is the delay element D3, the differential circuit DIF,
It is applied to each reset terminal of the shift register SR and the frequency divider circuit 3 via the OR circuit O1.

Next, the operation shown in FIG. 2 will be explained with reference to the time chart shown in FIG. Assume that the address designation signal "H" appears on the output line RS1 by the decoder 4 at time a. The signal on line RS1 is delayed by time τ ₁ by delay element D1 and applied to one input IN ₁₁ of AND circuit A1. Furthermore, after the time a when the address of the output line RS1 is specified (the time when the address specification of the output line RS2 is canceled), a pulse generated at the terminal Y is sent to the reset terminal of the shift register SR through the OR circuit O2 and the delay element. D3, differential circuit
The application reset operation is performed with a delay while passing through the DIF and OR circuit O1 (indicated as _τ3 in the diagram of the reset input RE in FIG. 2). The shift register SR performs a shift operation by using the DC Vdd as an "H" signal at the rising edge of P1 of the first clock pulse after application of this reset pulse. Since the second bit terminal T2 of the shift register SR is connected to the other input IN ₁₂ of the AND circuit A1, the second first clock pulse P is counted from the time when the shift register SR is reset.
1 rise time (time b), AND circuit A
Apply an “H” signal to the IN ₁₂ terminal of 1. AND circuit A1 performs a logical product operation and outputs “H”
applies the clock pulse P2 to the shift registers 1 and 1 via the OR circuit O2, and also applies the clock pulse P2 to the delay element D.
Since it is also applied to 3, it becomes a reset signal for the shift register SR again. Between times a and b, the rhythm pattern at the address specified by the output line RS1 is obtained from the rhythm pattern generation circuit 5.
With two clock pulses, ie, a quarter note as one beat, a rhythm is obtained between half notes.

At time b, clock pulse P2 is applied to shift register 1,1, so that the data shifted one stage causes decoder 4 to introduce a new addressing signal. How the output of the shift register changes depending on the clock pulse is irregular and cannot be predicted. Assume that the output line RS2 is selected as the signal of the decoder 4 due to this change.

The operation of the pulse counting circuit 10 after the output line RS2 is selected is similar to the operation when the output line RS1 is selected. However, shift register
The delay operation by SR is the 4th bit (time b in Figure 2).
equivalent). Note that at time c, "H" is generated at one input IN ₁₂ of AND circuit A1, but this is because the "H" signal of Vdd passes through the second bit as part of the operation of shift register SR. , and since no “H” signal is applied to input IN ₁₁ , AND circuit A1 outputs “H”
does not occur. Therefore, at time c, the reset signal is not fed back to the shift register SR, and the clock pulse P2 is not sent to the random pulse generating circuit 1.

Then, at time d, the AND circuit A2 operates and outputs the clock pulse P2, so that the shift registers 1, 1 of the random pulse generating circuit 1 are shifted by one stage. A new address is designated to the decoder 4, and FIG. 3 shows a case where the same output line SR2 is selected again. That is, the output line RS2 is selected again at time d by the clock pulse P2, and after the delay time τ ₃ of the delay element D3, the shift register SR is reset and starts counting again. When four first clock pulses P1 are introduced, the decoder 4 operates in the same manner as described above.

That is, assume that the output line RS2 changes to RS1 at time e. Note that the delay times τ ₁ , τ ₂ , τ ₃ in the delay elements D1, D2, D3 must be selected so that τ ₁ , τ ₂ >τ ₃ . When the rhythm pattern generation circuit moves from a long beat number (4 beats in this case) to a short beat number (2 beats in this case), if τ ₃ > τ ₁ is selected, τ ₃ is applied to terminal X at time f. A short pulse with a length of −τ ₁ is generated and applied to the random pulse generation circuit 1 in some cases.

The case where one rhythm pattern generation circuit 5 is provided has been described above, but if a rhythm pattern generator including a circuit that generates a normal rhythm pattern is driven by the same frequency dividing circuit, the normal rhythm pattern generation circuit By memorizing snare drums and top cymbals, and using the present invention only as an improvised rhythm part, the performance effect can be sufficiently improved. Also, decoder 4
It is also easy to increase the number of input and output lines, and it is sufficient to combine parts with the same number of beats using a nonlinear element such as a diode.

In this way, according to the present invention, different beat numbers,
Since different rhythm patterns are selected irregularly and automatically, the automatic rhythm performance device is highly improvisational, with, for example, 4-beat lengths and 2-beat lengths appearing alternately or one after the other. ing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an automatic rhythm playing device that has already been proposed, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart explaining the operation of FIG. 1... Random pulse generation circuit, 1, 1... Shift register, 1, 2... Exclusive OR circuit, 2
...Clock pulse generation circuit, 3...Frequency division circuit,
4...Decoder, 5...Rhythm pattern generation circuit,
6... Sound source circuit, 7... Amplifier, 8... Speaker, 9... Sequential pulse generation circuit, 10... Pulse counting circuit, P1... First clock pulse, P2...
...second clock pulse, SR...shift register,
A1, A2, A3...AND circuit, O1, O2...
...OR circuit, D1, D2, D3...delay element.

Claims (1)

[Claims for Utility Model Registration] A sequential pulse generation circuit 9 that divides the output pulse of the pulse generation circuit 2 by a frequency division circuit 3 and generates sequential pulses for reading rhythm patterns, and a plurality of rhythm patterns with different beat rates. remember,
a rhythm pattern generation circuit 5 from which required rhythm patterns are read out by the sequential pulses; and an address signal that designates a read address so as to switch the rhythm patterns read from the rhythm pattern generation circuit 5 in an irregular order. A pulse corresponding to one beat from among the divided pulses of the rhythm pattern designation circuits 1 and 4 and the sequential pulse generation circuit 9 is inputted as the first clock pulse, and an address signal from the rhythm pattern designation circuits (1 and 4) is inputted as the first clock pulse. controlled by
a pulse counting circuit 10 for applying a second clock pulse with a period corresponding to the number of beats necessary for playing a predetermined rhythm pattern to the pulse generating circuit 1 in the rhythm pattern specifying circuits 1 and 4; The circuit 10 operates on a counter (SR) into which the first clock pulse is input, an output signal from the counter (SR) corresponding to the required number of beats, and an address signal from the rhythm pattern designation circuits 1 and 4. 1. An automatic rhythm performance device comprising logical operation circuits A1, A2, and O2, each of which generates the second clock pulse.