JPH026480Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to an automatic rhythm performance device that performs rhythm performance according to a rhythm pattern.

Conventionally, in a rhythm box capable of performing rhythm performances, a rhythm pattern generation circuit that operates according to a clock signal of a predetermined frequency output from an oscillation circuit generates a plurality of rhythm sound sources corresponding to each percussion instrument sound. , pulses are sent at intervals synchronized with the timing of the clock signal according to a predetermined rhythm pattern, thereby driving the rhythm sound source to generate rhythm sound.

However, with this kind of device, the timing at which each percussion instrument sound is generated is synchronized with the clock signal, so the generated rhythm sounds are too precise in their timing and become monotonous. There were flaws.

This invention was developed against the background of the above-mentioned circumstances, and its purpose is to provide an automatic rhythm playing device that is capable of playing rhythms with changes similar to when playing a natural musical instrument.

This invention will be specifically explained below based on embodiments shown in the drawings. Figure 1 is an overall circuit diagram showing an automatic rhythm performance device such as a rhythm box.This automatic rhythm performance device includes a BD which stores rhythm patterns of predetermined percussion instrument sounds according to the type of rhythm such as rock and waltz. -ROM (read only memory) 1-1, SD-ROM1-2, ...SYM-
ROM1-N are provided. In this case, B.D.
-ROM1-1 is bass drum (BD), SD-ROM
1-2 is snare drum (SD), SYM-ROM1-
N is for storing cymbal (SYM) rhythm patterns for each type of rhythm.

In each ROM 1-1 to 1-N, each area for storing a predetermined rhythm pattern for each type of rhythm is designated by rhythm designation data sent from a CPU (central processing unit) not shown, and the corresponding selection circuit Address data input from 2-1 to 2-N designate each address in the designated area.

The selection circuits 2-1 to 2-N are configured as shown in FIG. In addition, each selection circuit 2-1 to 2-2
-N are constructed in the same way, one of which is illustrated, and the others are omitted. FIG. 2 shows details of the selection circuit 2-1.
As shown in FIG. 3, three-phase clock signals CLN, CLF, and CLB, which are out of phase with each other, are input to -1. In this case, each clock signal CLN,
CLF and CLB are rectangular pulse signals with the same period.
The signal CLF is a signal whose phase is slightly ahead of the signal CLN, and the signal CLB is a signal whose phase is slightly delayed from the signal CLN. Each clock signal is sent to the counter via the clock CLN through the transfer gate G ₁ and the OR gate 13, the clock signal CLF through the AND gate 14 and the OR gate 13, and the clock signal CLB through the AND gate 15 and the OR gate 13. 12 is input. The counter 12 counts the output of the OR gate 13 and outputs the obtained count data as address data of the ROM. For example, the coincidence circuit 12 receives numerical data corresponding to the number of operations of the external switch SW. Also supplied. Matching circuit 1
Reference numeral 6 detects a match between both input data, and when a match between both data is detected, a one-shot pulse match signal is outputted and applied to the set terminal S of the SR type flip-flop (SR-FF) 17. It will be done. The SR-FF 17 is reset in synchronization with the rising edge of the OR gate 13 by applying the output of the OR gate 13 to its reset terminal R, and its set output Q is sent to the transfer gate G ₁ via the inverter 18. , and are directly applied to transfer gates G ₂ and G ₃ as gate opening/closing signals, respectively. For transfer gates G ₁ to _{G 3} , the input gate opening/closing signal is “1”
It is said that it was opened at the time of. Then,
When the transfer gates G ₂ and G ₃ are opened, they provide the outputs of the corresponding external switches SW to the corresponding AND gates 14 and 15 as gate opening/closing signals, respectively.

According to the rhythm sound generator configured in this manner, in normal times when no coincidence is detected by the coincidence circuit 16, the SR-FF 17 is reset, so the output of the inverter 18 becomes "1" and the transfer gate _G1 is opened. has been done. Therefore, the counter 12 executes a counting operation of counting the clock signal CLN inputted via the transfer gate G ₁ and the OR gate 13. Thus, when the coincidence signal is output from the coincidence circuit 16,
SR-FF17 is set and transfer gate
G ₁ is opened. On the other hand, transfer gate G ₂ ,
G ₃ will be opened. Therefore, AND gate 1
4 and 15 are opened alternatively, so counter 1
2, a clock signal CLF or CLB is supplied instead of the clock signal CLN.
At the same time, the SR-FF 17 is reset by the output of the OR gate 13, so the transfer gate _G1 is opened again, the transfer gates _G2 and _G3 are closed, and the counter 12 receives the clock signal CLN. will be supplied. Therefore, the counting operation of the counter 12 is normally executed in synchronization with the clock signal CLN, but every time a coincidence signal is output from the coincidence circuit 16, the clock signal CLF whose phase is ahead of the clock signal CLN is activated.
Alternatively, it will be executed in synchronization with the delayed clock signal CLB. Therefore, by setting the numerical data of the external switch SW input to the matching circuit 16 to an arbitrary value, this arbitrary value and the counter 1
When the count value data outputted from the counter 2 match, the next count value data outputted from the counter 12 is outputted in synchronization with the clock signal CLF or CLB. As a result, some pulses of the rhythm sound signal created according to the output of the counter 12 are advanced or delayed.

FIG. 5 shows a case where the second pulse of the BD rhythm sound signal is delayed from the SD and SYM rhythm sound signals. FIG. 4 shows the contents of the rhythm pattern data at this time. In other words, when the first clock signal CLN is input to the counter 12, the count value data of this counter 12 is
BD-ROM 1-1, the value ``1'' at address ``0'' is read out, and this ``1'' output is input as a drive signal to the bass drum rhythm sound source circuit 8-1, and the bass drum sound is output to the mixer 9, Sound is emitted through the speaker 10. On the other hand, the count data of the counter 12 is input to the matching circuit 16, but no matching signal is output. At this time, the first clock signals CLF and CLB
is not output from the AND gates 14 and 15. Then, the second clock signal CLN is sent to the counter 12.
address ``1'' of the BD-ROM 1-1 is read out based on the count value data of the counter 12, but since the value of this address ``1'' is ``0'', no bass drum sound is emitted. At this time as well, the coincidence circuit 16 does not output a coincidence signal. Similarly, the second clock signals CLF and CLB are applied to the AND gate 14,
No output from 15. Next, the third clock signal
CLN is input to counter 12, and this counter 1
Address "2" of the BD-ROM 1-1 is read based on the count value data of "2", but since the value of address "2" is "0", no bass drum sound is emitted. Here, the third clock signals CLF and CLB are not output from the AND gates 14 and 15.

However, the count value of the counter 12 and the matching circuit 1
When the values match with 6, a match signal is output. As a result, SR-FF17 becomes set state, transfer gate G1 is opened, and transfer gate _G1 is opened.
G ₂ and G ₃ are developed. Then, the fourth clock signal CLB is input to the counter 12 via the AND gate 15 which is opened by the signal from the SW. Based on the count value data of this counter 12,
Address "3" of BD-ROM1-1 is read, and the read value "1" drives the bass drum rhythm sound source circuit 8-1, and the bass drum sound is emitted with a slight delay from the normal timing. be done. At this time, the output signal from the OR gate 13 causes SR−
FF17 is reset and transfer gate
G ₂ and G ₃ are closed, and transfer gate G ₁ is opened. Then, the bass drum sound is emitted at the normal timing by the fifth clock signal CLN. Further, the sixth clock signal CLN is input to the counter 12 and the address "5" of the BD-ROM 1-1 is read out, but since the read value is "0", no bass drum sound is emitted. After that, repeat the above operation. The generation timing of each percussion instrument sound in this case is as shown in FIG. 6, and only a part of the percussion instrument sounds on the BD are generated asynchronously with other percussion instrument sounds.

Note that the above embodiment uses three types of clock signals.
Although CLN, CLF, and CLB are used, four or more types of clock signals may be used.

As described in detail above, according to the automatic rhythm performance device according to the invention, the timing of producing rhythm sounds related to automatic rhythm performance is shifted only at an arbitrary beat, so that accents can be added to the rhythm, It is possible to obtain varying rhythm performance sounds.

[Brief explanation of the drawing]

1 to 6 show an embodiment of this invention, in which FIG. 1 is an overall circuit diagram of the automatic rhythm performance device, FIG. 2 is a diagram of the selection circuit shown in FIG. 1, and FIG. Figure 3 is an output waveform diagram of various clock signals, Figure 4 is a diagram showing an example of a rhythm pattern, Figure 5 is a timing chart of various rhythm sound signals, and Figure 6 is a diagram showing the output waveforms of various rhythm sound signals. FIG. 3 is a diagram showing the timing of generation of percussion instrument sounds. 1-1~1-N...ROM, 2-1~2-N...
...Selection circuit, 8-1 to 8-N...Rhythm sound source circuit, 9...Mixer, 10...Speaker, 11...
selection circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] An automatic rhythm performance device that performs rhythm performance according to a rhythm pattern, comprising: beat designation means for designating a beat related to the rhythm performance; and the beat designated by the beat designation means and the rhythm performance. a coincidence detecting means for detecting a coincidence with a beat related to the rhythm performance during the performance of the rhythm; and a control means controlling to shift the sounding timing of each rhythm sound related to the rhythm performance only when the beat is detected as a coincidence by the coincidence detecting means. An automatic rhythm performance device comprising: rhythm sound generation means for generating rhythm sounds related to the rhythm performance under control by the control means.