JPH04124071A - Ceramic circuit board and its production - Google Patents

Ceramic circuit board and its production

Info

Publication number
JPH04124071A
JPH04124071A JP24275690A JP24275690A JPH04124071A JP H04124071 A JPH04124071 A JP H04124071A JP 24275690 A JP24275690 A JP 24275690A JP 24275690 A JP24275690 A JP 24275690A JP H04124071 A JPH04124071 A JP H04124071A
Authority
JP
Japan
Prior art keywords
substrate
wiring
ceramic
ceramic substrate
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24275690A
Other languages
Japanese (ja)
Inventor
Koji Omote
孝司 表
Hirozo Yokoyama
横山 博三
Mineharu Tsukada
峰春 塚田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24275690A priority Critical patent/JPH04124071A/en
Publication of JPH04124071A publication Critical patent/JPH04124071A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Ceramic Products (AREA)

Abstract

PURPOSE:To prevent the generation of cracks by applying a wiring material comprising a specific metal to a ceramic substrate and into openings, press- sealing the ceramic substrate and the wiring material and calcining the combina tion. CONSTITUTION:A green sheet comprising a ceramic substrate material 1 such as Al2O3 or AlN is prepared, punched and laminated. Viaholes (openings) 3 having prescribed diameters are formed in the prepared substrate. After the formation of the viaholes 3, a wiring material 2 comprising a metal melting at the calcination temperature of the ceramic substrate material 1, such as Cu, Au, Ag, Al, Ni, Pd, Pt, Ag-Pt alloy or W-Cu alloy in the case of the Al2O3 substrate is wired on the ceramic substrate material 1 and in the viaholes. The wired substrate 1 is nipped with plates comprising the same material as the ceramic substrate material from both the sides of the substrate 1, press- sealed under a pressure of approximately 30-100MPa, heated in a N2 atmosphere for defatting, and subsequently calcined at a prescribed temperature to provide a ceramic circuit substrate free from cracks.

Description

【発明の詳細な説明】 〔概 要] セラミック回路基板及びその製造方法に係り、特に低い
電気抵抗で基板と強い密着力を有する配線材料を設けた
多層セラミック回路基板に関し、電気抵抗値を上げるこ
となく、基板−導体間の焼成収縮率の整合性をたかめク
ランクを防止したセラミック回路基板及びその製造方法
を擢供することを目的とし、 セラミック基板と、該セラミック基板の焼成温度で溶融
する金属からなる配線材料とを有すること及びセラミッ
ク基板材(1)上及び該セラミック基板材(1)に設け
られた開口部(3)に該セラミック基板材の焼成温度で
溶融する金属からなる配線材料(2)を施し、前記配線
材料(2)が形成されたセラミック基板材を加圧−密封
して焼成することを構成とする。
[Detailed Description of the Invention] [Summary] This invention relates to a ceramic circuit board and a method for manufacturing the same, and particularly to a multilayer ceramic circuit board provided with a wiring material having low electrical resistance and strong adhesion to the board, to increase the electrical resistance value. The purpose of the present invention is to provide a ceramic circuit board and a method for manufacturing the same that improves the consistency of the firing shrinkage rate between the board and the conductor and prevents cranking, and that the present invention is made of a ceramic circuit board and a metal that melts at the firing temperature of the ceramic board. and a wiring material (2) made of a metal that melts at the firing temperature of the ceramic substrate material (2) on the ceramic substrate material (1) and in the opening (3) provided in the ceramic substrate material (1). The ceramic substrate material on which the wiring material (2) is formed is pressurized, sealed, and fired.

〔産業上の利用分野〕[Industrial application field]

本発明はセラミック回路基板及びその製造方法に係り、
特に低い電気抵抗で基板と強い密着力を有する配線材料
を設けた多層セラミック回路基板に関するものである。
The present invention relates to a ceramic circuit board and a method for manufacturing the same,
In particular, the present invention relates to a multilayer ceramic circuit board provided with a wiring material having low electrical resistance and strong adhesion to the substrate.

近年のコンピュータシステムの高速化に伴い、多層セラ
ミンク回路基板が要求されている。多層セラミック回路
基板を作製するための必要な技術として回路配線の形成
技術がある。セラミック基板の配線材料として、低い電
気抵抗、基板との強い密着力等が要求され、また、層間
を接続するためのビア用導体として、基板−導体間のク
ラックを防止するために基板と導体の焼成収縮率を一致
させる必要がある。
As computer systems become faster in recent years, multilayer ceramic circuit boards are required. A technique for forming circuit wiring is a necessary technique for producing a multilayer ceramic circuit board. As a wiring material for ceramic substrates, it is required to have low electrical resistance and strong adhesion to the substrate, and as a conductor for vias to connect layers, it is necessary to bond the substrate and conductor to prevent cracks between the substrate and the conductor. It is necessary to match the firing shrinkage rate.

[従来の技術〕 現在セラミック回路基板の導体材料は、回路基板の焼成
温度で焼結が行われる金属が同時焼成に通していると言
われている。しかし、セラミックと金属の焼成過程の収
縮モードは、一致していないので基板−導体間に収縮差
が生しる。そのため、基板−導体間にはクランクが生し
基板と導体間の密着力が低下し、導通不良の原因となる
[Prior Art] Currently, it is said that the conductor material of a ceramic circuit board is a metal that is sintered at the firing temperature of the circuit board through simultaneous firing. However, since the shrinkage modes of the ceramic and metal during the firing process do not match, a difference in shrinkage occurs between the substrate and the conductor. Therefore, a crank is formed between the board and the conductor, reducing the adhesion between the board and the conductor, causing poor conduction.

従来技術のセラミック基板の作製方法として、第3図に
示すようにセラミック基板lの焼成温度で焼結が始まる
金属を使用し、導体中にセラミックス基板と同組成の粉
末を添加して基板1−ビア3間の焼成過程の収縮率差を
緩和しクラック防止方法がある。しかし、この方法では
基板−導体間の密着力を上げるために、導体中に絶縁物
が混入されるため、電気抵抗値が上がってしまう。さら
に、Cu、Au等の低抵抗金属は、融点が1200°C
以下なので1600°C以上の高温焼成のセラミンク(
II2N、 Ap2os)に使用すると導体は溶融し球
状になる。そこで、高温焼成のセラミックに使用できる
導体がW、Mo等と限られてくるので、導体の低抵抗化
、焼成収縮率の調整等が困難である。
As shown in FIG. 3, a conventional method for manufacturing a ceramic substrate uses a metal that starts sintering at the firing temperature of the ceramic substrate 1, and adds powder of the same composition as the ceramic substrate into the conductor to form the substrate 1- There is a method for preventing cracks by alleviating the shrinkage rate difference between the vias 3 during the firing process. However, in this method, an insulator is mixed into the conductor in order to increase the adhesion between the substrate and the conductor, resulting in an increase in electrical resistance. Furthermore, low resistance metals such as Cu and Au have melting points of 1200°C.
Ceramink fired at a high temperature of 1600°C or higher (
II2N, Ap2os), the conductor melts and becomes spherical. Therefore, since the conductors that can be used in high-temperature fired ceramics are limited to W, Mo, etc., it is difficult to reduce the resistance of the conductor and adjust the firing shrinkage rate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従って本発明は電気抵抗値を上げることなく、基板−導
体間の焼成収縮率の整合性をたかめクランクを防止した
セラミック回路基板及びその製造方法を提供することを
目的とする。
Accordingly, an object of the present invention is to provide a ceramic circuit board and a method for manufacturing the same, which prevent cranking by improving the consistency of firing shrinkage between the board and the conductor without increasing the electrical resistance value.

更に本発明は高温焼成セラミック(A7!N、 Al2
ZO3)に使用する導体の低抵抗化を図ったセラミック
回路基板及びその製造方法を提供することを目的とする
Furthermore, the present invention provides high-temperature fired ceramics (A7!N, Al2
An object of the present invention is to provide a ceramic circuit board in which the resistance of a conductor used in ZO3) is reduced, and a method for manufacturing the same.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は、本発明によればセラミック基板(1)と、
該セラミック基板(1)の焼成温度で溶融する金属から
なる配線材料(2)とを有することを特徴とするセラミ
ック回路基板によって解決される。
According to the present invention, the above problem can be solved by a ceramic substrate (1),
The problem is solved by a ceramic circuit board characterized by having a wiring material (2) made of metal that melts at the firing temperature of the ceramic circuit board (1).

本発明で用いるセラミック基板としてガラスセラミック
複合材、アルミナ(A 1. z(h)、マグネシア(
MgO) 、ジルコニア(ZrO□)あるいは窒化アル
ミニウム(A f N)が好ましい。
Ceramic substrates used in the present invention include glass-ceramic composites, alumina (A1.z(h), magnesia (
Preferred are MgO), zirconia (ZrO□), or aluminum nitride (A f N).

またセラミック基板をガラスセラミック複合材基板とし
た場合の配線材料として銅(Cu)、金(Au)、アル
ミニウムあるいはCu 、 Au 、 Ag、又は八!
を主成分としたW、Mo、Ni、Pd又はptとの合金
が好ましい。
In addition, when the ceramic substrate is a glass ceramic composite substrate, the wiring material may be copper (Cu), gold (Au), aluminum, Cu, Au, Ag, or 8!
An alloy containing W, Mo, Ni, Pd, or pt as a main component is preferable.

またセラミック基板をアルミナ基板とした場合の配線材
料としてCu、Au、  Af 、Ni、Pd、Ptあ
るいはCu、Au、Ag、  Al 、Ni、Pd又は
ptを主成分としたW、又はMoとの合金が好ましい。
In addition, when the ceramic substrate is used as an alumina substrate, wiring materials such as Cu, Au, Af, Ni, Pd, Pt, or alloys with W or Mo whose main components are Cu, Au, Ag, Al, Ni, Pd, or pt are used. is preferred.

更にセラミック基板をマグネシア基板のあるいはジルコ
ニア基板とした場合の配線材料として八〇。
Furthermore, it is 80% as a wiring material when the ceramic substrate is a magnesia substrate or a zirconia substrate.

Pd 、 PLあるいはAu 、 Ag 、 Pd又は
PLを主成分とした合金が好ましい。
Pd, PL, or an alloy containing Au, Ag, Pd, or PL as a main component is preferable.

またセラミック基板を窒化アルミニウム基板とした場合
の配線材料としてCu、Au、  Af 、Ni、Pd
In addition, when the ceramic substrate is an aluminum nitride substrate, wiring materials such as Cu, Au, Af, Ni, and Pd can be used.
.

PtあるいはCu、Au、Ag、  Al 、Ni、P
d又はptを主成分としたW又はMoとの合金が好まし
い。
Pt or Cu, Au, Ag, Al, Ni, P
An alloy containing d or pt as a main component and W or Mo is preferable.

本発明では配線材料がセラミック内に密封して焼成され
、しかも回路配線はワイヤーで形成されるのが望ましい
In the present invention, it is preferable that the wiring material is sealed and fired within the ceramic, and that the circuit wiring is formed of wire.

更に上記課題は本発明によればセラミンク基板材(1)
上及び該セラミック基板材(1)に設けられた開口部(
3)に該セラミック基板材の焼成温度で溶融する金属か
らなる配線材料(2)を施し、配線材料(2)が形成さ
れたセラミック基板材を加圧−密封して焼成することを
特徴とするセラミック回路基板の製造方法によって解決
される。
Furthermore, the above problem can be solved by the ceramic substrate material (1) according to the present invention.
an opening (
3) is characterized by applying a wiring material (2) made of a metal that melts at the firing temperature of the ceramic substrate material, pressurizing and sealing the ceramic substrate material on which the wiring material (2) has been formed, and firing it. The problem is solved by a method of manufacturing a ceramic circuit board.

本発明では配線材料がワイヤー状を有することが好まし
く、また上記加圧−密封処理がセラミック基板材とは\
”同質の材料で該セラミック基板材を上下から挾むよう
にして行うことが好ましい。
In the present invention, it is preferable that the wiring material has a wire shape, and the above pressure-sealing treatment is different from the ceramic substrate material.
``It is preferable to sandwich the ceramic substrate material from above and below using the same material.

その加圧圧力は30MPa〜100MPa程度が好まし
い。
The pressurizing pressure is preferably about 30 MPa to 100 MPa.

(作 用〕 本発明によればセラミック焼成温度で溶融する金属を配
線材料に使用し、ワイヤーで配線を施し、セラミック内
に密封することにより、基板−導体間クランクを防止す
ることができる。さらに、導体を基板内に密封している
ため、高温(1600’C以上)で焼成を行っても導体
の球状変形は生じない。
(Function) According to the present invention, cranking between the substrate and the conductor can be prevented by using a metal that melts at the ceramic firing temperature as the wiring material, wiring with wire, and sealing it inside the ceramic. Since the conductor is sealed within the substrate, spherical deformation of the conductor does not occur even if the conductor is fired at a high temperature (1600'C or higher).

そのため、高温域(1600”C以上)焼成のセラミッ
ク(Ml!N、 1203)に低抵抗金属の配線を施す
ことができる。
Therefore, low-resistance metal wiring can be applied to ceramic (Ml!N, 1203) fired in a high temperature range (1600''C or higher).

〔実施例〕〔Example〕

以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.

第1図は、本発明に係るグリーンシート(セラミック基
板材)に導体線2を配線し、導体線でビアを形成した物
の斜視図及びAの部分拡大間であり、第2図(a)及び
(b)は無垢グリーンシートでビア形成グリーンシート
を密封した積層体を示す断面図及びBの部分拡大図であ
る。
FIG. 1 is a perspective view of a green sheet (ceramic substrate material) according to the present invention, in which conductor wires 2 are wired and vias are formed with the conductor wires, and a partially enlarged view of A, and FIG. 2(a) and (b) is a sectional view showing a laminate in which a via-forming green sheet is sealed with a solid green sheet, and a partially enlarged view of B.

本発明ではセラミック基板1としてアルミナ基板を用い
、ワイヤー2及びビア材3aとしてアルミナ基板(グリ
ーンシート)の焼成温度(約1600”C)で溶融する
Cu、Au等が用いられている。
In the present invention, an alumina substrate is used as the ceramic substrate 1, and Cu, Au, etc., which melt at the firing temperature of the alumina substrate (green sheet) (approximately 1600''C), are used as the wires 2 and the via material 3a.

第2図に示すようにグリーンシートに配線材料を設けら
れたセラミック基板材は同質の密封用セラミックス6に
よって上下に挾まれさらに積層金型7を介して加圧され
る。4はデラミである。
As shown in FIG. 2, a ceramic substrate material in which wiring material is provided on a green sheet is sandwiched vertically by sealing ceramics 6 of the same quality, and further pressurized through a laminated mold 7. 4 is Delami.

実施例1 第1表のNa3に示す組成のセラミック基板材1である
グリーンシート(密度1.60g/cffl、厚さ30
0 tna )をドクターブレード法で作製した。この
グリーンシートを口90mmに打抜き、6枚1組で積層
(60°C、5MPa)を行った。積層体を第4図に示
すようにドリルでφ250μのピアホール3を10個形
成した。次に、第2表に示す市販の導体線2(φ250
,1111)の充填を行った。ビア形成後、積層体に市
販の導体線(φ250趣)を使用し配線を施した。配線
後、積層体の上下を4枚の上記と同質のグリーンシート
で挟み込み積層(60℃、 50?1Pa)を行い、N
2中800°C,5hで脱脂し、第3表随aの条件で焼
成を行った。焼成後の配線の体積抵抗率および基板−ビ
ア間のクシツクの有無を第4表に示す。
Example 1 A green sheet (density 1.60 g/cffl, thickness 30
0 tna) was prepared by the doctor blade method. This green sheet was punched out to have an opening of 90 mm, and a set of 6 sheets were laminated (60°C, 5 MPa). As shown in FIG. 4, ten pier holes 3 having a diameter of 250 μm were formed in the laminate using a drill. Next, commercially available conductor wire 2 (φ250
, 1111). After forming the vias, wiring was applied to the laminate using commercially available conductor wires (φ250 diameter). After wiring, the top and bottom of the laminate were sandwiched between four green sheets of the same quality as above, and laminated (60℃, 50?1Pa).
The sample was degreased at 800°C for 5 hours in No. 2, and fired under the conditions shown in Table 3, Item a. Table 4 shows the volume resistivity of the wiring after firing and the presence or absence of wrinkles between the substrate and the via.

実施例2 第1表No、bに示す組成のグリーンシート1 (密度
1.70g/d、厚さ300庫)をドクターブレード法
で作製した。このグリーンシートを口90Il111に
打抜き、6枚1組で積層(60℃、5MPa)を行った
Example 2 Green sheet 1 (density 1.70 g/d, thickness 300 mm) having the composition shown in Table 1 No. b was produced by a doctor blade method. This green sheet was punched out into a hole of 90Il111 and laminated (60°C, 5MPa) into a set of 6 sheets.

積層体を第4図に示すようにドリルでφ250pのピア
ホール3を10個形成した。次に、第2表に示す市販の
導体線2(φ250趨)の充填を行った。
As shown in FIG. 4, ten pier holes 3 of φ250p were formed in the laminate using a drill. Next, commercially available conductor wire 2 (φ250) shown in Table 2 was filled.

ビア形成後、積層体に市販の導体線(φ250IzII
l)を使用し配線を施した。配線後、積層体の上下を4
枚の上記と同質のグリーンシートで挟み込み積層(60
℃、 50MPa)を行い、湿潤N、中800°C25
hで脱脂し、第3表bbの条件で焼成を行った。
After forming the vias, a commercially available conductor wire (φ250IzII
1) was used for wiring. After wiring, the top and bottom of the laminate are
Sandwiched and laminated with green sheets of the same quality as above (60
℃, 50MPa) and wet N, 800℃ in 25
It was degreased at 100 m and then fired under the conditions shown in Table 3 bb.

焼成後の配線の体積抵抗率および基板−ビア間のクラッ
クの有無を第4表に示す。
Table 4 shows the volume resistivity of the wiring after firing and the presence or absence of cracks between the substrate and vias.

実施例3 第1表Na cに示す組成のグリーンシート1(密度1
.60g/d、厚さ300Inn)をドクターブレード
法で作製した。このグリーンシートを口90mmに打抜
き、6枚1組で積層(60°C、5MPa)を行った。
Example 3 Green sheet 1 having the composition shown in Table 1 (density 1
.. 60 g/d, thickness 300 Inn) was produced by the doctor blade method. This green sheet was punched out to have an opening of 90 mm, and a set of 6 sheets were laminated (60°C, 5 MPa).

積層体を第4図に示すようにドリルで≠250tnaの
ピアホール3を10個形成した。次に、第2表に示す市
販の導体線2(φ250p#A)の充填を行った。
As shown in FIG. 4, ten pier holes 3 of ≠250 tna were formed in the laminate using a drill. Next, commercially available conductor wire 2 (φ250p#A) shown in Table 2 was filled.

ビア形成後、積層体に市販の導体線(φ250.m)を
使用し配線を施した。配線後、積層体の上下を4枚の上
記と同質のグリーンシートで挟み込み積層(60°C、
50MPa)を行い、大気中800°C,5hで脱脂し
、第3表N[lCの条件で焼成を行った。焼成後の配線
の体積抵抗率および基板−ビア間のクラックの有無を第
4表に示す。
After forming the vias, wiring was applied to the laminate using commercially available conductor wires (φ250.m). After wiring, the top and bottom of the laminate were sandwiched between four green sheets of the same quality as above and laminated (60°C,
50 MPa), degreased in the air at 800°C for 5 hours, and fired under the conditions of N[lC in Table 3. Table 4 shows the volume resistivity of the wiring after firing and the presence or absence of cracks between the substrate and vias.

実施例4 第1表Nαdに示す組成のグリーンシート1 (密度1
.60g/cd、厚さ300B)をドクターブレード法
で作製した。このグリーンシートを口90mに打抜き、
6枚1組で積層(60″C、5MPa)を行った。
Example 4 Green sheet 1 having the composition shown in Table 1 Nαd (density 1
.. 60g/cd, thickness 300B) was produced by the doctor blade method. This green sheet was punched out to a width of 90m,
A set of 6 sheets was laminated (60″C, 5 MPa).

積層体を第4図に示すようにドリルでφ250−のピア
ホール3を10個形成した。次に、第2表に示す市販の
導体線2(φ250μ)の充填を行った。
As shown in FIG. 4, ten pier holes 3 having a diameter of 250 mm were formed in the laminate using a drill. Next, commercially available conductor wire 2 (φ250μ) shown in Table 2 was filled.

ビア形成後、積層体に市販の導体線(φ250μ)を使
用し配線を施した。配線後、積層体の上下を4枚の上記
と同質のグリーンシートで挟み込み積層(60℃、 5
0MPa)を行い、大気中800℃、5hで脱脂し、第
3表Nl1dの条件で焼成を行った。焼成後の配線の体
積抵抗率および基板−ビア間のクランクの有無を第4表
に示す。また、第5表にCuを配線した試料の結果を示
す。
After forming the vias, the laminate was wired using commercially available conductor wires (φ250μ). After wiring, the top and bottom of the laminate were sandwiched between four green sheets of the same quality as above and laminated (60℃, 5
0 MPa), degreased in the air at 800° C. for 5 hours, and fired under the conditions shown in Table 3 Nl1d. Table 4 shows the volume resistivity of the wiring after firing and the presence or absence of a crank between the substrate and the via. Further, Table 5 shows the results of samples with Cu wiring.

実施例5 第1表No、 eに示す組成のグリーンシート1 (密
度1.70g/d、厚さ300趨)をドクターブレード
法で作製した。このグリーンシートを口90mnに打抜
き、6枚1組で積層(60°C、5MPa)を行った。
Example 5 Green sheet 1 (density 1.70 g/d, thickness 300 mm) having the composition shown in Table 1 No. e was produced by a doctor blade method. This green sheet was punched out to a width of 90 mm and laminated (60°C, 5 MPa) into a set of 6 sheets.

積層体を第4図に示すようにドリルでφ250nのピア
ホール3を10個形成した。次に、第2表に示す市販の
導体線2(φ250I!In)の充填を行った。
As shown in FIG. 4, ten pier holes 3 having a diameter of 250 nm were formed in the laminate using a drill. Next, a commercially available conductor wire 2 (φ250I!In) shown in Table 2 was filled.

ビア形成後、積層体に市販の導体線(φ25On)を使
用し配線を施した。配線後、積層体の上下を4枚の上記
と同質のグリーンシートで挟み込み積層(60°C、5
0MPa)を行い、N2中800°C,5hで脱脂し、
第3表Nαeの条件で焼成を行った。焼成後の配線の体
積抵抗率および基板−ビア間のクラックの有無を第5表
に示す。
After forming the vias, wiring was applied to the laminate using commercially available conductor wires (φ25On). After wiring, the top and bottom of the laminate were sandwiched between four green sheets of the same quality as above and laminated (60°C, 50°C).
0 MPa), degreased in N2 at 800°C for 5 hours,
Firing was performed under the conditions of Nαe in Table 3. Table 5 shows the volume resistivity of the wiring after firing and the presence or absence of cracks between the substrate and vias.

比較例1 第1表No、 eに示す組成のグリーンシート】(密度
1.7og/cffl、厚さ30011v)をドクター
ブレード法で作製した。このグリーンシートを口90鵬
に打抜き、6枚1&[1で積層(60°C、5MPa)
を行った。
Comparative Example 1 A green sheet having the composition shown in Table 1 No. e (density 1.7 og/cffl, thickness 30011v) was produced by a doctor blade method. This green sheet was punched out to a diameter of 90 mm, and 6 sheets were laminated at 1&[1] (60°C, 5MPa)
I did it.

積層体を第4図に示すようにドリルでφ250卿のピア
ホール3を10個形成した。次に、市販のWペーストで
充填を行った。ビア形成後、積層体にメタルマスクを使
用し、市販のWペーストで配線2(幅3004)を施し
た。配線後、積層体の上下を4枚の上記と同質のグリー
ンシートで挟み込み積層(60°C、50MPa)を行
い、N2中800°C,5hで脱脂し、第5表の条件で
焼成を行った。焼成後の配線の体積抵抗率および基板−
ビア間のクランクの有無を第5表に示す。
As shown in FIG. 4, ten pier holes 3 having a diameter of 250 mm were formed in the laminate using a drill. Next, filling was performed with commercially available W paste. After forming the vias, a metal mask was used on the laminate to form wiring 2 (width 3004) using commercially available W paste. After wiring, the top and bottom of the laminate were sandwiched between four green sheets of the same quality as above and laminated (60°C, 50MPa), degreased in N2 at 800°C for 5 hours, and fired under the conditions shown in Table 5. Ta. Volume resistivity of wiring and substrate after firing
Table 5 shows the presence or absence of cranks between vias.

比較例2 第1表Nneに示す組成のグリーンシート1 (密度1
.70 g /d、厚さ300an)をドクターブレー
ド法で作製した。このグリーンシートを口90mmに打
抜き、6枚1組で積層(60°C、5MPa)を行った
Comparative Example 2 Green sheet 1 having the composition shown in Table 1 Nne (density 1
.. 70 g/d, thickness 300 an) was produced by the doctor blade method. This green sheet was punched out to have an opening of 90 mm, and a set of 6 sheets were laminated (60°C, 5 MPa).

積層体を第4図に示すようにドリルでφ250趨のピア
ホール3を10個形成した。次に、市販の銅ペーストで
充填を行った。ビア形成後、積層体にメタルマスクを使
用し、市販の銅ペーストで配線2(幅300卿)を施し
た。配線後、積層体の上下を4枚の上記と同質のグリー
ンシートで挟み込み積層(60°C、50MPa)を行
い、N2中800″C,5hで脱脂し、第5表の条件で
焼成を行った。焼成後の配線の体積抵抗率および基板−
ビア間のクランクの有無を第5表に示す。
As shown in FIG. 4, ten pier holes 3 each having a diameter of 250 mm were formed in the laminate using a drill. Next, filling was performed with commercially available copper paste. After forming the vias, a metal mask was used on the laminate, and wiring 2 (width 300 mm) was formed using commercially available copper paste. After wiring, the top and bottom of the laminate were sandwiched between four green sheets of the same quality as above and laminated (60°C, 50MPa), degreased at 800''C in N2 for 5 hours, and fired under the conditions shown in Table 5. Volume resistivity of wiring and substrate after firing
Table 5 shows the presence or absence of cranks between vias.

比較例3 第1表Ntheに示す組成のグリーンシート1 (密度
1.70g/cd、厚さ3001na)をドクターブレ
ード法で作製した。このグリーンシートを口90++m
に打抜き、6枚1組で積層(60″C、5MPa)を行
った。
Comparative Example 3 Green sheet 1 (density 1.70 g/cd, thickness 3001 na) having the composition shown in Table 1 Nthe was produced by a doctor blade method. This green sheet is 90++ m
The sheets were punched out and laminated (60''C, 5MPa) in a set of 6 sheets.

積層体を第4図に示すようにドリルでφ250−のピア
ホール3を10個形成した。次に、第2表に示す市販の
導体線2(φ250p)の充填を行った。
As shown in FIG. 4, ten pier holes 3 having a diameter of 250 mm were formed in the laminate using a drill. Next, a commercially available conductor wire 2 (φ250p) shown in Table 2 was filled.

ビア形成後、積層体に市販の導体線(φ25On)を使
用し配線を施した。配線後、積層体の配線面を4枚の上
記と同質のグリーンシートで覆い積層(60°C、50
MPa)を行い、N2中800”C、5hで脱脂し、第
5表の条件で焼成を行った。焼成後の配線の体積抵抗率
および基板−ビア間のクシツクの有無を第4表に示す。
After forming the vias, wiring was applied to the laminate using commercially available conductor wires (φ25On). After wiring, the wiring surface of the laminate was covered with four green sheets of the same quality as above and laminated (60°C, 50°C).
MPa), degreased at 800"C in N2 for 5 hours, and fired under the conditions shown in Table 5. Table 4 shows the volume resistivity of the wiring after firing and the presence or absence of wrinkles between the substrate and vias. .

第1表 グリーンシート組成 第2表 基板と導体の組合せ O:組合せ良 二組合せ不可 第5表 比 較 〔発明の効果〕 以上説明したように、本発明によれば基板−導体間に生
じるクラックを防止することができ、さらに高温域(1
600°C以上)焼成のセラミック(AffiN、 A
pzox)に低抵抗金属の配線を施すことができる。ま
たこれらの効果のため、セラミック回路基板の高性能化
多用途化および歩留り向上に寄与する所が大きい。
Table 1: Green sheet composition Table 2: Combination of substrate and conductor O: Good combination, 2 bad combinations: Table 5 Comparison [Effects of the invention] As explained above, according to the present invention, cracks occurring between the substrate and the conductor can be prevented. In addition, the high temperature range (1
600°C or higher) fired ceramics (AffiN, A
pzox) can be provided with low resistance metal wiring. In addition, these effects greatly contribute to the high performance, versatility, and yield improvement of ceramic circuit boards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明に係るグリーンシートに導体線を配線
し、導体線でビアを形成した物の斜視図及び部分拡大図
であり、第2図(a)及び(b)は無垢グリーンシート
でビア形成グリーンシートを密封した積層体を示す断面
図及び部分拡大図であり、第3図(a)及び(b)はセ
ラミック回路基板(従来)の斜視図及び部分拡大図であ
り、第4図は本発明の実施例を示す図である。 1・・・セラミック基板材(グリーンシート)、2・・
・ワイヤー(配線導体)、 3・・・ビア(配線導体)、 3a・・・ビア材(配線材)、  4・・・デラミ、6
・・・密封用セラミックス(焼成前)、7・・・積層金
型。 3・・・ビア(配線材) 3a・・・ビア材 4・・・デラミ 6・・・密封用セラミックス 実施例 第2図 従来例 第3図 実施例 第4図
Fig. 1 is a perspective view and a partially enlarged view of a green sheet according to the present invention, in which conductor wires are wired and vias are formed with the conductor wires, and Fig. 2 (a) and (b) are solid green sheets. FIGS. 3(a) and 3(b) are a perspective view and a partially enlarged view of a ceramic circuit board (conventional), and FIGS. The figure shows an embodiment of the present invention. 1... Ceramic substrate material (green sheet), 2...
・Wire (wiring conductor), 3... Via (wiring conductor), 3a... Via material (wiring material), 4... Delami, 6
... Sealing ceramics (before firing), 7... Laminated mold. 3... Via (wiring material) 3a... Via material 4... Delami 6... Ceramic for sealing Embodiment Fig. 2 Conventional example Fig. 3 Embodiment Fig. 4

Claims (1)

【特許請求の範囲】 1、セラミック基板(1)と、該セラミック基板(1)
の焼成温度で溶融する金属からなる配線材料(2)とを
有することを特徴とするセラミック回路基。 2、セラミック基板材上及び該セラミック基板(1)に
設けられた開口部(3)に該セラミック基板材の焼成温
度で溶融する金属からなる配線材料(2)を施し、前記
配線材料(2)が形成されたセラミック基板材を加圧−
密封して焼成することを特徴とするセラミック回路基板
の製造方法。 3、前記配線材料がワイヤー状を有することを特徴とす
る請求項2記載の方法。 4、前記加圧−密封処理が前記セラミック基板材とほゞ
同質の材料で該セラミック基板材を上下から挾むように
して行うことを特徴とする請求項2記載の方法。
[Claims] 1. Ceramic substrate (1) and the ceramic substrate (1)
A ceramic circuit board comprising a wiring material (2) made of a metal that melts at a firing temperature of . 2. Apply a wiring material (2) made of a metal that melts at the firing temperature of the ceramic substrate material to the opening (3) provided on the ceramic substrate material and the ceramic substrate (1), and apply the wiring material (2) Pressure is applied to the ceramic substrate material that has been formed.
A method for manufacturing a ceramic circuit board, characterized by sealing and firing. 3. The method according to claim 2, wherein the wiring material has a wire shape. 4. The method according to claim 2, wherein the pressurizing and sealing treatment is performed by sandwiching the ceramic substrate material from above and below using a material that is substantially the same as the ceramic substrate material.
JP24275690A 1990-09-14 1990-09-14 Ceramic circuit board and its production Pending JPH04124071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24275690A JPH04124071A (en) 1990-09-14 1990-09-14 Ceramic circuit board and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24275690A JPH04124071A (en) 1990-09-14 1990-09-14 Ceramic circuit board and its production

Publications (1)

Publication Number Publication Date
JPH04124071A true JPH04124071A (en) 1992-04-24

Family

ID=17093801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24275690A Pending JPH04124071A (en) 1990-09-14 1990-09-14 Ceramic circuit board and its production

Country Status (1)

Country Link
JP (1) JPH04124071A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000151045A (en) * 1998-08-31 2000-05-30 Kyocera Corp Wiring board and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000151045A (en) * 1998-08-31 2000-05-30 Kyocera Corp Wiring board and manufacture thereof

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