JPH04123445A - Semi-conductor integrated circuit device - Google Patents

Semi-conductor integrated circuit device

Info

Publication number
JPH04123445A
JPH04123445A JP2244446A JP24444690A JPH04123445A JP H04123445 A JPH04123445 A JP H04123445A JP 2244446 A JP2244446 A JP 2244446A JP 24444690 A JP24444690 A JP 24444690A JP H04123445 A JPH04123445 A JP H04123445A
Authority
JP
Japan
Prior art keywords
lead
bonding
wires
pin
grid array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2244446A
Other languages
Japanese (ja)
Inventor
Toshihiro Tsuboi
敏宏 坪井
Masayuki Shirai
優之 白井
Takashi Miwa
孝志 三輪
Kanji Otsuka
寛治 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP2244446A priority Critical patent/JPH04123445A/en
Publication of JPH04123445A publication Critical patent/JPH04123445A/en
Pending legal-status Critical Current

Links

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Abstract

PURPOSE:To provide multiple pins by a method wherein a semi-conductor chip and, at least, a part of a lead pin are connected with a covered wire, and one bonding, lead and one lead pin are connected with a plurality of covered wires, thereby allowing a high-speed operation of a pin grid array. CONSTITUTION:An insulated circuit board 2 of a pin grid array 1 is made of a synthetic resin, with a semi-conductor chip 3 bonded on the center of the upper side by means of adhesives 4. A bonding lead 5 is arranged so as to surround the semi-conductor chip 3, and a covered wire 7 is bonded over a bonding pad 6 formed on the surroundings of the main plain of the semi-conductor chip. A covered wire 9 is bonded between the lead pin 8 and the bonding lead 5, with one end of the wire 9 being bonded on a rand 11 formed on the upper corner section of a through-hole 10. It is possible to connect between the semi-conductor chip 3 and the lead pin 8 with the shortest distance so that the length for wiring can be shortened, thereby reducing the impedance of the wiring.

Description

【発明の詳細な説明】 〔産業上の利用分野コ 本発明は、半導体集積回路装置に関し、特にピングリッ
ドアレイ（ｐｉｎ　ｇｒｉｄ　ａｒｒａｙ）に適用して
有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a pin grid array.

〔従来の技術〕[Conventional technology]

多ビン化に好適なＬＳＩパッケージの一種にピングリッ
ドアレイがある。ピングリッドアレイは、多数のリード
ピンを挿入した絶縁基板の中央に半導体チップを搭載し
、上記絶縁基板に形成した配線と上記半導体チップとの
間をワイヤにより接続したパッケージ構造を有している
。なお、ピングリッドアレイについては、特開昭６０−
３８８４２号公報に記載がある。A pin grid array is a type of LSI package suitable for multi-bin implementation. A pin grid array has a package structure in which a semiconductor chip is mounted in the center of an insulating substrate into which a large number of lead pins are inserted, and wiring formed on the insulating substrate and the semiconductor chip are connected by wires. Regarding the pin grid array, please refer to Japanese Patent Application Laid-Open No. 1986-
There is a description in Publication No. 38842.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、従来のピングリッドアレイは、リードピンに
接続された配線をチップの近傍まで引き回す際、より内
側にあるリードピンを迂回させたり、スルーホールを介
して別の層を経由させたりするため、配線長の増加に起
因するインピーダンスの増大が避けられず、高速動作を
実現することが困難になっている。また、限られた面積
の絶縁基板に高密度に配線を形成することは加工上の限
界があるため、多ビン化を実現することも困難になって
いる。However, in conventional pin grid arrays, when routing the wiring connected to the lead pins to the vicinity of the chip, the wiring length is reduced because the wiring is routed around the lead pins located further inside or through another layer via a through hole. An increase in impedance due to an increase in 2 is unavoidable, making it difficult to achieve high-speed operation. Furthermore, there are processing limitations in forming wiring at high density on an insulating substrate with a limited area, making it difficult to realize a large number of bins.

本発明の目的は、ピングリッドアレイの高速動作を実現
する技術を提供することにある。An object of the present invention is to provide a technique for realizing high-speed operation of a pin grid array.

本発明の他の目的は、ピングリッドアレイの多ピン化を
実現する技術を提供することにある。Another object of the present invention is to provide a technique for increasing the number of pins in a pin grid array.

本発明の他の目的は、ピングリッドアレイの製造コスト
の低減を実現する技術を提供することにある。Another object of the present invention is to provide a technique for reducing manufacturing costs of pin grid arrays.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとふりである。A brief overview of typical inventions disclosed in this application is as follows.

（１）１本願の一つの発明は、絶縁基板の中央部に搭載
した半導体チップと少なくとも一部のリードビンとを被
覆ワイヤにより接続したピングリッドアレイである。(1) One invention of the present application is a pin grid array in which a semiconductor chip mounted in the center of an insulating substrate and at least some lead bins are connected by a covered wire.

（２）９本願のもう一つの発明は、上記（１）のピング
リッドアレイにおいて、一つのボンディングリードと一
つのリードピンとを複数本の被覆ワイヤにより接続する
ものである。(2)9 Another invention of the present application is that in the pin grid array of the above (1), one bonding lead and one lead pin are connected by a plurality of covered wires.

〔作用〕[Effect]

上記した手段（１）によれば、半導体チップとリードピ
ンとをワイヤで接続することにより、両者の間を最短距
離で接続することができるので、絶縁基板上で配線を引
き回す従来技術に比べて配線のインピーダンスを低減す
ることができる。According to the above-mentioned means (1), by connecting the semiconductor chip and the lead pins with wires, it is possible to connect them over the shortest distance. impedance can be reduced.

また、上記した手段（１）によれば、半導体チップとリ
ードピンとを接続するワイヤに被覆ワイヤを使用するこ
とにより、ワイヤ同士の接触による短絡を回避すること
ができるため、絶縁基板上で配線を引き回す従来技術に
比べて配線を高密度化することができ、絶縁基板を大形
化することなく多ピン化を実現することができる。Furthermore, according to the above-mentioned means (1), by using coated wires for the wires connecting the semiconductor chip and the lead pins, it is possible to avoid short circuits due to contact between the wires. It is possible to increase the density of wiring compared to the conventional technique of routing the wiring, and it is possible to increase the number of pins without increasing the size of the insulating substrate.

また、上記した手段（１）によれば、半導体チップとリ
ードピンとをワイヤで接続することにより、配線変更を
自由に行うことができるので、回路の設計変更毎に絶縁
基板を作り直す手間が不要となる。また、同一の絶縁基
板を用いて多品種のピングリッドアレイを製造すること
ができる。Furthermore, according to the above-mentioned means (1), wiring can be changed freely by connecting the semiconductor chip and the lead pins with wires, so there is no need to re-create the insulating substrate every time the circuit design is changed. Become. Furthermore, a wide variety of pin grid arrays can be manufactured using the same insulating substrate.

上記した手段（２）によれば、一つのボンディングリー
ドと一つのリードピンとを複数本のワイヤで接続するこ
とにより、配線のインダクタンス（Ｌ）成分や抵抗（Ｒ
）成分が低減されるので、配線のインピーダンスをさら
に低減することができる。According to the above-mentioned means (2), by connecting one bonding lead and one lead pin with a plurality of wires, the inductance (L) component and resistance (R) of the wiring can be reduced.
) component is reduced, the impedance of the wiring can be further reduced.

以下、実施例により本発明を説明する。なお、実施例を
説明するための全図において同一の機能を有するものは
同一の符号を付し、その繰り返しの説明は省略する。The present invention will be explained below with reference to Examples. In addition, in all the figures for explaining the embodiment, parts having the same functions are denoted by the same reference numerals, and repeated explanation thereof will be omitted.

〔実施例１〕 第１図は、本実施例１によるピングリッドアレイ１の断
面図、第２図は同じく平面図である。[Example 1] FIG. 1 is a sectional view of a pin grid array 1 according to Example 1, and FIG. 2 is a plan view thereof.

ピングリッドアレイ１の絶縁基板２は、例えばガラス布
基材エポキシ樹脂（ガラエポ）、ガラス布基材ポリイミ
ド樹脂またはビスマレイミド−トリアジン樹脂（ＢＴレ
ジン）などの合成樹脂で構成されている。上記絶縁基板
２の上面中央部には半導体チップ３が搭載されている。The insulating substrate 2 of the pin grid array 1 is made of synthetic resin such as glass cloth-based epoxy resin (glass-epoxy resin), glass cloth-based polyimide resin, or bismaleimide-triazine resin (BT resin). A semiconductor chip 3 is mounted on the center portion of the upper surface of the insulating substrate 2.

上記半導体チップ３は、例えばシリコーンゴムなどの接
着剤４により絶縁基板２上に接着されている。The semiconductor chip 3 is bonded onto the insulating substrate 2 with an adhesive 4 such as silicone rubber.

上記半導体チップ３の近傍の絶縁基板２上には多数のボ
ンディングリード５が形成されている。A large number of bonding leads 5 are formed on the insulating substrate 2 near the semiconductor chip 3.

上記ボンディングリード５は、半導体チップ３を囲むよ
うに配置されている。ボンディングリード５は、例えば
絶縁基板２上に接着したＣｕ箔をエツチングしたもので
、その表面にはＮｉ、Ａｕの順でメツキが施されている
。半導体チップ３の主面の周辺部に形成されたポンディ
ングパッド６とボンディングリード５との間には、Ａｕ
、ＡｌまたはＣｕからなるワイヤ７がボンディングされ
ている。The bonding leads 5 are arranged to surround the semiconductor chip 3. The bonding lead 5 is, for example, etched Cu foil adhered to the insulating substrate 2, and its surface is plated with Ni and Au in that order. Between the bonding pad 6 and the bonding lead 5 formed on the periphery of the main surface of the semiconductor chip 3, an
A wire 7 made of , Al or Cu is bonded.

上記絶縁基板２の中央部を除いた領域には多数のリード
ピン８が挿入されている。上記リードピン８は、例えば
４２７０イやコバールなどのＦｅ系合金で構成されてお
り、その表面にはＳｎあるいは半田などのメツキが施さ
れている。リードビン８とボンディングリード５との間
には、Ａｕ。A large number of lead pins 8 are inserted into a region of the insulating substrate 2 excluding the central portion. The lead pin 8 is made of an Fe-based alloy such as 4270I or Kovar, and its surface is plated with Sn or solder. Between the lead bin 8 and the bonding lead 5 is Au.

ＡＡまたはＣｕからなるワイヤの表面に合成樹脂などの
絶縁材料を被覆した被覆ワイヤ９がボンディングされて
いる。上記被覆ワイヤ９の一端は、例えばリードビン８
が挿入されたスルーホール１０の上縁部に形成されたラ
ンド１１上にボンディングされている。A coated wire 9 coated with an insulating material such as a synthetic resin is bonded to the surface of a wire made of AA or Cu. One end of the covered wire 9 is connected to a lead bin 8, for example.
is bonded onto a land 11 formed on the upper edge of the through hole 10 into which the through hole 10 is inserted.

上記絶縁基板２の上面には、半導体チップ３、ワイヤ７
および被覆ワイヤ９の耐湿性を確保するための封止樹脂
１２が設けられている。上記封止樹脂１２は、例えば射
出成形やポツティングにより形成されたエポキシ系樹脂
などからなる。On the upper surface of the insulating substrate 2, a semiconductor chip 3 and wires 7 are provided.
A sealing resin 12 is provided to ensure the moisture resistance of the coated wire 9. The sealing resin 12 is made of, for example, an epoxy resin formed by injection molding or potting.

以上のように構成された本実施例１のピングリッドアレ
イ１によれば、下言己のような作用、効果を得ることが
できる。According to the pin grid array 1 of the first embodiment configured as described above, the following operations and effects can be obtained.

（１）、半導体チップ３とその近傍に配置したボンディ
ングリード５とをワイヤ７で接続するとともに、ボンデ
ィングリード５とリードピン８とを被覆ワイヤ９で接続
することにより、半導体チップ３とリードピン８との間
を最短距離で接続することができる。これにより、絶縁
基板２上の配線長を従来よりも短縮することができるの
で、配線のインピーダンスを低減することができ、ピン
グリッドアレイ１の高速動作を実現することができる。(1) The semiconductor chip 3 and the lead pins 8 are connected by connecting the semiconductor chip 3 and the bonding leads 5 disposed near the semiconductor chip 3 with the wires 7, and by connecting the bonding leads 5 and the lead pins 8 with the coated wires 9. can be connected over the shortest distance. As a result, the length of the wiring on the insulating substrate 2 can be made shorter than before, so the impedance of the wiring can be reduced, and high-speed operation of the pin grid array 1 can be realized.

（２）、ボンディングリード５とリードピン８とを被覆
ワイヤ９で接続することにより、ワイヤ同士の接触によ
る短絡を回避することができる。これにより、絶縁基板
２上の配線密度を向上させることができるので、絶縁基
板２を大形化することなくピングリッドアレイ１の多ピ
ン化を実現することができる。(2) By connecting the bonding lead 5 and the lead pin 8 with the coated wire 9, it is possible to avoid a short circuit due to contact between the wires. As a result, the wiring density on the insulating substrate 2 can be improved, so it is possible to increase the number of pins in the pin grid array 1 without increasing the size of the insulating substrate 2.

〔３）、半導体チップ３とリードピン８とをワイヤ７９
で接続することにより、配線変更を自由に行うことがで
きる。すなわち半導体チップ３に形成された任意のポン
ディングパッド６と絶縁基板２に挿入された任意のリー
ドピン８とを接続することができるので、回路の設計変
更毎に絶縁基板２を作り直す手間が不要となり、また、
同一の絶縁基板２を用いて多品種のピングリッドアレイ
を製造することができるので、ピングリッドアレイ１の
製造コストを低減することができる。[3) Connect the semiconductor chip 3 and lead pins 8 with wires 79
By connecting with , wiring can be changed freely. In other words, any bonding pad 6 formed on the semiconductor chip 3 can be connected to any lead pin 8 inserted into the insulating substrate 2, so there is no need to recreate the insulating substrate 2 every time the circuit design is changed. ,Also,
Since a wide variety of pin grid arrays can be manufactured using the same insulating substrate 2, the manufacturing cost of the pin grid array 1 can be reduced.

なお、ボンディングリード５とリードピン８との接続は
、必ずしも全てを被覆ワイヤ９で行う必要はない。すな
わちワイヤの密度が低く、ワイヤ同士の接触による短絡
の虞れがない領域では、被覆のない裸のワイヤでボンデ
ィングリード５とリードピン８とを接続してもよい。こ
れにより、高価な被覆ワイヤ９の使用量を減らすことが
できるので、ピングリッドアレイ１の製造コストを低減
することができる。Note that the bonding leads 5 and the lead pins 8 do not necessarily need to be connected entirely using the coated wires 9. That is, in areas where the density of wires is low and there is no risk of short circuiting due to contact between wires, the bonding leads 5 and lead pins 8 may be connected using bare wires without coating. As a result, the amount of expensive coated wire 9 used can be reduced, so the manufacturing cost of pin grid array 1 can be reduced.

また、ボンディングリード５とリードピン８との接続の
みならず、半導体チップ３のポンディングパッド６とボ
ンディングリード５との接続に被覆ワイヤを使用しても
よい。これにより、例えば封止樹脂１２を成形する際の
樹脂流れなどに起因するワイヤ同士の短絡を確実に防止
することができるので、ピングリッドアレイ１の信頼性
が向上する。Further, a coated wire may be used not only for the connection between the bonding lead 5 and the lead pin 8 but also for the connection between the bonding pad 6 of the semiconductor chip 3 and the bonding lead 5. This makes it possible to reliably prevent short circuits between wires due to, for example, resin flow during molding of the sealing resin 12, thereby improving the reliability of the pin grid array 1.

また、被覆ワイヤ９の一端をランドｌｌ上にボンディン
グする手段に代えて、リードビン８上に直接ボンディン
グしてもよい。この場合は、リードピン８の上端を平坦
化しておくことにより、ボンディング作業が容易になる
。Furthermore, instead of bonding one end of the covered wire 9 onto the land 11, it may be directly bonded onto the lead bin 8. In this case, the bonding work can be facilitated by flattening the upper end of the lead pin 8.

〔実施例２〕 第３図は、本実施例２のピングリッドアレイ１の断面図
である。[Example 2] FIG. 3 is a sectional view of the pin grid array 1 of Example 2.

本実施例２のピングリッドアレイ１は、ボンディングリ
ード５とリードピン８との接続に二本の被覆ワイヤ９を
使用している。The pin grid array 1 of the second embodiment uses two coated wires 9 to connect the bonding leads 5 and lead pins 8.

これにより、ボンディングリード５とリードピン８とを
一本の被覆ワイヤ９で接続する場合に比べて、ワイヤの
インダクタンス（Ｌ）成分や抵抗（Ｒ）成分が低減され
るので、配線のインピーダンスをさらに低減することが
でき、ピングリッドアレイ１のより一層の高速動作を実
現することができる。As a result, the inductance (L) component and resistance (R) component of the wire are reduced compared to the case where the bonding lead 5 and the lead pin 8 are connected with a single coated wire 9, so the impedance of the wiring is further reduced. Therefore, even higher speed operation of the pin grid array 1 can be realized.

なお、ボンディングリード５とリードピン８との接続に
三本またはそれ以上の被覆ワイヤ９を使用することによ
り、配線のインピーダンスをさらに低減することができ
る。Note that by using three or more coated wires 9 to connect the bonding lead 5 and the lead pin 8, the impedance of the wiring can be further reduced.

才だ、ボンディングリード５とリードビン８゜の接続は
、必ずしも全てを複数本の被覆ワイヤで行う必要はない
。例えば電源電位や接地電位（供給するボンディングリ
ード５−リードピン８ｎにだけ複数本の被覆ワイヤ９を
使用した場合で４ピングリツドアレイ１の電気特性を向
上させることができる。However, the connection between the bonding lead 5 and the lead bin 8° does not necessarily have to be made using a plurality of coated wires. For example, the electrical characteristics of the four-pin grid array 1 can be improved by using a plurality of covered wires 9 only for the bonding leads 5 to the lead pins 8n that supply the power supply potential or the ground potential.

また、ボンディングリード５とリードピン８Ｊの接続の
みならず、半導体チップ３のポンデイ）グパッド６とボ
ンディングリード５とを複数本Ｃワイヤ７で接続するこ
ともできる。これにより、配線のインピーダンスをさら
に低減することができる。In addition to connecting the bonding leads 5 and the lead pins 8J, it is also possible to connect the bonding pads 6 of the semiconductor chip 3 and the bonding leads 5 with a plurality of C wires 7. Thereby, the impedance of the wiring can be further reduced.

〔実施例３〕 第４図は、本実施例３のビングリッドアレイｌの断面図
である。[Embodiment 3] FIG. 4 is a sectional view of the bin grid array l of this embodiment 3.

本実施例３のビングリッドアレイ１は、半導体チップ３
の近傍にボンディングリード５を設ける手段に代えて、
リードピン８と第４図では図示しない半導体チップ３の
ポンディングパッド６との間を直接被覆ワイヤ９でボン
ディングしている。The bin grid array 1 of the third embodiment includes a semiconductor chip 3
Instead of providing the bonding lead 5 near the
Lead pins 8 and bonding pads 6 of semiconductor chip 3 (not shown in FIG. 4) are directly bonded using covered wires 9.

これにより、絶縁基板２上の配線長を前記実施例１．２
よりもさらに短縮することができるので、ビングリッド
アレイｊのより一層の高速動作を実現することができる
。As a result, the wiring length on the insulating substrate 2 can be adjusted as in Example 1.2.
Since the length can be further shortened, even higher speed operation of the bin grid array j can be realized.

また、ボンディングリード５を設ける工程が省け、かつ
ポンディングパッド５と半導体チップ３との間にワイヤ
７をボンディングする工程が省けるので、ビングリッド
アレイ１の製造工程が短縮され、その製造コストをさら
に低減することができる。In addition, the process of providing the bonding leads 5 and the process of bonding the wires 7 between the bonding pads 5 and the semiconductor chip 3 can be omitted, so the manufacturing process of the bin grid array 1 is shortened and the manufacturing cost is further reduced. can be reduced.

なお、本実施例３に右いても前記実施例２と同様、リー
ドピン８と半導体チップ３との間を複数本の被覆ワイヤ
９で接続することができる。Incidentally, even in the third embodiment, as in the second embodiment, the lead pins 8 and the semiconductor chip 3 can be connected by a plurality of covered wires 9.

また、前記実施例１と同様、ワイヤの密度が低く、ワイ
ヤ同士の接触による短絡の虞れがない領域では、被覆の
ない裸のワイヤでリードピン８と半導体チップ３とを接
続してもよい。Further, as in the first embodiment, in areas where the wire density is low and there is no risk of short circuiting due to contact between wires, the lead pins 8 and the semiconductor chip 3 may be connected using bare wires without coating.

以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例１〜３に限定
されるものではなく、その要旨を逸脱しない範囲で種々
変更可能であることはいうまでもない。The invention made by the present inventor has been specifically explained based on Examples above, but the present invention is not limited to Examples 1 to 3, and can be modified in various ways without departing from the gist thereof. Needless to say.

例えば第５図に示すように、絶縁基板２の内側に位置し
ているリードピン８は、絶縁基板２上にあらかじめ形成
した配線１３とその一端にボンディングしたワイヤ７と
を介して半導体チップ３に接続し、絶縁基板２の周辺部
に位置しているリードピン８は、被覆ワイヤ９とボンデ
ィングリード６とワイヤ７とを介して半導体チップ３に
接続してもよい。For example, as shown in FIG. 5, lead pins 8 located inside the insulating substrate 2 are connected to the semiconductor chip 3 via a wiring 13 previously formed on the insulating substrate 2 and a wire 7 bonded to one end of the wiring 13. However, the lead pins 8 located on the periphery of the insulating substrate 2 may be connected to the semiconductor chip 3 via the covered wires 9, the bonding leads 6, and the wires 7.

また以上の説明では、絶縁基板を合成樹脂で構成したプ
ラスチック・ビングリッドアレイに適用した場合につい
て説明したが、絶縁基板を窒化アルミニウム、アルミナ
、ムライトなどのセラミックで構成したセラミック・ビ
ングリッドアレイに適用することもできる。Furthermore, in the above explanation, we have explained the case where the insulating substrate is applied to a plastic bin grid array made of synthetic resin, but it can also be applied to a ceramic bin grid array whose insulating substrate is made of ceramic such as aluminum nitride, alumina, or mullite. You can also.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

（ｌ］２絶縁基板の中央部に搭載した半導体チップと少
なくとも一部のリードピンとを被覆ワイヤにより接続し
たピングリッドアレイ構造とすることにより、半導体チ
ップとリードピンとの間を最短距離で接続することがで
きるので、配線のインピーダンスが低減される結果１．
ビングリッドアレイの高速動作を実現することができる
。(l) 2 By forming a pin grid array structure in which the semiconductor chip mounted in the center of the insulating substrate and at least some of the lead pins are connected by coated wires, the semiconductor chip and the lead pins can be connected at the shortest possible distance. As a result, the impedance of the wiring is reduced.1.
High-speed operation of bin grid arrays can be achieved.

また、ワイヤ同士の接触による短絡を回避することがで
きるので、配線を高密度化することができ、絶縁基板を
大形化することなくビングリッドアレイの多ビン化を実
現することができる。Further, since short circuits due to contact between wires can be avoided, the wiring density can be increased, and a multi-bin bin grid array can be realized without increasing the size of the insulating substrate.

また、配線変更を自由に行うことができるので、回路の
設計変更毎に絶縁基板を作り直す手間が不要となる、同
一の絶縁基板を用いて多品種のビングリッドアレイを製
造することができるなどの効果が得られ、ビングリッド
アレイの製造コストを低減することができる。In addition, since wiring can be changed freely, there is no need to re-create the insulating substrate every time the circuit design is changed, and a wide variety of bin grid arrays can be manufactured using the same insulating substrate. This is effective, and the manufacturing cost of the bin grid array can be reduced.

（２）、絶縁基板の中央部に搭載した半導体チップと少
なくとも一部のリードピンとを複数本の被覆ワイヤによ
り接続したピングリッドアレイ構造とすることにより、
配線のインピーダンスをさらに低減することができるの
で、ピングリッドアレイのより一層の高速動作を実現す
ることができる。(2) By forming a pin grid array structure in which the semiconductor chip mounted in the center of the insulating substrate and at least some of the lead pins are connected by a plurality of covered wires,
Since the impedance of the wiring can be further reduced, even higher speed operation of the pin grid array can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例である半導体集積回路装置
の断面図、 第２図は、同じく要部破断平面図、 第３図は、本発明の他の実施例である半導体集積回路装
置の断面図、 第４図は、本発明のさらに他の実施例である半導体集積
回路装置の断面図、 第５図は、本発明のさらに他の実施例である半導体集積
回路装置の断面図である。 １・・・ビングリッドアｌ／イ、２・・・絶縁基板、３
・・・半導体チップ、４・・・接着剤、５・・・ボンデ
ィングリード、６・・・ボンデインクハツト、７・・・
ワイヤ、８・・・リードピン、９・・・被覆ワイヤ、１
０・・・スルーホール、１１・・・ランド、１２・・・
封止樹脂、１３・・配線。FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device that is an embodiment of the present invention, FIG. 2 is a cutaway plan view of the main parts, and FIG. 3 is a semiconductor integrated circuit that is another embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor integrated circuit device according to yet another embodiment of the present invention; FIG. 5 is a cross-sectional view of a semiconductor integrated circuit device according to still another embodiment of the present invention. It is. 1... Bingrid l/a, 2... Insulating substrate, 3
... Semiconductor chip, 4... Adhesive, 5... Bonding lead, 6... Bonding ink hat, 7...
Wire, 8... Lead pin, 9... Covered wire, 1
0...Through hole, 11...Land, 12...
Sealing resin, 13... Wiring.

Claims (1)

【特許請求の範囲】 １、絶縁基板の中央部に搭載した半導体チップと少なく
とも一部のリードピンとを被覆ワイヤにより接続したこ
とを特徴とするピングリッドアレイ形の半導体集積回路
装置。 ２、半導体チップの周囲にボンディングリードを設け、
前記半導体チップと前記ボンディングリードとをワイヤ
により接続するとともに、前記ボンディングリードとリ
ードピンとを被覆ワイヤにより接続したことを特徴とす
る請求項１記載の半導体集積回路装置。 ３、一つのボンディングリードと一つのリードピンとを
複数本のワイヤにより接続したことを特徴とする請求項
１または２記載の半導体集積回路装置。[Scope of Claims] 1. A pin grid array type semiconductor integrated circuit device, characterized in that a semiconductor chip mounted in the center of an insulating substrate and at least some of the lead pins are connected by covered wires. 2. Provide bonding leads around the semiconductor chip,
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor chip and the bonding leads are connected by wires, and the bonding leads and lead pins are connected by covered wires. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein one bonding lead and one lead pin are connected by a plurality of wires.
JP2244446A 1990-09-14 1990-09-14 Semi-conductor integrated circuit device Pending JPH04123445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2244446A JPH04123445A (en) 1990-09-14 1990-09-14 Semi-conductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2244446A JPH04123445A (en) 1990-09-14 1990-09-14 Semi-conductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04123445A true JPH04123445A (en) 1992-04-23

Family

ID=17118776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2244446A Pending JPH04123445A (en) 1990-09-14 1990-09-14 Semi-conductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04123445A (en)

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