JPH04122068A - Gate array integrated circuit device - Google Patents

Abstract

PURPOSE:To keep power consumption low, to reduce a dominating space and to reduce cost by operating a gate array section and an output buffer section for a backup memory from different supplies. CONSTITUTION:A first power supply VDD1 is used for operation of a logic gate circuit in a gate array section 50 and a second power supply VDD2 is used for operation of some of I-O buffer cells for input/output of the logic gate circuit, The I-O buffer cells 51A, 51B, 52A and 52B are located in a line and three parallel tower lines 61-63 are located perpendicular to these I/O buffer cells. The line 61 is used for grounding, the line 62 for the power supply VDD1 and the line 63 for the power supply VDD2. Therefore, a backup logic gate of an external memory chip is not required to be separately installed outside the gate array. Consequently, an IC for external circuit can be eliminated and thus the cost is reduced. In addition, power consumption is also decreased.

Description

TECHNICAL FIELD The present invention relates to gate array integrated circuit devices, and more particularly to gate array human output buffer circuits.

BACKGROUND OF THE INVENTION Conventional gate array integrated circuit devices typically use a single operating power supply. Therefore, it has the following drawbacks.

For example, in a logic circuit system using a gate array integrated circuit chip and a memory chip such as SRAM that requires backup, during normal operation, the SRA is activated by a memory access signal output from the gate array integrated circuit chip.
There are cases where the M chip is accessed and the SRAM chip is backed up and controlled by a predetermined logic level (high level) signal in the memory backup mode. In such a memory backup mode, in order to fix the backup control signal from the gate array integrated circuit chip at a high level, it is necessary to keep the single power supply of the gate array integrated circuit chip on.

In memory backup mode, even though the gate array integrated circuit does not need to operate, the power to the gate array integrated circuit chip is turned on to generate a high-level control signal for memory backup. The disadvantage is that the entire array must be kept active, which is wasteful in terms of power consumption.

In addition, since the power supply during normal operation and the backup power supply are switched by a switch circuit using diodes and transistors, the voltage drop of the gate array power supply is caused by the voltage drop of the diode and transistor. Another drawback is that the operating margin of the gate array is reduced.

Therefore, it is conceivable to separately provide only a logic circuit for memory backup control outside the gate array integrated circuit chip. However, in this case, a special logic IC is required, which has the disadvantage of increasing the space occupied by the IC and increasing the price.

OBJECTS OF THE INVENTION An object of the present invention is to provide a gate array integrated circuit which is capable of suppressing power consumption, reducing occupied space, and reducing cost, with separate operating power supplies for the gate array section and the output buffer section for the backup memory. The purpose is to provide equipment.

Structure of the Invention A gate array integrated circuit device according to the present invention includes a first power supply line, a second power supply line, a gate array unit operated by the power supply of the second power supply line, and a gate array unit that operates by the power supply of the second power supply line. and an output buffer section which operates according to the output of the gate array section and outputs a logic output signal to the outside according to the output of the gate array section, and the output buffer section is configured to operate in response to an external power cutoff indicating a power cutoff of the first power supply line. It is characterized by having a function of generating an output signal of a predetermined logic level in response to a detection signal.

Embodiment FIG. 1A is a diagram showing an example of the arrangement of power supply bins of an IC chip according to an embodiment of the present invention, and FIG. 1B is a diagram showing an example of the layout of power supply lines of an IO buffer section.

The gate array IC chip 1 has a gate array section 50 inside.
is integrated, and the input/output pad row 10 is on the outer periphery.
．． 20.30 and 4o are arranged. Power supply pads 11, 21, and 31 for the first power supply VDDI are provided approximately in the center of each of the input/output pad rows 10, 20, and 30, respectively, and a A power supply pad 41 for the second power supply VDD2 is provided.

The first power supply V DDI is used as an operating power supply for the logic gate circuit in the gate array section 50, and the second power supply V DDI
D2 is used as an operating power source for a portion of the 10 buffer cells for input/output of this logic gate circuit.

Therefore, 10 buffer cells 51A, 51B, 52A, 5
The layout of the 2B section is constructed as shown in FIG. 1(B). In the figure, 10 buffer cells are arranged in a row,
Three power lines 61 to 63 are arranged parallel to each other so as to traverse each cell.

The power line 61 is for grounding, the power line 62 is for power V DDI, and the power line 63 is for power V DD
It is for 2.

The power supply line 63 for VDDZ is connected to 10 buffer cells 51A and 5 which derive an output signal related to a backed-up SRAM chip (not shown) among the IO buffer cells.
Used as a 1B power line.

10 buffer cells 52 not related to the SRAM chip
A and 52B use the power line 62.

FIG. 2 shows an SR using the integrated circuit chip 1 shown in FIG.
This is an example of a circuit that realizes backup control of the AM chip 70. In this example, VDDI is the normal power supply for the integrated circuit chip 1, VDD2 is the backup power supply, and VDD represents the power supply for the entire system.

The system power supply VDD and the voltage of the battery 72 are applied to the power supply monitoring IC chip 71, and the system power supply VDD
(-VDDI) is higher than the voltage of the battery 72, the power supply monitoring IC chip 71 changes VDDI to VDD.
If the power supply VDDI is cut off and becomes lower than the battery voltage, the battery voltage is output as VDD2.

Further, the power supply monitoring IC chip 71 generates a low level signal (BCIN) when the power supply VDDI is below a specified value, and generates a high level signal when it is above the specified value.

The SRAM chip 70 is switched between backup modes by a C8 (chip select) control, and a high level signal is applied during backup mode, and a high level signal is applied during memory access. This signal is supplied as BCOUT from the gate array integrated circuit chip 1, and the signal indicating the power monitoring result of the power monitoring IC chip 71 is supplied as BCIN.
The signal is supplied to the integrated circuit chip 1 as a signal.

FIG. 3 is a specific operation time chart of the circuit shown in FIG. 2. VDDI changes from OV to 5V, VD2 is VD
If DI is lower than the battery voltage (3V in the figure), it is the battery voltage, and if it is higher, it is the voltage of VDDI.

When the signal BCIN becomes VDDI or more than 4.5 V, V
DDI is used as is and becomes a high level signal,
Indicates normal operation mode, low level below 4.5V (
OV) signal, indicating memory backup mode.

Signal BCOUT outputs VDD2 (high level) in memory backup mode when signal BCIN is low level, and becomes a backup control signal.
In normal operation mode above V, the SR of the gate array circuit
A logic signal for memory access to the AM chip 70 is output.

In other words, when the system side power supply VDDI decreases and is cut off, the SRAM chip enters the backup mode and the VDDI
When DDI rises to 4.5 V or higher, the SRAM chip enters memory access mode.

FIG. 4 is a diagram showing a specific circuit of the 0 buffer 51 related to the SRAM chip 70 of the gate array integrated circuit chip 1.

This buffer 51 consists of a two-man gate 55, an inverter (MOS) transistor 56 which uses the gate output as a human power, and a drain resistor 57), and a NOR gate 55.
5, and a pull-down resistor 54 for pulling down by one person. The SRAM access signal from the gate array section is applied to the pull-down input terminal of the NOR gate 55, and the signal BCIN is applied to the other input terminal of the NOR gate 55 via the inverter 53. These buffer 51 and inverter 53 are operated by power supply VDD2.

In the normal memory access mode, since the signal BCIN is at a high level, the output of the NOR gate 55 is always fixed at a low level by the inverter 53. Therefore,
The memory access signal IN from the gate array section is converted directly to the signal BC by the NOR gate 55 and the transistor 56.
Output as OUT.

In the memory backup mode, VDDI is disconnected and is at a low level, and the output from the gate array section is floating, but the single power of the NOR gate 55 is fixed at a low level by the pull-down resistor 54. At this time, since the signal BCIN is at low level, the inverter 5
The output of No. 3 becomes high level (VDD2), and therefore, this high level signal is directly outputted as signal BCOUT by the NOR gate 55 and transistor 56, making it possible to back up the memory.

Effects of the Invention As stated above, since the power supply for the 10 buffer cells of the gate array related to the SRAM chip is configured to use a power supply different from that of the gate array, the The IO buffer 7 cells make it possible to generate a memory backup control signal for the SRAM chip.Therefore, there is no need to specially provide a backup logic gate for the SRAM outside the gate array, reducing the number of external circuit ICs and lowering the price. Furthermore, there is an effect that it becomes possible to achieve low power consumption.

[Brief explanation of drawings]

FIG. 1(A) is a power pin arrangement diagram of an embodiment of the present invention.
Figure (B) is a layout diagram of the power supply line of the same < 10 buffer section, Figure 2 is a circuit diagram that realizes backup control of an SRAM chip using the gate array of the embodiment of the present invention, and Figure 3 is a diagram of Figure 2. 4 is a time chart showing the operation of the circuit. FIG. 4 is a circuit diagram of a specific example of a 10 buffer cell used in an embodiment of the present invention. Explanation of symbols of main parts 1... Gate array integrated circuit chip 50...
...Gate array 51.52...10 buffer cell 62.63.
...Power line 70...SRAM chip 71...Power supply monitoring IC

Claims (2)

[Claims] (1) A first power supply line, a second power supply line, a gate array section operated by the power supply of the first power supply line, and an output of the gate array section operated by the power supply of the second power supply line. an output buffer section that outputs a logical output signal to the outside according to the first power supply line, and the output buffer section outputs a predetermined output signal in response to an external power-off detection signal indicating a power-off of the first power supply line. 1. A gate array integrated circuit device having a function of generating an output signal of a logic level. (2) The power supply of the second power supply line is a backup power supply for an external memory chip, the output signal of the output buffer is a memory access signal of the external memory chip, and the output signal of the predetermined logic level 2. The gate array integrated circuit device according to claim 1, wherein: is a signal for memory backup of the external memory chip.