JPH04119652A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a current level difference to be set large enough to serve as discriminating data by a method wherein a semiconductor device is provided with a discriminating circuit which contains a fuse element and a diode, and an impedance viewed from the standpoint of a connection node of a discriminating circuit toward an inner circuit is set larger than that toward the discriminating circuit. CONSTITUTION:A discriminating circuit 3 is composed of a fuse element 31 and a diode 32 connected in series between a connection node N and a power supply potential Vcc. On the other hand, a resistor R0 is an equivalent resistor of a wiring between an input pin 1 and the connection node N of the discriminating circuit, and a resistor Ra is an equivalent resistor of a wiring between the connection node N and the input circuit 2. An R1 is an equivalent resistor viewed from the connection node N toward the discriminating circuit 3 including the resistance of the fuse element 31. Apart from these resistors, an resistor Rb is a resistor which is inserted so as to enable a resistor, R2=Ra+Rb, viewed from the connection node N toward the input circuit 2 to be much larger than the equivalent resistor R1 toward a discriminating circuit 2 side. By this setup, discrimination data can be detected large enough in sensitivity, so that it can be discriminated that a redundant circuit system is utilized or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device having a redundant circuit.

(Prior Art) In semiconductor integrated circuits, redundant circuits are often provided for hard error relief. For example, in dynamic semiconductor memory devices (DRAM), redundant circuits include spare lines and column selection lines in addition to necessary word lines and column selection lines.
word line.

A spare column selection line is provided, and redundant bit selection/
Spare row decoder to control deselection.

It is configured with a spare column decoder.

In this case, the chip contains the defective address as phase data, and when the defective address is selected, it is replaced with a spare word line or spare column selection line. This redundant circuit system improves the yield of DRAMs.

However, this type of redundant circuit system is adopted by manufacturers as a means of improving product yield, and from the user's perspective, it is impossible to tell whether the DRAM is a non-defective product that has been salvaged by the redundant circuit or a completely non-defective product. Therefore, an identification circuit is provided within the DRAM chip so that the user can easily identify whether it is a repaired non-defective product or a completely non-defective product using an external pin.

FIG. 8 shows an example of the configuration of such a conventional identification circuit. The figure shows a case where an identification circuit 13 is provided on the wiring connecting the output pin 11 and the output circuit 12.

Here, the output circuit 12 has two NMOS transistors Ql and Q2 as driver transistors. The identification circuit 13 includes a phase element 31 and a diode 32. RO and Ra indicate equivalent resistance such as wiring resistance.

The identification information is written depending on whether or not the phase element 31 is disconnected (cut). That is, when a redundant circuit is used, the phase element 31 is cut, and when a redundant circuit is not used, it is left uncut. This identification information is determined by applying a potential higher than the power supply potential Vcc to the output pin 11 and reading the current level at that time.

As shown by the solid line in Figure 10, the voltage-current characteristics of ■ with phase cut and ■ without phase cut are significantly different, and this allows us to identify whether there is phase cut or not, that is, whether it is a completely good product or a repaired good product. I can do it.

However, in such a conventional identification circuit system, a problem arises when the Drino (portion) of the output circuit 12 is converted to CMO3 as shown in FIG.
The output stage of is a PMOS) transistor Ql on the power supply Vce side.
When a CMO5 configuration is adopted using an NMOS (NMOS) transistor Q12 on the ground VSS side, a diode DiD2 is inserted into its output terminal with the polarity shown in the figure. Then, when a positive potential is applied to the output pin 11, the presence or absence of a phase cut in the identification circuit 13 cannot be sufficiently detected due to leakage from the diode D1 of the output circuit 12. This is indicated by broken lines ■ and ■ in Figure 10.

A similar problem also occurs when the identification circuit is provided in the input circuit section. The input circuit section often includes wiring and power supply potential Vc.
This is because a protective diode is provided between c and the ground potential SS.

(Problems to be Solved by the Invention) As described above, in the conventional identification circuit system consisting only of phase elements and diodes, when the output circuit is converted to CMO8 or when a protection diode is provided in the input circuit, The problem was that it could not function properly.

An object of the present invention is to provide a semiconductor integrated circuit device having an identification circuit that solves such problems.

[Structure of the Invention] (Means for Solving the Problems) The present invention identifies whether or not a redundant circuit for relieving hard errors and a redundant circuit connected to wiring connecting an input/output pin and an internal circuit are used. In a semiconductor integrated circuit device having an identification circuit including a phase element and a diode, the impedance in the direction of the internal circuit from the connection node of the identification circuit on the wiring is set to be greater than the impedance in the direction of the identification circuit. It is said that

(Function) According to the present invention, while the basic configuration of the identification circuit is the same as the conventional one, a certain difference is established between the two by focusing on the impedance of the identification circuit side and the internal circuit side as seen from the connection node of the identification circuit. By attaching this, it is possible to create a sufficient difference in current level as identification information, regardless of the configuration of the output circuit or the input circuit.

(Example) Hereinafter, an example in which the present invention is applied to a DRAM will be described.

FIG. 1 shows the configuration of the input circuit section provided with the identification circuit in the DRAM of the embodiment, and FIG. 2 shows the DR of the identification circuit section.
The layout on the AM chip is shown. As shown in FIG. 1, an identification circuit 3 is provided on the wiring between the input pin 1 and the input circuit 2. Input circuit 2 is provided with protective diodes 2122 between its input terminal and power supply potential Vec and ground potential SS. Identification circuit 3
is constructed by connecting a phase element 31 and a diode 32 in series between its connection node N and power supply potential Vcc. The basic configuration of this identification circuit 3 is unchanged from the conventional one. R
O is the equivalent resistance of the wiring from input pin 1 to connection node N of the identification circuit, and Ra is the resistance of the wiring from connection node N to input circuit 2.
is the equivalent resistance of the wiring up to . Further, R1 is an equivalent resistance including the resistance of the phase element 31 when looking from the connection node N to the identification circuit 3 side. For these resistances, Rb
is the resistance R2 when looking at the input circuit 2 side from the connection node N.
(-Ra +Rb) is the equivalent resistance R1 on the identification circuit 2 side
This is an insertion resistance inserted so that it becomes sufficiently larger.

As shown in FIG. 2, a memory array 5 is arranged in a divided manner in the DRAM chip 4. Various peripheral circuits such as buffers and input/output circuits are arranged between the memory arrays 5. The identification circuit section in FIG. 1 is arranged in this peripheral circuit area as shown by the equivalent circuit in the figure.

Now, in the configuration shown in FIG. 1, when a potential V PIN higher than the power supply potential VCC is applied to the input pin 1 so that the diode 32 of the identification circuit 3 is forward biased, the internal impedance Rin seen from the input pin 1 is , the outline is expressed as follows. The internal impedance R1n0 when the phase 31 is not cut is R1n0 = RO+R1・R2/ (R1+R2)...
-(1) The internal impedance R1n1 when the phase 31 is cut is R1n1 = RO + R2 - (2). In this example, so that R1<R2 is satisfied,
The value of insertion resistance Rb is selected. At this time, equation (1) is expressed as RjnO=RO+R1=13). As is clear from comparing equations (2) and (3), the internal impedance varies greatly depending on the presence or absence of a phase cut, and therefore a sufficient difference in current level can be secured as identification information.

FIG. 3 shows voltage-current characteristics with and without phase cut in this embodiment. Regarding the resistance RO, it is usually preferable that RO=R1, but it is not necessarily limited to this. That is, if RO<R2 is satisfied, sufficient effects can be obtained. The characteristics in Figure 3 are RO=
170Ω, R1=170Ω, Ra=600Ω, Rb=1
．． This is the result when Ω is set to 3. As shown in the figure, the voltage (
VPIN Vcc) -2.5V, a current of approximately 5 mA flows without phase cut, and a current of approximately 0.75 mA flows with phase cut.

This current difference makes it possible to reliably detect the presence or absence of a phase cut.

In order to detect the presence or absence of a phase cut based on the current difference as described above, it is desirable that Rinl is at least twice as large as R1n0. However, increasing the insertion resistance Rb to increase R2 is not preferable in terms of the operation of the DRAM chip. Therefore, RO and R
By making 1 as small as possible, it is desirable not to make the value of R2 too large. Then, by minimizing RO and R1 and setting R2 within a range that does not adversely affect the operation of the DRAM chip, the internal impedance ratio Rinl / R with and without phase cut can be adjusted.
It is possible to set 1nlo as large as about 1000.

FIG. 4 shows another embodiment. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In this embodiment, NM
A MOS diode in which an OS transistor is diode-connected is used. By setting the threshold value of the MOS1-transistor used at this time to be smaller than the forward voltage drop V of the pn diode, the effects of the present invention can be more fully exhibited.

FIG. 5 shows an example in which a phase path is provided on the side to vSS, and FIG. 6 shows a diode 32 in that case.
This is an embodiment in which n stages are connected in series.

In these embodiments as well, parts corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1.

FIG. 7 shows an embodiment in which an identification circuit is provided on the output circuit side. Here, the part corresponding to FIG. 9 which is a conventional example is shown in FIG.
The same reference numerals as in the figure are given. The output stage driver of the output circuit 12 is a PMOS transistor Qll and an NMOS)
It has a CMOS configuration of transistor Q12. In this case, the impedance as seen from the connection node N of the identification circuit 13 toward the identification circuit 13 side and the impedance seen from the output circuit 12 side are shown in the figure so that they satisfy the same relationship as in the embodiment shown in FIG. The resistors R1 and R2 (-Ra +Rb) are set. As a result, even though the output circuit 12 has a CMOS configuration, whether or not there is a phase cut can be determined from the output pin 1.
1 can be reliably detected.

The present invention is not limited to the above embodiments.

For example, the present invention can be applied to various semiconductor integrated circuits incorporating a DRAM-like redundant circuit system.

[Effects of the Invention] As described above, according to the present invention, identification information can be detected with sufficient detection sensitivity regardless of the input/output circuit configuration, and it is possible to determine whether or not a redundant circuit system is used. A semiconductor integrated circuit device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the identification circuit section of a DRAM according to an embodiment of the present invention, FIG. 2 is a diagram showing the layout of the DRAM, and FIG. 3 is a diagram showing voltage-current characteristics for identifying identification information. 4 is a diagram showing the configuration of the identification circuit section of a DRAM according to another embodiment. FIG. 5 is a diagram showing a DRAM of an embodiment provided with an identification circuit for VSS.
FIG. 6 is a diagram showing the configuration of the identification circuit section of a DRAM according to an embodiment that is slightly modified from FIG. 5, and FIG. 7 is an implementation in which the identification circuit is provided on the output circuit side. Example DR
A diagram showing the configuration of the AM identification circuit section, FIG. 8 is a diagram showing the configuration of the AM identification circuit section.
FIG. 9 is a diagram showing the configuration of the identification circuit section of the conventional DRAM, which has a problem. FIG. FIG. 3 is a diagram showing voltage-current characteristics. 1...Input bin, 2...Input circuit, 21.22...
・Protective diode, 3... Identification circuit, 31... Phase element, 32... Diode, N... Connection node, RO... Wiring resistance, R1... Identification circuit side equivalent resistance, R2 ...Equivalent resistance on the input circuit side, Ra...Wiring resistance, Rb...Insertion resistance, 4...DRAM chip, 5
...Memory array, 11...Output pin, 12...
Output circuit, Qll...PMOS transistor, Q12
...NMOS) transistor, 13...Identification circuit. Applicant's Representative Patent Attorney Takehiko Suzue 1 Figure X2 Figure VPIN -Vcc (V) Figure 3 Figure 5 Figure 8 Figure 9 Figure VPOOT -VCC (V) Figure 10

Claims (3)

[Claims] (1) It has a redundant circuit for relieving hard errors, and an identification circuit including a phase element and a diode for identifying whether or not the redundant circuit is used, which is connected to wiring connecting input/output pins and internal circuits. A semiconductor integrated circuit device, characterized in that impedance in the direction of the internal circuit from a connection node of the identification circuit on the wiring is set to be larger than impedance in the direction of the identification circuit. (2) A resistance element is interposed between the connection node and the internal circuit in order to set the impedance from the connection node in the direction of the internal circuit to be larger than the impedance in the direction of the identification circuit. The semiconductor integrated circuit device according to item 1. (3) The semiconductor integrated circuit device according to claim 1, wherein the impedance in the direction of the internal circuit from the connection node is set to be twice or more larger than the impedance in the direction of the identification circuit.