JPH0411798A - Manufacture of board with bump - Google Patents
Manufacture of board with bumpInfo
- Publication number
- JPH0411798A JPH0411798A JP11438490A JP11438490A JPH0411798A JP H0411798 A JPH0411798 A JP H0411798A JP 11438490 A JP11438490 A JP 11438490A JP 11438490 A JP11438490 A JP 11438490A JP H0411798 A JPH0411798 A JP H0411798A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- brazing
- electrode
- board
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000919 ceramic Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000005219 brazing Methods 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract 1
- 238000005245 sintering Methods 0.000 description 5
- 238000010304 firing Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910017309 Mo—Mn Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
５産業上の利用分野〕
本発明はバンプ付き基板の製造方法に間し、特にバンプ
の位置、高さ、および形状を高精度に形成する方法に関
する。DETAILED DESCRIPTION OF THE INVENTION 5. Field of Industrial Application The present invention relates to a method of manufacturing a bumped substrate, and particularly to a method of forming the position, height, and shape of bumps with high precision.
従来、この種のバンプ付きセラミック回路基板は、未焼
結のグリーンシートに導体ペーストを複数回印刷するこ
とによって所定の高さに盛り上げ、基板と一体に焼結し
てバンプ（突起電極）を形成し、さらにバンプ高さの不
均一を修正するため、先端を研磨加工する方法が一般的
であった。Conventionally, this type of ceramic circuit board with bumps was produced by printing conductive paste on an unsintered green sheet multiple times to raise it to a predetermined height, and then sintering it with the board to form bumps (protruding electrodes). However, in order to further correct unevenness in bump height, it has been common practice to polish the tips.
一方一、回路の高集積化にともなう接続端子数の増加に
より、バンプの一層の高密度化と高精度化が求められ、
これらに対応することを目的として、特開平１〜７７９
８９ 、実開平１−１１８４４０公報で金属ボールを使
用したバンプ形成に関する技術が提案されている。On the other hand, as the number of connection terminals increases due to higher integration of circuits, higher density and higher accuracy of bumps are required.
In order to respond to these issues,
No. 89, Japanese Utility Model Application Publication No. 1-118440 proposes a technique for forming bumps using metal balls.
しかしながら、前記した従来の方法によっても、セラミ
ック回路基板の焼成収縮のばらつきにともない、バンプ
位置精度がでないという間頚点がある。セラミック回路
基板の焼成収縮による寸法ばらつきは、通常０．５％〜
０．８％程度あるため、バンプの位置精度も同じばらつ
きを生じる。このバンプ付き基板は、マザーボードと呼
ばれるプリント回路基板の対応するパッド電極に、はん
だで接続される。パッド電極は一般に、フォトリソグラ
フィー法で形成され極めて高精度のため、バンプとの相
対位置のずれが、はんだの接続不良を発生させる。However, even with the above-mentioned conventional method, there is a drawback in that the bump position accuracy is not accurate due to variations in firing shrinkage of the ceramic circuit board. Dimensional variations due to firing shrinkage of ceramic circuit boards are usually 0.5% to
Since the difference is about 0.8%, the same variation occurs in the bump position accuracy. This bumped board is connected by solder to corresponding pad electrodes on a printed circuit board called a motherboard. Pad electrodes are generally formed by photolithography and have extremely high precision, so any deviation in their relative position to the bumps will cause poor solder connection.
また、基板焼結時に反りや歪みが発生し、バンプ高さが
不均一となるため先端を研磨して平均化することが必要
となる。この研磨によりバンプ形状か一定せず、はんだ
付着量にばらつきを生じ接続面の信頼性を低下させると
いう欠点があった。In addition, warpage and distortion occur during substrate sintering, resulting in non-uniform bump heights, which require polishing the tips to make them even. This polishing has disadvantages in that the shape of the bumps is not constant and the amount of solder deposited varies, reducing the reliability of the connection surface.
本発明はこれらの問題点を解決し、バンプの位置、高さ
、形状を高精度に形成する方法を提供することを目的と
する。It is an object of the present invention to solve these problems and provide a method for forming the position, height, and shape of bumps with high accuracy.
以上の目的を達成するため、この発明のバンプ付き基板
の製造方法は、焼結したセラミ・ツク回路基板のバンプ
形成面を研磨した後、バンプ形成部分にｔ８ｉを形成し
、この’ｔｉ上に金属導体をろう付けすることを特徴と
している。In order to achieve the above object, the method for manufacturing a bumped board of the present invention involves polishing the bump-forming surface of a sintered ceramic circuit board, forming t8i on the bump-forming part, and then polishing the bump-formed surface of the sintered ceramic circuit board. It is characterized by brazing metal conductors.
バンプの位置精度は、セラミック回路基板の焼成収縮ば
らつきの影響を受けず、金属導体のろう付は精度により
決定される。ろう付けの位置精度は精密に加工された治
具の精度により規定されるので、一般に高精度となる。The positional accuracy of the bump is not affected by variations in firing shrinkage of the ceramic circuit board, and brazing of the metal conductor is determined by the accuracy. The positional accuracy of brazing is determined by the accuracy of precisely machined jigs, so it is generally highly accurate.
バンプの高さは、セラミック回路基板のバンプ形成面を
研磨して、焼結時に発生する基板の反りや歪みを取り除
いた後、寸法、形状とも精度良く成形された金属導体を
ろう付けしてバンプ形成を行うので、高さ、形状ともに
高精度が保たれる。The height of the bump is determined by polishing the bump forming surface of the ceramic circuit board to remove warpage and distortion of the board that occurs during sintering, and then brazing a metal conductor that has been formed with precision in size and shape. Since it is formed, high precision in both height and shape can be maintained.
３実施例〕 以下、実施例により本発明を説明する。3 Examples] The present invention will be explained below with reference to Examples.
第１図（ａ）〜（ｄ）は本発明の一実施例であるバンプ
付き基板の製造方法を説明する図である。FIGS. 1(a) to 1(d) are diagrams illustrating a method for manufacturing a bumped substrate according to an embodiment of the present invention.
第１図（ａ）はバンプ付き基板を製造するため、グリー
ンシートに所定の導体回路パターンを形成した後、一体
に焼結されたセラミック回路基板ｌである。回路基板は
、一般に裏面にバンプを形成し、表面にはＩＣ（集積回
路）を搭載するための回路パターンや必要な導体配線が
形成される（図示せず）。FIG. 1(a) shows a ceramic circuit board l which is integrally sintered after forming a predetermined conductive circuit pattern on a green sheet in order to manufacture a board with bumps. A circuit board generally has bumps formed on its back surface, and a circuit pattern for mounting an IC (integrated circuit) and necessary conductor wiring on its front surface (not shown).
図に示すように、セラミック回路基板は、焼結時に若干
の反りや歪みを生じることが避けられず、後工程での問
題点発生の原因となる。As shown in the figure, it is inevitable that ceramic circuit boards will be slightly warped or distorted during sintering, which will cause problems in subsequent processes.
そのため、第１図（ｂ）で示すように、バンプ取り付は
面２となるセラミック回路基板の裏面側を研磨ライン３
まで研磨加工し、反りや歪みを取り除く。Therefore, as shown in FIG. 1(b), when attaching bumps, the back side of the ceramic circuit board, which is surface 2, is lined with a polishing line.
Polished to remove warping and distortion.
次に同図（ｃ）に示す通り、研磨加工した面のバンプ形
成部分に、金属導体をろう付けするための電極４を形成
する。電極４は、Ｍｏ−Ｍｎペーストを用いての厚膜手
法や、Ｔ ｉ ／ Ｍ ｏ ／ Ｃｕなどによる薄膜法
で形成する。電極はセラミックの一体焼結温度よりも低
い温度で焼き付は可能な導体材料を選択して使用するこ
とで、電極形成時の反りや歪みと、焼成収縮による寸法
ばらつきの再発生が防止できる。また、電極は、必要に
応じてメツキ処理などを行う。Next, as shown in FIG. 4(c), an electrode 4 for brazing a metal conductor is formed on the bump forming portion of the polished surface. The electrode 4 is formed by a thick film method using Mo-Mn paste or a thin film method using Ti/Mo/Cu or the like. By selecting and using a conductive material that can be baked at a temperature lower than the integral sintering temperature of the ceramic for the electrode, it is possible to prevent warping and distortion during electrode formation and the reoccurrence of dimensional variations due to firing shrinkage. Further, the electrodes are subjected to plating treatment, etc., as necessary.
次に、同図（ｄ）に示すように、形成した電極上に、所
望のバンプ形状、寸法に成形した金属導体５をろう付け
する。金属導体５は、Ｆｅ−Ｎｉ合金系、Ｍｏ系、Ｃｕ
、Ｃｕ−Ｗ系など、セラミック回路基板との膨張係数が
近く、ろう付けし易い材料から選択し、金属加工技術に
より寸法、形状とも精度良く成形したものをそのまま、
あるいは、メツキ処理して用いる。ろう付けは、通常用
いられる治具（図示せず）を使用して行うのが、バンプ
の位置精度、特にピッチ精度を高めるのに好適であり、
ろう材６は銀ろうが一般的である。Next, as shown in FIG. 4(d), a metal conductor 5 formed into a desired bump shape and size is brazed onto the formed electrode. The metal conductor 5 is made of Fe-Ni alloy, Mo, or Cu.
, Cu-W type, etc. are selected from materials that have an expansion coefficient close to that of the ceramic circuit board and are easy to braze, and are molded with precision in size and shape using metal processing technology.
Alternatively, use it after plating. It is suitable for brazing to be performed using a commonly used jig (not shown) in order to improve the positional accuracy of the bump, especially the pitch accuracy.
The brazing material 6 is generally silver solder.
また、回路基板は、アルミナ、ムライト、窒化アルミニ
ウム等のセラミックや、低温で焼成できるガラスセラミ
ック等を使うこともできる。この場合、電極材料はＡｇ
／Ｐｄ、Ｃｕを用い、ろう材にはＡｕ−３ｉ、Ａｕ−８
ｎが使用できる。Furthermore, the circuit board can also be made of ceramic such as alumina, mullite, or aluminum nitride, or glass ceramic that can be fired at low temperatures. In this case, the electrode material is Ag
/Pd, Cu, and the brazing filler metals are Au-3i and Au-8.
n can be used.
ｒ発明の効果〕
以−Ｅ説明した様に、本発明の方法で製造されたセラミ
ック回路基板は、バンプの位置、高さ、形状において精
度の一層の向上が可能となり、はんだ接続部の信頼性を
高め、回路のより大型化、高密度化に対応ができる。[Effects of the Invention] As explained below, the ceramic circuit board manufactured by the method of the present invention can further improve the accuracy of bump positions, heights, and shapes, and improves the reliability of soldered joints. It is possible to respond to larger circuits and higher density circuits.
また、セラミック回路基板のバンプ形成面が研磨加工さ
れ平坦なため、ＩＣの搭載工程で、反りによる基板のが
たつきや割れが防止できる効果がある。Furthermore, since the bump forming surface of the ceramic circuit board is polished and flat, it is effective in preventing rattling and cracking of the board due to warping during the IC mounting process.
（以下余白）(Margin below)
第１図（ａ）〜（ｄ）は、本発明の製造方法によりバン
プ付き基板を製造する工程図である。
１・・・セラミック回路基板 訃・・バンプ取り付は面
３・・・研磨ライン ４・・・電極 ５・・・金属導体
６・・・ろう材FIGS. 1(a) to 1(d) are process diagrams for manufacturing a bumped substrate by the manufacturing method of the present invention. 1... Ceramic circuit board - Bump attachment is on surface 3... Polishing line 4... Electrode 5... Metal conductor 6... Brazing metal
Claims (1)
磨した後、バンプ形成部分に電極を形成し、この電極上
に金属導体をろう付けすることを特徴とするバンプ付き
基板の製造方法。(1) A method for manufacturing a bumped board, which comprises polishing the bump-forming surface of a sintered ceramic circuit board, forming an electrode on the bump-forming portion, and brazing a metal conductor onto the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11438490A JPH0411798A (en) | 1990-04-28 | 1990-04-28 | Manufacture of board with bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11438490A JPH0411798A (en) | 1990-04-28 | 1990-04-28 | Manufacture of board with bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0411798A true JPH0411798A (en) | 1992-01-16 |
Family
ID=14636324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11438490A Pending JPH0411798A (en) | 1990-04-28 | 1990-04-28 | Manufacture of board with bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0411798A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006292067A (en) * | 2005-04-11 | 2006-10-26 | Taihei Dengyo Kaisha Ltd | Hydraulic circuit for high-pressure hydraulic system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649588A (en) * | 1979-09-28 | 1981-05-06 | Tokyo Shibaura Electric Co | Method of forming thin film for ceramic substrate |
| JPS6477989A (en) * | 1987-09-18 | 1989-03-23 | Fujitsu Ltd | Substrate having bump and manufacture thereof |
-
1990
- 1990-04-28 JP JP11438490A patent/JPH0411798A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649588A (en) * | 1979-09-28 | 1981-05-06 | Tokyo Shibaura Electric Co | Method of forming thin film for ceramic substrate |
| JPS6477989A (en) * | 1987-09-18 | 1989-03-23 | Fujitsu Ltd | Substrate having bump and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006292067A (en) * | 2005-04-11 | 2006-10-26 | Taihei Dengyo Kaisha Ltd | Hydraulic circuit for high-pressure hydraulic system |
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